Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-07 09:25:34 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

Merge pull request #379 from JoakimLarsson/z80scc_m166_3

Browse Source 
Z80scc m166 3
This commit is contained in:
R. Belmont 2015-10-13 16:33:22 -04:00
commit 4d9ab25ec8
4 changed files with 1780 additions and 1583 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

459
src/devices/machine/z80scc.c
View File

File diff suppressed because it is too large Load Diff

21
src/devices/machine/z80scc.h
View File

@ -108,7 +108,9 @@
class z80scc_device; class z80scc_device;
class z80scc_channel : public z80sio_channel //class z80scc_channel : public z80sio_channel
class z80scc_channel : public device_t,
public device_serial_interface
{ {
friend class z80scc_device; friend class z80scc_device;
@ -146,6 +148,7 @@ public:
// write register handlers // write register handlers
void do_sccreg_wr0(UINT8 data); void do_sccreg_wr0(UINT8 data);
void do_sccreg_wr0_resets(UINT8 data);
void do_sccreg_wr1(UINT8 data); void do_sccreg_wr1(UINT8 data);
void do_sccreg_wr2(UINT8 data); void do_sccreg_wr2(UINT8 data);
void do_sccreg_wr3(UINT8 data); void do_sccreg_wr3(UINT8 data);
@ -185,11 +188,9 @@ public:
// Register state // Register state
// read registers enum // read registers enum
#if 0 //defined by z80sio.h
UINT8 m_rr0; // REG_RR0_STATUS UINT8 m_rr0; // REG_RR0_STATUS
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
#endif
UINT8 m_rr3; // REG_RR3_INTERUPPT_PEND UINT8 m_rr3; // REG_RR3_INTERUPPT_PEND
UINT8 m_rr4; // REG_RR4_WR4_OR_RR0 UINT8 m_rr4; // REG_RR4_WR4_OR_RR0
UINT8 m_rr5; // REG_RR5_WR5_OR_RR0 UINT8 m_rr5; // REG_RR5_WR5_OR_RR0
@ -205,7 +206,6 @@ public:
UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT
// write registers enum // write registers enum
#if 0 //defined by z80sio.h
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
UINT8 m_wr2; // REG_WR2_INT_VECTOR UINT8 m_wr2; // REG_WR2_INT_VECTOR
@ -214,7 +214,6 @@ public:
UINT8 m_wr5; // REG_WR5_TX_CONTROL UINT8 m_wr5; // REG_WR5_TX_CONTROL
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
#endif
UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA
UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL
UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL
@ -506,7 +505,7 @@ protected:
// synchronous state // synchronous state
UINT16 m_sync; // sync character UINT16 m_sync; // sync character
// int m_index; int m_index;
z80scc_device *m_uart; z80scc_device *m_uart;
// SCC specifics // SCC specifics
@ -557,10 +556,11 @@ public:
DECLARE_READ8_MEMBER( ba_cd_r ); DECLARE_READ8_MEMBER( ba_cd_r );
DECLARE_WRITE8_MEMBER( ba_cd_w ); DECLARE_WRITE8_MEMBER( ba_cd_w );
DECLARE_READ8_MEMBER( da_r ) { return m_chanA->data_read(); } /* Definitions moved to z80scc.c for enhencements */
DECLARE_WRITE8_MEMBER( da_w ) { m_chanA->data_write(data); } DECLARE_READ8_MEMBER( da_r ); // { return m_chanA->data_read(); }
DECLARE_READ8_MEMBER( db_r ) { return m_chanB->data_read(); } DECLARE_WRITE8_MEMBER( da_w ); // { m_chanA->data_write(data); }
DECLARE_WRITE8_MEMBER( db_w ) { m_chanB->data_write(data); } DECLARE_READ8_MEMBER( db_r ); // { return m_chanB->data_read(); }
DECLARE_WRITE8_MEMBER( db_w ); // { m_chanB->data_write(data); }
DECLARE_READ8_MEMBER( ca_r ) { return m_chanA->control_read(); } DECLARE_READ8_MEMBER( ca_r ) { return m_chanA->control_read(); }
DECLARE_WRITE8_MEMBER( ca_w ) { m_chanA->control_write(data); } DECLARE_WRITE8_MEMBER( ca_w ) { m_chanA->control_write(data); }
@ -662,6 +662,7 @@ protected:
int m_int_state[6]; // interrupt state int m_int_state[6]; // interrupt state
int m_variant; int m_variant;
UINT8 m_wr0_ptrbits;
}; };
class scc8030_device : public z80scc_device class scc8030_device : public z80scc_device

130
src/devices/machine/z80sio.c
View File

@ -11,7 +11,7 @@
check that an operation is invalid because of package type but relies check that an operation is invalid because of package type but relies
on the software to be adapated for the particular version. on the software to be adapated for the particular version.
Package: DIP40 SIO/0, SIO/1, SIO/2, Package: DIP40 SIO/0, SIO/1, SIO/2, SIO/9
QFP44 SIO/3 QFP44 SIO/3
PLCC44 SIO/4 PLCC44 SIO/4
------------------------------------------------------------------- -------------------------------------------------------------------
@ -86,8 +86,8 @@ const device_type Z80SIO_CHANNEL = &device_creator<z80sio_channel>;
//------------------------------------------------- //-------------------------------------------------
MACHINE_CONFIG_FRAGMENT( z80sio ) MACHINE_CONFIG_FRAGMENT( z80sio )
MCFG_DEVICE_ADD(CHANA_TAG, Z80SIO_CHANNEL, 0) MCFG_DEVICE_ADD(CHANA_TAG, Z80SIO_CHANNEL, 0)
MCFG_DEVICE_ADD(CHANB_TAG, Z80SIO_CHANNEL, 0) MCFG_DEVICE_ADD(CHANB_TAG, Z80SIO_CHANNEL, 0)
MACHINE_CONFIG_END MACHINE_CONFIG_END
machine_config_constructor z80sio_device::device_mconfig_additions() const machine_config_constructor z80sio_device::device_mconfig_additions() const
@ -166,7 +166,6 @@ z80sio_device::z80sio_device(const machine_config &mconfig, const char *tag, dev
//------------------------------------------------- //-------------------------------------------------
// device_start - device-specific startup // device_start - device-specific startup
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::device_start() void z80sio_device::device_start()
{ {
LOG(("%s\n", FUNCNAME)); LOG(("%s\n", FUNCNAME));
@ -203,7 +202,6 @@ void z80sio_device::device_start()
//------------------------------------------------- //-------------------------------------------------
// device_reset - device-specific reset // device_reset - device-specific reset
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::device_reset() void z80sio_device::device_reset()
{ {
LOG(("%s \"%s\" \n", FUNCNAME, tag())); LOG(("%s \"%s\" \n", FUNCNAME, tag()));
@ -215,13 +213,13 @@ void z80sio_device::device_reset()
//------------------------------------------------- //-------------------------------------------------
// z80daisy_irq_state - get interrupt status // z80daisy_irq_state - get interrupt status
//------------------------------------------------- //-------------------------------------------------
int z80sio_device::z80daisy_irq_state() int z80sio_device::z80daisy_irq_state()
{ {
int state = 0; int state = 0;
int i; int i;
LOG(("Z80SIO \"%s\" : Interrupt State A:%d%d%d%d B:%d%d%d%d\n", tag(),
LOG(("%s %s A:%d%d%d%d B:%d%d%d%d ",FUNCNAME, tag(),
m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3], m_int_state[0], m_int_state[1], m_int_state[2], m_int_state[3],
m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7])); m_int_state[4], m_int_state[5], m_int_state[6], m_int_state[7]));
@ -237,7 +235,7 @@ int z80sio_device::z80daisy_irq_state()
state |= m_int_state[i]; state |= m_int_state[i];
} }
LOG(("Z80SIO \"%s\" : Interrupt State %u\n", tag(), state)); LOG(("Interrupt State %u\n", state));
return state; return state;
} }
@ -246,12 +244,11 @@ int z80sio_device::z80daisy_irq_state()
//------------------------------------------------- //-------------------------------------------------
// z80daisy_irq_ack - interrupt acknowledge // z80daisy_irq_ack - interrupt acknowledge
//------------------------------------------------- //-------------------------------------------------
int z80sio_device::z80daisy_irq_ack() int z80sio_device::z80daisy_irq_ack()
{ {
int i; int i;
LOG(("Z80SIO \"%s\" Interrupt Acknowledge\n", tag())); LOG(("%s %s \n",FUNCNAME, tag()));
// loop over all interrupt sources // loop over all interrupt sources
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
@ -264,7 +261,7 @@ int z80sio_device::z80daisy_irq_ack()
m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING; m_chanA->m_rr0 &= ~z80sio_channel::RR0_INTERRUPT_PENDING;
check_interrupts(); check_interrupts();
LOG(("Z80SIO \"%s\" : Interrupt Acknowledge Vector %02x\n", tag(), m_chanB->m_rr2)); //LOG(("%s %s \n",FUNCNAME, tag(), m_chanB->m_rr2));
return m_chanB->m_rr2; return m_chanB->m_rr2;
} }
@ -279,12 +276,11 @@ int z80sio_device::z80daisy_irq_ack()
//------------------------------------------------- //-------------------------------------------------
// z80daisy_irq_reti - return from interrupt // z80daisy_irq_reti - return from interrupt
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::z80daisy_irq_reti() void z80sio_device::z80daisy_irq_reti()
{ {
int i; int i;
LOG(("Z80SIO \"%s\" Return from Interrupt\n", tag())); LOG(("%s %s \n",FUNCNAME, tag()));
// loop over all interrupt sources // loop over all interrupt sources
for (i = 0; i < 8; i++) for (i = 0; i < 8; i++)
@ -306,9 +302,9 @@ void z80sio_device::z80daisy_irq_reti()
//------------------------------------------------- //-------------------------------------------------
// check_interrupts - // check_interrupts -
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::check_interrupts() void z80sio_device::check_interrupts()
{ {
LOG(("%s %s \n",FUNCNAME, tag()));
int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE; int state = (z80daisy_irq_state() & Z80_DAISY_INT) ? ASSERT_LINE : CLEAR_LINE;
m_out_int_cb(state); m_out_int_cb(state);
} }
@ -317,9 +313,10 @@ void z80sio_device::check_interrupts()
//------------------------------------------------- //-------------------------------------------------
// reset_interrupts - // reset_interrupts -
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::reset_interrupts() void z80sio_device::reset_interrupts()
{ {
LOG(("%s %s \n",FUNCNAME, tag()));
// reset internal interrupt sources
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
m_int_state[i] = 0; m_int_state[i] = 0;
@ -332,12 +329,13 @@ void z80sio_device::reset_interrupts()
//------------------------------------------------- //-------------------------------------------------
// trigger_interrupt - TODO: needs attention for SIO // trigger_interrupt - TODO: needs attention for SIO
//------------------------------------------------- //-------------------------------------------------
void z80sio_device::trigger_interrupt(int index, int state) void z80sio_device::trigger_interrupt(int index, int state)
{ {
UINT8 vector = m_chanB->m_wr2; UINT8 vector = m_chanB->m_wr2;
int priority; int priority;
LOG(("%s %s \n",FUNCNAME, tag()));
#if 0 #if 0
if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201)) if((m_variant == TYPE_I8274) || (m_variant == TYPE_UPD7201))
{ {
@ -387,9 +385,6 @@ void z80sio_device::trigger_interrupt(int index, int state)
vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1); vector = (m_chanB->m_wr2 & 0xf1) | (!index << 3) | (state << 1);
} }
// } // }
LOG(("Z80SIO \"%s\" Channel %c : Interrupt Request %u\n", tag(), 'A' + index, state));
// update vector register // update vector register
m_chanB->m_rr2 = vector; m_chanB->m_rr2 = vector;
@ -405,9 +400,9 @@ void z80sio_device::trigger_interrupt(int index, int state)
//------------------------------------------------- //-------------------------------------------------
// m1_r - interrupt acknowledge // m1_r - interrupt acknowledge
//------------------------------------------------- //-------------------------------------------------
int z80sio_device::m1_r() int z80sio_device::m1_r()
{ {
LOG(("%s %s \n",FUNCNAME, tag()));
return z80daisy_irq_ack(); return z80daisy_irq_ack();
} }
@ -415,14 +410,13 @@ int z80sio_device::m1_r()
//------------------------------------------------- //-------------------------------------------------
// cd_ba_r - // cd_ba_r -
//------------------------------------------------- //-------------------------------------------------
READ8_MEMBER( z80sio_device::cd_ba_r ) READ8_MEMBER( z80sio_device::cd_ba_r )
{ {
int ba = BIT(offset, 0); int ba = BIT(offset, 0);
int cd = BIT(offset, 1); int cd = BIT(offset, 1);
z80sio_channel *channel = ba ? m_chanB : m_chanA; z80sio_channel *channel = ba ? m_chanB : m_chanA;
// LOG(("z80sio_device::cd_ba_r ba:%02x cd:%02x\n", ba, cd)); //LOG(("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ));
return cd ? channel->control_read() : channel->data_read(); return cd ? channel->control_read() : channel->data_read();
} }
@ -431,14 +425,13 @@ READ8_MEMBER( z80sio_device::cd_ba_r )
//------------------------------------------------- //-------------------------------------------------
// cd_ba_w - // cd_ba_w -
//------------------------------------------------- //-------------------------------------------------
WRITE8_MEMBER( z80sio_device::cd_ba_w ) WRITE8_MEMBER( z80sio_device::cd_ba_w )
{ {
int ba = BIT(offset, 0); int ba = BIT(offset, 0);
int cd = BIT(offset, 1); int cd = BIT(offset, 1);
z80sio_channel *channel = ba ? m_chanB : m_chanA; z80sio_channel *channel = ba ? m_chanB : m_chanA;
LOG(("z80sio_device::cd_ba_w ba:%02x cd:%02x\n", ba, cd)); LOG(("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ));
if (cd) if (cd)
channel->control_write(data); channel->control_write(data);
@ -450,14 +443,13 @@ WRITE8_MEMBER( z80sio_device::cd_ba_w )
//------------------------------------------------- //-------------------------------------------------
// ba_cd_r - // ba_cd_r -
//------------------------------------------------- //-------------------------------------------------
READ8_MEMBER( z80sio_device::ba_cd_r ) READ8_MEMBER( z80sio_device::ba_cd_r )
{ {
int ba = BIT(offset, 1); int ba = BIT(offset, 1);
int cd = BIT(offset, 0); int cd = BIT(offset, 0);
z80sio_channel *channel = ba ? m_chanB : m_chanA; z80sio_channel *channel = ba ? m_chanB : m_chanA;
// LOG(("z80sio_device::ba_cd_r ba:%02x cd:%02x\n", ba, cd)); //LOG(("%s %s %c %s read\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ));
return cd ? channel->control_read() : channel->data_read(); return cd ? channel->control_read() : channel->data_read();
} }
@ -466,14 +458,13 @@ READ8_MEMBER( z80sio_device::ba_cd_r )
//------------------------------------------------- //-------------------------------------------------
// ba_cd_w - // ba_cd_w -
//------------------------------------------------- //-------------------------------------------------
WRITE8_MEMBER( z80sio_device::ba_cd_w ) WRITE8_MEMBER( z80sio_device::ba_cd_w )
{ {
int ba = BIT(offset, 1); int ba = BIT(offset, 1);
int cd = BIT(offset, 0); int cd = BIT(offset, 0);
z80sio_channel *channel = ba ? m_chanB : m_chanA; z80sio_channel *channel = ba ? m_chanB : m_chanA;
LOG(("z80sio_device::ba_cd_w ba:%02x cd:%02x\n", ba, cd)); LOG(("%s %s %c %s write\n",FUNCNAME, tag(), 'A' + ba ? 1 : 0 , cd ? "control" : "data" ));
if (cd) if (cd)
channel->control_write(data); channel->control_write(data);
@ -488,7 +479,6 @@ WRITE8_MEMBER( z80sio_device::ba_cd_w )
//------------------------------------------------- //-------------------------------------------------
// z80sio_channel - constructor // z80sio_channel - constructor
//------------------------------------------------- //-------------------------------------------------
z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, Z80SIO_CHANNEL, "Z80 SIO channel", tag, owner, clock, "z80sio_channel", __FILE__), : device_t(mconfig, Z80SIO_CHANNEL, "Z80 SIO channel", tag, owner, clock, "z80sio_channel", __FILE__),
device_serial_interface(mconfig, *this), device_serial_interface(mconfig, *this),
@ -508,6 +498,7 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d
m_rts(0), m_rts(0),
m_sync(0) m_sync(0)
{ {
LOG(("%s\n",FUNCNAME));
// Reset all registers // Reset all registers
m_rr0 = m_rr1 = m_rr2 = 0; m_rr0 = m_rr1 = m_rr2 = 0;
m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0; m_wr0 = m_wr1 = m_wr2 = m_wr3 = m_wr4 = m_wr5 = m_wr6 = m_wr7 = 0;
@ -523,12 +514,12 @@ z80sio_channel::z80sio_channel(const machine_config &mconfig, const char *tag, d
//------------------------------------------------- //-------------------------------------------------
// start - channel startup // start - channel startup
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::device_start() void z80sio_channel::device_start()
{ {
LOG(("%s\n",FUNCNAME)); LOG(("%s\n",FUNCNAME));
m_uart = downcast<z80sio_device *>(owner()); m_uart = downcast<z80sio_device *>(owner());
m_index = m_uart->get_channel_index(this); m_index = m_uart->get_channel_index(this);
m_variant = ((z80sio_device *)m_owner)->m_variant;
// state saving // state saving
save_item(NAME(m_rr0)); save_item(NAME(m_rr0));
@ -558,6 +549,7 @@ void z80sio_channel::device_start()
save_item(NAME(m_dtr)); save_item(NAME(m_dtr));
save_item(NAME(m_rts)); save_item(NAME(m_rts));
save_item(NAME(m_sync)); save_item(NAME(m_sync));
save_item(NAME(m_variant));
device_serial_interface::register_save_state(machine().save(), this); device_serial_interface::register_save_state(machine().save(), this);
} }
@ -565,10 +557,11 @@ void z80sio_channel::device_start()
//------------------------------------------------- //-------------------------------------------------
// reset - reset channel status // reset - reset channel status
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::device_reset() void z80sio_channel::device_reset()
{ {
LOG(("%s\n", FUNCNAME)); LOG(("%s\n", FUNCNAME));
// Reset RS232 emulation
receive_register_reset(); receive_register_reset();
transmit_register_reset(); transmit_register_reset();
@ -596,15 +589,14 @@ void z80sio_channel::device_timer(emu_timer &timer, device_timer_id id, int para
device_serial_interface::device_timer(timer, id, param, ptr); device_serial_interface::device_timer(timer, id, param, ptr);
} }
//------------------------------------------------- //-------------------------------------------------
// tra_callback - // tra_callback -
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::tra_callback() void z80sio_channel::tra_callback()
{ {
if (!(m_wr5 & WR5_TX_ENABLE)) if (!(m_wr5 & WR5_TX_ENABLE))
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
// transmit mark // transmit mark
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(1); m_uart->m_out_txda_cb(1);
@ -613,6 +605,7 @@ void z80sio_channel::tra_callback()
} }
else if (m_wr5 & WR5_SEND_BREAK) else if (m_wr5 & WR5_SEND_BREAK)
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c send break 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
// transmit break // transmit break
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(0); m_uart->m_out_txda_cb(0);
@ -621,11 +614,19 @@ void z80sio_channel::tra_callback()
} }
else if (!is_transmit_register_empty()) else if (!is_transmit_register_empty())
{ {
int db = transmit_register_get_data_bit();
LOG(("%" I64FMT "d %s() \"%s \"Channel %c transmit data bit %d m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, db, m_wr5));
// transmit data // transmit data
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(transmit_register_get_data_bit()); m_uart->m_out_txda_cb(db);
else else
m_uart->m_out_txdb_cb(transmit_register_get_data_bit()); m_uart->m_out_txdb_cb(db);
}
else
{
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Failed to transmit m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
logerror("%s \"%s \"Channel %c Failed to transmit\n", FUNCNAME, m_owner->tag(), 'A' + m_index);
} }
} }
@ -633,12 +634,12 @@ void z80sio_channel::tra_callback()
//------------------------------------------------- //-------------------------------------------------
// tra_complete - // tra_complete -
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::tra_complete() void z80sio_channel::tra_complete()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY)) if ((m_wr5 & WR5_TX_ENABLE) && !(m_wr5 & WR5_SEND_BREAK) && !(m_rr0 & RR0_TX_BUFFER_EMPTY))
{ {
LOG(("Z80SIO \"%s\" Channel %c : Transmit Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, m_tx_data)); LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Data Byte '%02x' m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_tx_data, m_wr5));
transmit_register_setup(m_tx_data); transmit_register_setup(m_tx_data);
@ -650,6 +651,7 @@ void z80sio_channel::tra_complete()
} }
else if (m_wr5 & WR5_SEND_BREAK) else if (m_wr5 & WR5_SEND_BREAK)
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Break 0 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
// transmit break // transmit break
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(0); m_uart->m_out_txda_cb(0);
@ -658,6 +660,7 @@ void z80sio_channel::tra_complete()
} }
else else
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit Mark 1 m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
// transmit mark // transmit mark
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_txda_cb(1); m_uart->m_out_txda_cb(1);
@ -668,6 +671,7 @@ void z80sio_channel::tra_complete()
// if transmit buffer is empty // if transmit buffer is empty
if (m_rr0 & RR0_TX_BUFFER_EMPTY) if (m_rr0 & RR0_TX_BUFFER_EMPTY)
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Transmit buffer empty m_wr5:%02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_wr5));
// then all characters have been sent // then all characters have been sent
m_rr1 |= RR1_ALL_SENT; m_rr1 |= RR1_ALL_SENT;
@ -681,24 +685,34 @@ void z80sio_channel::tra_complete()
//------------------------------------------------- //-------------------------------------------------
// rcv_callback - // rcv_callback -
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::rcv_callback() void z80sio_channel::rcv_callback()
{ {
if (m_wr3 & WR3_RX_ENABLE) if (m_wr3 & WR3_RX_ENABLE)
{ {
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit %d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, m_rxd));
receive_register_update_bit(m_rxd); receive_register_update_bit(m_rxd);
} }
#if 0
else
{
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data Bit but receiver is disabled\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index));
logerror("Z80SIO %s() \"%s \"Channel %c Received data dit but receiver is disabled\n", __func__, m_owner->tag(), 'A' + m_index);
}
#endif
} }
//------------------------------------------------- //-------------------------------------------------
// rcv_complete - // rcv_complete -
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::rcv_complete() void z80sio_channel::rcv_complete()
{ {
UINT8 data;
receive_register_extract(); receive_register_extract();
receive_data(get_received_char()); data = get_received_char();
LOG(("%" I64FMT "d %s() \"%s \"Channel %c Received Data %02x\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, data));
receive_data(data);
} }
@ -708,6 +722,7 @@ void z80sio_channel::rcv_complete()
int z80sio_channel::get_clock_mode() int z80sio_channel::get_clock_mode()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
int clocks = 1; int clocks = 1;
switch (m_wr4 & WR4_CLOCK_RATE_MASK) switch (m_wr4 & WR4_CLOCK_RATE_MASK)
@ -734,6 +749,7 @@ CR5 = m_wr5 and SR1 = m_rr1
void z80sio_channel::set_rts(int state) void z80sio_channel::set_rts(int state)
{ {
LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index));
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)
m_uart->m_out_rtsa_cb(state); m_uart->m_out_rtsa_cb(state);
else else
@ -742,6 +758,8 @@ void z80sio_channel::set_rts(int state)
void z80sio_channel::update_rts() void z80sio_channel::update_rts()
{ {
// LOG(("%s(%d) \"%s\" Channel %c \n", FUNCNAME, state, m_owner->tag(), 'A' + m_index));
LOG(("%s() \"%s\" Channel %c \n", FUNCNAME, m_owner->tag(), 'A' + m_index));
if (m_wr5 & WR5_RTS) if (m_wr5 & WR5_RTS)
{ {
// when the RTS bit is set, the _RTS output goes low // when the RTS bit is set, the _RTS output goes low
@ -764,6 +782,7 @@ void z80sio_channel::update_rts()
device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits() device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
switch (m_wr4 & WR4_STOP_BITS_MASK) switch (m_wr4 & WR4_STOP_BITS_MASK)
{ {
case WR4_STOP_BITS_1: return STOP_BITS_1; case WR4_STOP_BITS_1: return STOP_BITS_1;
@ -781,6 +800,7 @@ device_serial_interface::stop_bits_t z80sio_channel::get_stop_bits()
int z80sio_channel::get_rx_word_length() int z80sio_channel::get_rx_word_length()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
int bits = 5; int bits = 5;
switch (m_wr3 & WR3_RX_WORD_LENGTH_MASK) switch (m_wr3 & WR3_RX_WORD_LENGTH_MASK)
@ -801,6 +821,7 @@ int z80sio_channel::get_rx_word_length()
int z80sio_channel::get_tx_word_length() int z80sio_channel::get_tx_word_length()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
int bits = 5; int bits = 5;
switch (m_wr5 & WR5_TX_WORD_LENGTH_MASK) switch (m_wr5 & WR5_TX_WORD_LENGTH_MASK)
@ -820,6 +841,7 @@ int z80sio_channel::get_tx_word_length()
* Break/Abort latch. */ * Break/Abort latch. */
UINT8 z80sio_channel::do_sioreg_rr0() UINT8 z80sio_channel::do_sioreg_rr0()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
return m_rr0; return m_rr0;
} }
/* /*
@ -827,6 +849,7 @@ UINT8 z80sio_channel::do_sioreg_rr0()
* codes for the I-Field in the SDLC Receive Mode. */ * codes for the I-Field in the SDLC Receive Mode. */
UINT8 z80sio_channel::do_sioreg_rr1() UINT8 z80sio_channel::do_sioreg_rr1()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
return m_rr1; return m_rr1;
} }
/* /*
@ -839,6 +862,7 @@ no interrupts are pending, the vector is modified with V3 = 0, V2 = 1, and
V1 = 1. This register is read only through Channel B. */ V1 = 1. This register is read only through Channel B. */
UINT8 z80sio_channel::do_sioreg_rr2() UINT8 z80sio_channel::do_sioreg_rr2()
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
// channel B only // channel B only
return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0; return m_index == z80sio_device::CHANNEL_B ? m_rr2 : 0;
} }
@ -853,6 +877,7 @@ UINT8 z80sio_channel::control_read()
UINT8 data = 0; UINT8 data = 0;
UINT8 reg = m_wr0 & WR0_REGISTER_MASK; UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
//LOG(("%s %s\n",FUNCNAME, tag()));
if (reg != 0) if (reg != 0)
{ {
// mask out register index // mask out register index
@ -866,16 +891,17 @@ UINT8 z80sio_channel::control_read()
case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break; case REG_RR2_INTERRUPT_VECT: data = do_sioreg_rr2(); break;
default: default:
logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg); logerror("Z80SIO \"%s\" Channel %c : Unsupported RRx register:%02x\n", m_owner->tag(), 'A' + m_index, reg);
LOG(("%s %s unsupported register:%02x\n",FUNCNAME, tag(), reg));
} }
//LOG(("Z80SIO \"%s\" Channel %c : Register R%d read '%02x'\n", m_owner->tag(), 'A' + m_index, reg, data));
return data; return data;
} }
/* SIO CRC Initialization Code handling /* SIO CRC Initialization Code handling - candidate for breaking out in a z80sio_base class
Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */ Handle the WR0 CRC Reset/Init bits separatelly, needed by derived devices separatelly from the commands */
void z80sio_channel::do_sioreg_wr0_resets(UINT8 data) void z80sio_channel::do_sioreg_wr0_resets(UINT8 data)
{ {
LOG(("%s %s\n",FUNCNAME, tag()));
switch (data & WR0_CRC_RESET_CODE_MASK) switch (data & WR0_CRC_RESET_CODE_MASK)
{ {
case WR0_CRC_RESET_NULL: case WR0_CRC_RESET_NULL:
@ -894,6 +920,7 @@ void z80sio_channel::do_sioreg_wr0_resets(UINT8 data)
logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK); logerror("Z80SIO \"%s\" Channel %c : %s Wrong CRC reset/init command:%02x\n", m_owner->tag(), 'A' + m_index, FUNCNAME, data & WR0_CRC_RESET_CODE_MASK);
} }
} }
void z80sio_channel::do_sioreg_wr0(UINT8 data) void z80sio_channel::do_sioreg_wr0(UINT8 data)
{ {
m_wr0 = data; m_wr0 = data;
@ -1033,7 +1060,6 @@ void z80sio_channel::do_sioreg_wr7(UINT8 data)
//------------------------------------------------- //-------------------------------------------------
// control_write - write control register // control_write - write control register
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::control_write(UINT8 data) void z80sio_channel::control_write(UINT8 data)
{ {
UINT8 reg = m_wr0 & WR0_REGISTER_MASK; UINT8 reg = m_wr0 & WR0_REGISTER_MASK;
@ -1044,7 +1070,7 @@ void z80sio_channel::control_write(UINT8 data)
m_wr0 &= ~WR0_REGISTER_MASK; m_wr0 &= ~WR0_REGISTER_MASK;
} }
LOG(("Z80SIO control_write reg %02x, regmask %02x, WR0 %02x, data %02x\n", reg, WR0_REGISTER_MASK, m_wr0, data)); LOG(("\n%s(%02x) reg %02x\n", FUNCNAME, data, reg));
switch (reg) switch (reg)
{ {
@ -1065,7 +1091,6 @@ void z80sio_channel::control_write(UINT8 data)
//------------------------------------------------- //-------------------------------------------------
// data_read - read data register // data_read - read data register
//------------------------------------------------- //-------------------------------------------------
UINT8 z80sio_channel::data_read() UINT8 z80sio_channel::data_read()
{ {
UINT8 data = 0; UINT8 data = 0;
@ -1097,7 +1122,6 @@ UINT8 z80sio_channel::data_read()
//------------------------------------------------- //-------------------------------------------------
// data_write - write data register // data_write - write data register
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::data_write(UINT8 data) void z80sio_channel::data_write(UINT8 data)
{ {
m_tx_data = data; m_tx_data = data;
@ -1116,25 +1140,24 @@ void z80sio_channel::data_write(UINT8 data)
} }
else else
{ {
LOG((" Transmitter %s, data byte dropped\n", m_wr5 & WR5_TX_ENABLE ? "not enabled" : "not emptied"));
m_rr0 &= ~RR0_TX_BUFFER_EMPTY; m_rr0 &= ~RR0_TX_BUFFER_EMPTY;
} }
m_rr1 &= ~RR1_ALL_SENT; m_rr1 &= ~RR1_ALL_SENT;
LOG(("Z80SIO \"%s\" Channel %c : Data Register Write '%02x'\n", m_owner->tag(), 'A' + m_index, data));
} }
//------------------------------------------------- //-------------------------------------------------
// receive_data - receive data word // receive_data - receive data word
//------------------------------------------------- //-------------------------------------------------
void z80sio_channel::receive_data(UINT8 data) void z80sio_channel::receive_data(UINT8 data)
{ {
LOG(("Z80SIO \"%s\" Channel %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data)); LOG(("%s(%02x) %s:%c\n",FUNCNAME, data, tag(), 'A' + m_index));
if (m_rx_fifo == 2) if (m_rx_fifo == 2)
{ {
LOG((" Overrun detected\n"));
// receive overrun error detected // receive overrun error detected
m_rx_error |= RR1_RX_OVERRUN_ERROR; m_rx_error |= RR1_RX_OVERRUN_ERROR;
@ -1171,7 +1194,6 @@ void z80sio_channel::receive_data(UINT8 data)
if (m_rx_first) if (m_rx_first)
{ {
m_uart->trigger_interrupt(m_index, INT_RECEIVE); m_uart->trigger_interrupt(m_index, INT_RECEIVE);
m_rx_first = 0; m_rx_first = 0;
} }
break; break;
@ -1180,6 +1202,9 @@ void z80sio_channel::receive_data(UINT8 data)
case WR1_RX_INT_ALL: case WR1_RX_INT_ALL:
m_uart->trigger_interrupt(m_index, INT_RECEIVE); m_uart->trigger_interrupt(m_index, INT_RECEIVE);
break; break;
default:
LOG(("No interrupt triggered\n"));
} }
} }
@ -1190,7 +1215,7 @@ void z80sio_channel::receive_data(UINT8 data)
WRITE_LINE_MEMBER( z80sio_channel::cts_w ) WRITE_LINE_MEMBER( z80sio_channel::cts_w )
{ {
LOG(("Z80SIO \"%s\" Channel %c : CTS %u\n", m_owner->tag(), 'A' + m_index, state)); LOG(("%s(%02x) %s:%c\n",FUNCNAME, state, tag(), 'A' + m_index));
if (m_cts != state) if (m_cts != state)
{ {
@ -1382,6 +1407,7 @@ void z80sio_channel::update_serial()
void z80sio_channel::set_dtr(int state) void z80sio_channel::set_dtr(int state)
{ {
LOG(("%s(%d)\n", FUNCNAME, state));
m_dtr = state; m_dtr = state;
if (m_index == z80sio_device::CHANNEL_A) if (m_index == z80sio_device::CHANNEL_A)

3
src/devices/machine/z80sio.h
View File

@ -403,7 +403,7 @@ class z80sio_device : public device_t,
{ {
friend class z80sio_channel; friend class z80sio_channel;
public: public:
// construction/destruction // construction/destruction
z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source); z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
@ -523,7 +523,6 @@ protected:
devcb_write_line m_out_txdrqb_cb; devcb_write_line m_out_txdrqb_cb;
int m_int_state[8]; // interrupt state int m_int_state[8]; // interrupt state
int m_variant; int m_variant;
}; };