srcclean in preparation for 0.241 release

This commit is contained in:
Vas Crabb 2022-02-20 19:10:34 +11:00
parent 02d29b771a
commit 4dff3746fe
21 changed files with 132 additions and 132 deletions

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@ -273977,8 +273977,8 @@ license:CC0
<!-- Project 2612 VGM Archives located at http://project2612.org/list.php <!-- Project 2612 VGM Archives located at http://project2612.org/list.php
Also https://archive.org/details/Project2612CompleteArchive20180623681Sets.7z Also https://archive.org/details/Project2612CompleteArchive20180623681Sets.7z
Integrated into VGMRIPS site (entries yet to be verified/confirmed) --> Integrated into VGMRIPS site (entries yet to be verified/confirmed) -->
<software name="16ton_md"> <software name="16ton_md">
<description>16t (GEN/MD)</description> <description>16t (GEN/MD)</description>

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@ -9,25 +9,25 @@
32k ram 32k ram
32k eprom 32k eprom
15.6672Mhz crystal 15.6672Mhz crystal
SWIM 1 Chip (1987) SWIM 1 Chip (1987)
65c02 processor (~2mhz) 65c02 processor (~2mhz)
uc: uc:
$0000-$7fff is ram $0000-$7fff is ram
$8000-$ffff is rom $8000-$ffff is rom
$0a00-$0aff is i/o $0a00-$0aff is i/o
apple 2 bus: apple 2 bus:
$c0n0-$c0nf - memory latch. selects a 1k window for $c800-$cbff $c0n0-$c0nf - memory latch. selects a 1k window for $c800-$cbff
$cn00-$cnff - uc ram ($7b00-$7bff) $cn00-$cnff - uc ram ($7b00-$7bff)
$c800-$cbff - uc ram ($0000-$3cff, based on memory latch) $c800-$cbff - uc ram ($0000-$3cff, based on memory latch)
$cc00-$cfff - uc ram ($7c00-$7fff) $cc00-$cfff - uc ram ($7c00-$7fff)
spamming Control-D while booting will invoke the built-in spamming Control-D while booting will invoke the built-in
diagnostics. An alternative entry is Cx0DG from the monitor. diagnostics. An alternative entry is Cx0DG from the monitor.
*********************************************************************/ *********************************************************************/

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@ -3344,7 +3344,7 @@ void nes_bmc_891227_device::write_h(offs_t offset, u8 data)
LOG_MMC(("bmc_891227 write_h, offset: %04x, data: %02x\n", offset, data)); LOG_MMC(("bmc_891227 write_h, offset: %04x, data: %02x\n", offset, data));
if (offset < 0x4000) if (offset < 0x4000)
data = (data & 0x80) >> 2 | (data & 0x60) << 1 | (data & 0x1f); data = (data & 0x80) >> 2 | (data & 0x60) << 1 | (data & 0x1f);
nes_bmc_ctc12in1_device::write_h(offset, data); nes_bmc_ctc12in1_device::write_h(offset, data);

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@ -53,7 +53,7 @@ void nscsi_s1410_device::scsi_command()
scsi_data_in(SBUF_SENSE, 4); scsi_data_in(SBUF_SENSE, 4);
scsi_status_complete(SS_GOOD); scsi_status_complete(SS_GOOD);
break; break;
case SC_FORMAT_UNIT: case SC_FORMAT_UNIT:
LOG("command FORMAT UNIT\n"); LOG("command FORMAT UNIT\n");
{ {

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@ -147,7 +147,7 @@ void nesapu_device::device_start()
/* /*
pulse channel output: pulse channel output:
95.88 95.88
----------------------- -----------------------
8128 8128
----------------- + 100 ----------------- + 100
@ -163,7 +163,7 @@ void nesapu_device::device_start()
/* /*
triangle, noise, DMC channel output: triangle, noise, DMC channel output:
159.79 159.79
------------------------------- -------------------------------
1 1
------------------------- + 100 ------------------------- + 100

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@ -18,7 +18,7 @@
"determines if slot output is accumulated(1), or output directly(0)" "determines if slot output is accumulated(1), or output directly(0)"
- Is memory handling 100% correct? At the moment, seibuspi.cpp is the only - Is memory handling 100% correct? At the moment, seibuspi.cpp is the only
hardware currently emulated that uses external handlers. hardware currently emulated that uses external handlers.
- *16 multiplier for timer B is free-running like other yamaha FM chips? - *16 multiplier for timer B is free-running like other yamaha FM chips?
*/ */
#include "emu.h" #include "emu.h"
@ -254,10 +254,10 @@ inline void ymf271_device::calculate_status_end(int slotnum, bool state)
return; return;
/* /*
bit scheme is kinda twisted bit scheme is kinda twisted
status1 Busy End36 End24 End12 End0 ---- TimB TimA status1 Busy End36 End24 End12 End0 ---- TimB TimA
status2 End44 End32 End20 End8 End40 End28 End16 End4 status2 End44 End32 End20 End8 End40 End28 End16 End4
*/ */
uint8_t subbit = slotnum / 12; uint8_t subbit = slotnum / 12;
uint8_t bankbit = ((slotnum % 12) >> 2); uint8_t bankbit = ((slotnum % 12) >> 2);

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@ -7,7 +7,7 @@
TODO: TODO:
- Use NSCSI instead of legacy one; - Use NSCSI instead of legacy one;
- Convert base mapping to address_map; - Convert base mapping to address_map;
- Convert I/O to space address, and make it honor mem_mask; - Convert I/O to space address, and make it honor mem_mask;
- subclass "SCSICD" into SCSI-2 "CD-ROM DRIVE:FX" - subclass "SCSICD" into SCSI-2 "CD-ROM DRIVE:FX"
\- Crashes if CD-ROM is in, on unhandled command 0x28 "Read(10)"; \- Crashes if CD-ROM is in, on unhandled command 0x28 "Read(10)";
\- During POST it tries an unhandled 0x44 "Read Header"; \- During POST it tries an unhandled 0x44 "Read Header";
@ -17,8 +17,8 @@
\- BIOS main menu draws BG0 only as backdrop of the PCE VDCs with 16M mode (5); \- BIOS main menu draws BG0 only as backdrop of the PCE VDCs with 16M mode (5);
- Implement video mixing with other PCFX chips; - Implement video mixing with other PCFX chips;
- Implement microprogram (layer timings, sort of Sega Saturn VRAM cycle patterns); - Implement microprogram (layer timings, sort of Sega Saturn VRAM cycle patterns);
- Implement Rainbow transfers (NEC logo on POST); - Implement Rainbow transfers (NEC logo on POST);
- Verify ADPCM transfers; - Verify ADPCM transfers;
ADPCM related patents: ADPCM related patents:
- https://patents.google.com/patent/US5692099 - https://patents.google.com/patent/US5692099

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@ -74,6 +74,6 @@ int abc1600_format::get_image_offset(const format &f, int head, int track)
const format &tf = get_track_format(f, head, trk); const format &tf = get_track_format(f, head, trk);
offset += compute_track_size(tf); offset += compute_track_size(tf);
} }
return offset; return offset;
} }

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@ -59,7 +59,7 @@
- connect RS-232 printer port - connect RS-232 printer port
- Z80 SCC/DART interrupt chain - Z80 SCC/DART interrupt chain
- Z80 SCC DMA request - Z80 SCC DMA request
- [:2a:chb] - TX FIFO is full, discarding data - [:2a:chb] - TX FIFO is full, discarding data
*/ */

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@ -6,8 +6,8 @@
by Juergen Buchmueller by Juergen Buchmueller
with contributions by: David Widel, Nicola Salmoria, Aaron Giles, Brian Troha, with contributions by: David Widel, Nicola Salmoria, Aaron Giles, Brian Troha,
Fabio Priuli, Lord Nightmare, The Dumping Union, Team Japump!!!, Hau, Fabio Priuli, Lord Nightmare, The Dumping Union, Team Japump!!!, Hau,
Jean-Francois Del Nero, Omar Cornut, Game Preservation Society, Joseph Redon Jean-Francois Del Nero, Omar Cornut, Game Preservation Society, Joseph Redon
The DECO cassette system consists of three PCBs in a card cage: The DECO cassette system consists of three PCBs in a card cage:

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@ -41,7 +41,7 @@
- XTAL 3.6864 MHz - XTAL 3.6864 MHz
TODO: TODO:
- Finish floppy hookup - Finish floppy hookup
- SCC interrupts - SCC interrupts
- Unknown DUART inputs/outputs - Unknown DUART inputs/outputs
- RS232 - RS232

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@ -4633,13 +4633,13 @@ void goldnpkr_state::caspoker(machine_config &config)
void goldnpkr_state::gldnirq0(machine_config &config) void goldnpkr_state::gldnirq0(machine_config &config)
{ {
goldnpkr_base(config); goldnpkr_base(config);
mc6845_device &crtc(MC6845(config.replace(), "crtc", CPU_CLOCK)); // 68B45 or 6845s @ CPU clock mc6845_device &crtc(MC6845(config.replace(), "crtc", CPU_CLOCK)); // 68B45 or 6845s @ CPU clock
crtc.set_screen("screen"); crtc.set_screen("screen");
crtc.set_show_border_area(false); crtc.set_show_border_area(false);
crtc.set_char_width(8); crtc.set_char_width(8);
crtc.out_vsync_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0); crtc.out_vsync_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
// sound hardware // sound hardware
SPEAKER(config, "mono").front_center(); SPEAKER(config, "mono").front_center();
DISCRETE(config, m_discrete, goldnpkr_discrete).add_route(ALL_OUTPUTS, "mono", 1.0); DISCRETE(config, m_discrete, goldnpkr_discrete).add_route(ALL_OUTPUTS, "mono", 1.0);
@ -11133,12 +11133,12 @@ ROM_START( boasorte )
ROM_REGION( 0x1800, "gfx1", 0 ) ROM_REGION( 0x1800, "gfx1", 0 )
ROM_FILL( 0x0000, 0x1000, 0x0000 ) // filling the R-G bitplanes ROM_FILL( 0x0000, 0x1000, 0x0000 ) // filling the R-G bitplanes
ROM_COPY( "gfx", 0x0000, 0x1000, 0X0800 ) ROM_COPY( "gfx", 0x0000, 0x1000, 0x0800 )
ROM_REGION( 0x1800, "gfx2", 0 ) ROM_REGION( 0x1800, "gfx2", 0 )
ROM_COPY( "gfx", 0x8000, 0x0000, 0X0800 ) ROM_COPY( "gfx", 0x8000, 0x0000, 0x0800 )
ROM_COPY( "gfx", 0xC000, 0x0800, 0X0800 ) ROM_COPY( "gfx", 0xC000, 0x0800, 0x0800 )
ROM_COPY( "gfx", 0x0800, 0x1000, 0X0800 ) ROM_COPY( "gfx", 0x0800, 0x1000, 0x0800 )
ROM_REGION( 0x0100, "proms", 0 ) ROM_REGION( 0x0100, "proms", 0 )
ROM_LOAD( "82s129.bin", 0x0000, 0x0100, CRC(7f31066b) SHA1(15420780ec6b2870fc4539ec3afe4f0c58eedf12) ) ROM_LOAD( "82s129.bin", 0x0000, 0x0100, CRC(7f31066b) SHA1(15420780ec6b2870fc4539ec3afe4f0c58eedf12) )

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@ -1,47 +1,47 @@
// license:BSD-3-Clause // license:BSD-3-Clause
// copyright-holders:Devin Acker // copyright-holders:Devin Acker
/* /*
Casio LD-50 electronic drums Casio LD-50 electronic drums
Unlike most Casio instruments, this is either rebranded or outsourced. Unlike most Casio instruments, this is either rebranded or outsourced.
It's unclear who developed it, or if it was ever sold under other brands, It's unclear who developed it, or if it was ever sold under other brands,
but the data ROM mentions "SharpWin". but the data ROM mentions "SharpWin".
Main board: Main board:
bottom left: "DIGITAL DRUM [LD-50] DATE: 2001/07/20" bottom left: "DIGITAL DRUM [LD-50] DATE: 2001/07/20"
bottom right: "LD50 Main PCB Rev.1" bottom right: "LD50 Main PCB Rev.1"
IC1: Burr-Brown PCM1717E DAC IC1: Burr-Brown PCM1717E DAC
IC2: unknown SOIC8 ("2429 170") IC2: unknown SOIC8 ("2429 170")
IC4: Philips P87C52UBAA MCU IC4: Philips P87C52UBAA MCU
IC5: AMD AM29F040 ROM IC5: AMD AM29F040 ROM
IC7/8/9/10: 4x 74HC374 IC7/8/9/10: 4x 74HC374
IC11: unknown COB (letter "B" handwritten on epoxy) IC11: unknown COB (letter "B" handwritten on epoxy)
IC12: Dream SAM9793 IC12: Dream SAM9793
XTAL1: 9.6MHz (for SAM9793) XTAL1: 9.6MHz (for SAM9793)
XTAL2: 12MHz (for MCU) XTAL2: 12MHz (for MCU)
A 10-pin header at the upper left connects to the input matrix and A 10-pin header at the upper left connects to the input matrix and
a small plastic LCD assembly on the other side of the board. a small plastic LCD assembly on the other side of the board.
Most of the sound is provided by the SAM9793, which is just a MIDI Most of the sound is provided by the SAM9793, which is just a MIDI
synth on a chip that takes in serial MIDI input and outputs I2S. synth on a chip that takes in serial MIDI input and outputs I2S.
The four sound effect pads also trigger PCM samples separately, The four sound effect pads also trigger PCM samples separately,
possibly via the black blob at IC11. possibly via the black blob at IC11.
The external ROM contains the demo and rhythms, which are all stored The external ROM contains the demo and rhythms, which are all stored
as standard type 0 MIDI files. as standard type 0 MIDI files.
To activate the test mode, hold "Rhythm" and "Assign" when powering on. To activate the test mode, hold "Rhythm" and "Assign" when powering on.
From here, hitting the drum pads will display time/velocity measurements. From here, hitting the drum pads will display time/velocity measurements.
TODO: TODO:
- drum LEDs - drum LEDs
- LCD artwork - LCD artwork
- clickable layout? - clickable layout?
- possibly connect a MIDI out port in lieu of the SAM9793 - possibly connect a MIDI out port in lieu of the SAM9793
(MCS51 core needs proper serial output first) (MCS51 core needs proper serial output first)
- dump/emulate the other PCM device somehow - dump/emulate the other PCM device somehow
*/ */
#include "emu.h" #include "emu.h"

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@ -2,7 +2,7 @@
// copyright-holders: // copyright-holders:
/* /*
Neo Mania: Neo Mania:
The Portuguese (Vila Nova de Gaia) company "Hyper M.A.R." created this machine on 2002 with 40 games, The Portuguese (Vila Nova de Gaia) company "Hyper M.A.R." created this machine on 2002 with 40 games,
and updated it on 2003 increasing the number of games up to 48. There was a latest newer version and updated it on 2003 increasing the number of games up to 48. There was a latest newer version
where they added "Strikers 1945" and "Prehistoric Isle 2", reaching 50 games. where they added "Strikers 1945" and "Prehistoric Isle 2", reaching 50 games.
There are Spanish and Portuguese localizations. There are Spanish and Portuguese localizations.

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@ -153,7 +153,7 @@ static INPUT_PORTS_START( rockrage )
PORT_DIPSETTING( 0x01, "3" ) PORT_DIPSETTING( 0x01, "3" )
PORT_DIPSETTING( 0x00, "5" ) PORT_DIPSETTING( 0x00, "5" )
PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3") PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) ) PORT_DIPLOCATION("SW2:3")
PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) ) // Actually noted as "テーブル" / "Table". Set here as initial in original Japanese version PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) ) // Actually noted as "テーブル" / "Table". Set here as initial in original Japanese version
PORT_DIPSETTING( 0x00, DEF_STR( Upright ) ) PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
PORT_DIPNAME( 0x08, 0x08, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:4") PORT_DIPNAME( 0x08, 0x08, DEF_STR( Bonus_Life ) ) PORT_DIPLOCATION("SW2:4")
PORT_DIPSETTING( 0x08, "30k & Every 70k" ) PORT_DIPSETTING( 0x08, "30k & Every 70k" )

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@ -462,7 +462,7 @@ void specpls3_state::spectrum_plus3(machine_config &config)
+2A/B has built-in tape "datacorder", +3/B has built-in 3" fdd +2A/B has built-in tape "datacorder", +3/B has built-in 3" fdd
+2A/+3 use common z70830 pcb with v4.0 rom (fdc etc. unpopulated on +2A) +2A/+3 use common z70830 pcb with v4.0 rom (fdc etc. unpopulated on +2A)
+2B/+3B use unique z70833/z70835 pcbs but use same v4.1 rom +2B/+3B use unique z70833/z70835 pcbs but use same v4.1 rom
Note, +2 (non-A/B, aka "grey case") although Amstrad built is essentially a re-cased Sinclair 128K, see spec128.cpp Note, +2 (non-A/B, aka "grey case") although Amstrad built is essentially a re-cased Sinclair 128K, see spec128.cpp
*/ */
ROM_START(specpl2a) ROM_START(specpl2a)

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@ -37,12 +37,12 @@ Features (TS-Configuration):
Refs: Refs:
ZxEvo: http://nedopc.com/zxevo/zxevo_eng.php ZxEvo: http://nedopc.com/zxevo/zxevo_eng.php
Principal scheme (rev. C) :: http://nedopc.com/zxevo/zxevo_sch_revc.pdf Principal scheme (rev. C) :: http://nedopc.com/zxevo/zxevo_sch_revc.pdf
Montage scheme (rev. C) :: http://nedopc.com/zxevo/zxevo_mon_revc.pdf Montage scheme (rev. C) :: http://nedopc.com/zxevo/zxevo_mon_revc.pdf
TsConf: https://github.com/tslabs/zx-evo/blob/master/pentevo/docs/TSconf/tsconf_en.md TsConf: https://github.com/tslabs/zx-evo/blob/master/pentevo/docs/TSconf/tsconf_en.md
https://github.com/tslabs/zx-evo/raw/master/pentevo/docs/TSconf/TSconf.xls https://github.com/tslabs/zx-evo/raw/master/pentevo/docs/TSconf/TSconf.xls
FAQ-RUS: https://forum.tslabs.info/viewtopic.php?f=35&t=157 FAQ-RUS: https://forum.tslabs.info/viewtopic.php?f=35&t=157
ROM: https://github.com/tslabs/zx-evo/blob/master/pentevo/rom/bin/ts-bios.rom (validated on: 2021-12-14) ROM: https://github.com/tslabs/zx-evo/blob/master/pentevo/rom/bin/ts-bios.rom (validated on: 2021-12-14)
HowTo: HowTo:
# Use ts-bios.rom above. You also need tr-dos roms which simpliest(?) to get from pentagon. # Use ts-bios.rom above. You also need tr-dos roms which simpliest(?) to get from pentagon.
@ -139,8 +139,8 @@ void tsconf_state::tsconf_bank_w(offs_t offset, u8 data)
static const gfx_layout spectrum_charlayout = static const gfx_layout spectrum_charlayout =
{ {
8, 8, /* 8 x 8 characters */ 8, 8, /* 8 x 8 characters */
96, /* 96 characters */ 96, /* 96 characters */
1, /* 1 bits per pixel */ 1, /* 1 bits per pixel */
{0}, /* no bitplanes */ {0}, /* no bitplanes */
/* x offsets */ /* x offsets */
{STEP8(0, 1)}, {STEP8(0, 1)},
@ -174,10 +174,10 @@ static const gfx_layout tsconf_tile_16cpp_layout =
}; };
static GFXDECODE_START(gfx_tsconf) static GFXDECODE_START(gfx_tsconf)
GFXDECODE_ENTRY("maincpu", 0, tsconf_charlayout, 0xf7, 1) // TM_TS_CHAR : TXT GFXDECODE_ENTRY("maincpu", 0, tsconf_charlayout, 0xf7, 1) // TM_TS_CHAR : TXT
GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_TILES0 : T0 16cpp GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_TILES0 : T0 16cpp
GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_TILES1 : T1 16cpp GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_TILES1 : T1 16cpp
GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_SPRITES : Sprites 16cpp GFXDECODE_ENTRY("maincpu", 0, tsconf_tile_16cpp_layout, 0, 16) // TM_SPRITES : Sprites 16cpp
GFXDECODE_ENTRY("maincpu", 0x1fd00, spectrum_charlayout, 0xf7, 1) // TM_ZX_CHAR GFXDECODE_ENTRY("maincpu", 0x1fd00, spectrum_charlayout, 0xf7, 1) // TM_ZX_CHAR
GFXDECODE_END GFXDECODE_END
@ -218,27 +218,27 @@ void tsconf_state::machine_reset()
m_port_f7_ext = DISABLED; m_port_f7_ext = DISABLED;
m_scanline_delayed_regs_update = {}; m_scanline_delayed_regs_update = {};
m_regs[V_CONFIG] = 0x00; // 00000000 m_regs[V_CONFIG] = 0x00; // 00000000
m_regs[V_PAGE] = 0x05; // 00000101 m_regs[V_PAGE] = 0x05; // 00000101
m_regs[G_X_OFFS_L] = 0x00; // 00000000 m_regs[G_X_OFFS_L] = 0x00; // 00000000
m_regs[G_X_OFFS_H] &= 0xfe; // xxxxxxx0 m_regs[G_X_OFFS_H] &= 0xfe; // xxxxxxx0
m_regs[G_Y_OFFS_L] = 0x00; // 00000000 m_regs[G_Y_OFFS_L] = 0x00; // 00000000
m_regs[G_Y_OFFS_H] &= 0xfe; // xxxxxxx0 m_regs[G_Y_OFFS_H] &= 0xfe; // xxxxxxx0
m_regs[TS_CONFIG] &= 0x03; // 000000xx m_regs[TS_CONFIG] &= 0x03; // 000000xx
m_regs[PAL_SEL] = 0x0f; // 00001111 m_regs[PAL_SEL] = 0x0f; // 00001111
m_regs[PAGE0] = 0x00; // 00000000 m_regs[PAGE0] = 0x00; // 00000000
m_regs[PAGE1] = 0x05; // 00000101 m_regs[PAGE1] = 0x05; // 00000101
m_regs[PAGE2] = 0x02; // 00000010 m_regs[PAGE2] = 0x02; // 00000010
m_regs[PAGE3] = 0x00; // 00000000 m_regs[PAGE3] = 0x00; // 00000000
m_regs[FMAPS] &= 0xef; // xxx0xxxx m_regs[FMAPS] &= 0xef; // xxx0xxxx
m_regs[SYS_CONFIG] = 0x00; // 00000000 m_regs[SYS_CONFIG] = 0x00; // 00000000
m_regs[MEM_CONFIG] = 0x04; // 00000100 m_regs[MEM_CONFIG] = 0x04; // 00000100
m_regs[HS_INT] = 0x01; // 00000001 m_regs[HS_INT] = 0x01; // 00000001
m_regs[VS_INT_L] = 0x00; // 00000000 m_regs[VS_INT_L] = 0x00; // 00000000
m_regs[VS_INT_H] &= 0x0e; // 0000xxx0 m_regs[VS_INT_H] &= 0x0e; // 0000xxx0
m_regs[FDD_VIRT] &= 0xf0; // xxxx0000 m_regs[FDD_VIRT] &= 0xf0; // xxxx0000
m_regs[INT_MASK] = 0x01; // xxxxx001 m_regs[INT_MASK] = 0x01; // xxxxx001
m_regs[CACHE_CONFIG] &= 0xf0; // xxxx0000 m_regs[CACHE_CONFIG] &= 0xf0; // xxxx0000
if (m_beta->started()) if (m_beta->started())
m_beta->enable(); m_beta->enable();

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@ -155,7 +155,7 @@ public:
void abc1600(machine_config &config); void abc1600(machine_config &config);
void abc1600_mem(address_map &map); void abc1600_mem(address_map &map);
void mac_mem(address_map &map); void mac_mem(address_map &map);
// peripherals // peripherals
int m_cs7; // card select address bit 7 int m_cs7; // card select address bit 7
int m_bus0; // BUS 0 selected int m_bus0; // BUS 0 selected

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@ -44,11 +44,11 @@ void abc1600_mac_device::mac_map(address_map &map)
{ {
map(0x80000, 0x80000).mirror(0x006f8).select(0x7f900).rw(FUNC(abc1600_mac_device::page_hi_r), FUNC(abc1600_mac_device::page_hi_w)); map(0x80000, 0x80000).mirror(0x006f8).select(0x7f900).rw(FUNC(abc1600_mac_device::page_hi_r), FUNC(abc1600_mac_device::page_hi_w));
map(0x80001, 0x80001).mirror(0x006f8).select(0x7f900).rw(FUNC(abc1600_mac_device::page_lo_r), FUNC(abc1600_mac_device::page_lo_w)); map(0x80001, 0x80001).mirror(0x006f8).select(0x7f900).rw(FUNC(abc1600_mac_device::page_lo_r), FUNC(abc1600_mac_device::page_lo_w));
map(0x80002, 0x80002).mirror(0x7fff8).noprw(); map(0x80002, 0x80002).mirror(0x7fff8).noprw();
map(0x80003, 0x80003).mirror(0x07ef8).select(0x78100).rw(FUNC(abc1600_mac_device::segment_r), FUNC(abc1600_mac_device::segment_w)); map(0x80003, 0x80003).mirror(0x07ef8).select(0x78100).rw(FUNC(abc1600_mac_device::segment_r), FUNC(abc1600_mac_device::segment_w));
map(0x80004, 0x80004).mirror(0x7fff8).noprw(); map(0x80004, 0x80004).mirror(0x7fff8).noprw();
map(0x80005, 0x80005).mirror(0x7fff8).nopr().w(FUNC(abc1600_mac_device::task_w)); map(0x80005, 0x80005).mirror(0x7fff8).nopr().w(FUNC(abc1600_mac_device::task_w));
map(0x80006, 0x80006).mirror(0x7fff8).noprw(); map(0x80006, 0x80006).mirror(0x7fff8).noprw();
map(0x80007, 0x80007).mirror(0x7fff8).r(FUNC(abc1600_mac_device::cause_r)).nopw(); map(0x80007, 0x80007).mirror(0x7fff8).r(FUNC(abc1600_mac_device::cause_r)).nopw();
} }
@ -179,7 +179,7 @@ inline offs_t abc1600_mac_device::get_physical_offset(offs_t offset, int task, b
nonx = PAGE_NONX; nonx = PAGE_NONX;
wp = PAGE_WP; wp = PAGE_WP;
if (LOG && (offset != virtual_offset)) logerror("%s MAC %05x:%06x (SEGA %03x SEGD %02x PGA %03x PGD %04x NONX %u WP %u TASK %u FC %u MAGIC %u)\n", if (LOG && (offset != virtual_offset)) logerror("%s MAC %05x:%06x (SEGA %03x SEGD %02x PGA %03x PGD %04x NONX %u WP %u TASK %u FC %u MAGIC %u)\n",
machine().describe_context(), offset, virtual_offset, sega, segd, pga, page_data, nonx, wp, task, m_read_fc(), m_magic); machine().describe_context(), offset, virtual_offset, sega, segd, pga, page_data, nonx, wp, task, m_read_fc(), m_magic);
return virtual_offset; return virtual_offset;
@ -196,7 +196,7 @@ uint8_t abc1600_mac_device::read(offs_t offset)
{ {
return m_rom->base()[offset & 0x3fff]; return m_rom->base()[offset & 0x3fff];
} }
uint8_t fc = m_read_fc(); uint8_t fc = m_read_fc();
int task = m_task; int task = m_task;
@ -342,7 +342,7 @@ void abc1600_mac_device::task_w(offs_t offset, uint8_t data)
m_boote = !BIT(data, 6); m_boote = !BIT(data, 6);
m_magic = !BIT(data, 7); m_magic = !BIT(data, 7);
if (LOG_MAC) logerror("%s TASK W %02x (TASK %u BOOTE %u MAGIC %u)\n", if (LOG_MAC) logerror("%s TASK W %02x (TASK %u BOOTE %u MAGIC %u)\n",
machine().describe_context(), data, m_task, m_boote, m_magic); machine().describe_context(), data, m_task, m_boote, m_magic);
} }
@ -399,7 +399,7 @@ void abc1600_mac_device::segment_w(offs_t offset, uint8_t data)
offs_t sega = (m_task << 5) | A8 << 4 | ((offset >> 15) & 0xf); offs_t sega = (m_task << 5) | A8 << 4 | ((offset >> 15) & 0xf);
m_segment_ram[sega] = data & 0x7f; m_segment_ram[sega] = data & 0x7f;
if (LOG_MAC) logerror("%s SEG W %05x:%02x SEGA %03x SEGD %02x TASK %u\n", if (LOG_MAC) logerror("%s SEG W %05x:%02x SEGA %03x SEGD %02x TASK %u\n",
machine().describe_context(), offset, data, machine().describe_context(), offset, data,
sega, m_segment_ram[sega], m_task); sega, m_segment_ram[sega], m_task);
} }
@ -502,8 +502,8 @@ void abc1600_mac_device::page_lo_w(offs_t offset, uint8_t data)
offs_t pga = ((segd & 0x3f) << 4) | ((offset >> 11) & 0xf); offs_t pga = ((segd & 0x3f) << 4) | ((offset >> 11) & 0xf);
m_page_ram[pga] = (m_page_ram[pga] & 0xff00) | data; m_page_ram[pga] = (m_page_ram[pga] & 0xff00) | data;
if (LOG_MAC) logerror("%s PAGE W %05x:%02x (SEGA %03x SEGD %02x PGA %03x PGD %04x TASK %u)\n", if (LOG_MAC) logerror("%s PAGE W %05x:%02x (SEGA %03x SEGD %02x PGA %03x PGD %04x TASK %u)\n",
machine().describe_context(), offset, data, machine().describe_context(), offset, data,
sega, segd, pga, m_page_ram[pga], m_task); sega, segd, pga, m_page_ram[pga], m_task);
} }
@ -520,10 +520,10 @@ void abc1600_mac_device::page_hi_w(offs_t offset, uint8_t data)
0 X19 0 X19
1 X20 1 X20
2 2
3 3
4 4
5 5
6 _WP 6 _WP
7 NONX 7 NONX
@ -651,10 +651,10 @@ void abc1600_mac_device::dump()
offs_t sega = (task << 5) | seg; offs_t sega = (task << 5) | seg;
uint8_t segd = m_segment_ram[sega]; uint8_t segd = m_segment_ram[sega];
offs_t pga = ((segd & 0x3f) << 4) | page; offs_t pga = ((segd & 0x3f) << 4) | page;
uint16_t page_data = m_page_ram[pga]; uint16_t page_data = m_page_ram[pga];
offs_t physical = (page_data & 0x3ff) << 11; offs_t physical = (page_data & 0x3ff) << 11;
bool nonx = PAGE_NONX; bool nonx = PAGE_NONX;
bool wp = PAGE_WP; bool wp = PAGE_WP;

View File

@ -63,7 +63,7 @@ public:
void dma2_mreq_w(offs_t offset, uint8_t data) { dma_mreq_w(DMAMAP_R2_LO, offset, data); } void dma2_mreq_w(offs_t offset, uint8_t data) { dma_mreq_w(DMAMAP_R2_LO, offset, data); }
uint8_t dma2_iorq_r(offs_t offset) { return dma_iorq_r(DMAMAP_R2_LO, offset); } uint8_t dma2_iorq_r(offs_t offset) { return dma_iorq_r(DMAMAP_R2_LO, offset); }
void dma2_iorq_w(offs_t offset, uint8_t data) { dma_iorq_w(DMAMAP_R2_LO, offset, data); } void dma2_iorq_w(offs_t offset, uint8_t data) { dma_iorq_w(DMAMAP_R2_LO, offset, data); }
void dump(); void dump();
protected: protected:
@ -88,7 +88,7 @@ private:
DMAMAP_R0_LO, DMAMAP_R0_LO,
DMAMAP_R0_HI DMAMAP_R0_HI
}; };
offs_t get_physical_offset(offs_t offset, int task, bool &nonx, bool &wp); offs_t get_physical_offset(offs_t offset, int task, bool &nonx, bool &wp);
offs_t get_dma_address(int index, uint16_t offset); offs_t get_dma_address(int index, uint16_t offset);
@ -109,12 +109,12 @@ private:
required_device<watchdog_timer_device> m_watchdog; required_device<watchdog_timer_device> m_watchdog;
devcb_read8 m_read_fc; devcb_read8 m_read_fc;
devcb_write8 m_write_buserr; devcb_write8 m_write_buserr;
bool m_boote; bool m_boote;
bool m_magic; bool m_magic;
int m_task; int m_task;
uint8_t m_dmamap[8]; uint8_t m_dmamap[8];
uint8_t m_cause; uint8_t m_cause;
}; };

View File

@ -358,13 +358,13 @@ void tsconf_state::spectrum_UpdateBorderBitmap()
} }
/* /*
SFILE Reg.16 7 6 5 4 3 2 1 0 SFILE Reg.16 7 6 5 4 3 2 1 0
0 R0L Y[7:0] 0 R0L Y[7:0]
1 R0H YF LEAP ACT - YS[2:0] Y[8] 1 R0H YF LEAP ACT - YS[2:0] Y[8]
2 R1L X[7:0] 2 R1L X[7:0]
3 R1H XF - - - XS[2:0] X[8] 3 R1H XF - - - XS[2:0] X[8]
4 R2L TNUM[7:0] 4 R2L TNUM[7:0]
5 R2H SPAL[7:4] TNUM[11:8] 5 R2H SPAL[7:4] TNUM[11:8]
*/ */
void tsconf_state::draw_sprites(const rectangle &cliprect) void tsconf_state::draw_sprites(const rectangle &cliprect)
{ {