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- mips3: Made fast RAM option common to both interpreter and DRC. [MooglyGuy]

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This commit is contained in:
therealmogminer@gmail.com 2015-03-29 19:20:21 +02:00
parent 9be2780fcd
commit 4e11cfcb0d
9 changed files with 359 additions and 374 deletions
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560
src/emu/cpu/mips/mips3.c
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@ -148,9 +148,12 @@ mips3_device::mips3_device(const machine_config &mconfig, device_type type, cons
, m_pfnmask(0) , m_pfnmask(0)
, m_tlbentries(0) , m_tlbentries(0)
, m_bigendian(endianness == ENDIANNESS_BIG) , m_bigendian(endianness == ENDIANNESS_BIG)
, m_byte_xor(m_bigendian ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0))
, m_word_xor(m_bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0))
, c_icache_size(0) , c_icache_size(0)
, c_dcache_size(0) , c_dcache_size(0)
, m_vtlb(NULL) , m_vtlb(NULL)
, m_fastram_select(0)
, m_debugger_temp(0) , m_debugger_temp(0)
, m_cache(CACHE_SIZE + sizeof(internal_mips3_state)) , m_cache(CACHE_SIZE + sizeof(internal_mips3_state))
, m_drcuml(NULL) , m_drcuml(NULL)
@ -161,7 +164,6 @@ mips3_device::mips3_device(const machine_config &mconfig, device_type type, cons
, m_nocode(NULL) , m_nocode(NULL)
, m_out_of_cycles(NULL) , m_out_of_cycles(NULL)
, m_tlb_mismatch(NULL) , m_tlb_mismatch(NULL)
, m_fastram_select(0)
, m_hotspot_select(0) , m_hotspot_select(0)
{ {
memset(m_fpmode, 0, sizeof(m_fpmode)); memset(m_fpmode, 0, sizeof(m_fpmode));
@ -996,12 +998,23 @@ offs_t mips3_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *op
TLB HANDLING TLB HANDLING
***************************************************************************/ ***************************************************************************/
inline int mips3_device::RBYTE(offs_t address, UINT32 *result) bool mips3_device::RBYTE(offs_t address, UINT32 *result)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
*result = fastbase[tlbaddress ^ m_byte_xor];
return true;
}
*result = (*m_memory.read_byte)(*m_program, tlbaddress);
} }
else else
{ {
@ -1014,18 +1027,28 @@ inline int mips3_device::RBYTE(offs_t address, UINT32 *result)
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
bool mips3_device::RHALF(offs_t address, UINT32 *result)
inline int mips3_device::RHALF(offs_t address, UINT32 *result)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
*result = ((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1];
return true;
}
*result = (*m_memory.read_word)(*m_program, tlbaddress);
} }
else else
{ {
@ -1038,18 +1061,28 @@ inline int mips3_device::RHALF(offs_t address, UINT32 *result)
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
bool mips3_device::RWORD(offs_t address, UINT32 *result)
inline int mips3_device::RWORD(offs_t address, UINT32 *result)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
*result = ((UINT32*)fastbase)[tlbaddress >> 2];
return true;
}
*result = (*m_memory.read_dword)(*m_program, tlbaddress);
} }
else else
{ {
@ -1062,15 +1095,14 @@ inline int mips3_device::RWORD(offs_t address, UINT32 *result)
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
bool mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
inline int mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); *result = (*m_memory.read_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
@ -1086,15 +1118,14 @@ inline int mips3_device::RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
bool mips3_device::RDOUBLE(offs_t address, UINT64 *result)
inline int mips3_device::RDOUBLE(offs_t address, UINT64 *result)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff)); *result = (*m_memory.read_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff));
@ -1110,15 +1141,14 @@ inline int mips3_device::RDOUBLE(offs_t address, UINT64 *result)
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
bool mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
inline int mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_READ_ALLOWED) if (tlbval & VTLB_READ_ALLOWED)
{ {
*result = (*m_memory.read_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask); *result = (*m_memory.read_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), mem_mask);
@ -1134,18 +1164,28 @@ inline int mips3_device::RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 m
generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address); generate_tlb_exception(EXCEPTION_TLBLOAD_FILL, address);
} }
*result = 0; *result = 0;
return 0; return false;
} }
return 1; return true;
} }
void mips3_device::WBYTE(offs_t address, UINT8 data)
inline void mips3_device::WBYTE(offs_t address, UINT8 data)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_byte)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
UINT8 *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
fastbase[tlbaddress ^ m_byte_xor] = data;
return;
}
(*m_memory.write_byte)(*m_program, tlbaddress, data);
} }
else else
{ {
@ -1164,13 +1204,23 @@ inline void mips3_device::WBYTE(offs_t address, UINT8 data)
} }
} }
void mips3_device::WHALF(offs_t address, UINT16 data)
inline void mips3_device::WHALF(offs_t address, UINT16 data)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_word)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
((UINT16*)fastbase)[(tlbaddress ^ m_word_xor) >> 1] = data;
return;
}
(*m_memory.write_word)(*m_program, tlbaddress, data);
} }
else else
{ {
@ -1189,13 +1239,23 @@ inline void mips3_device::WHALF(offs_t address, UINT16 data)
} }
} }
void mips3_device::WWORD(offs_t address, UINT32 data)
inline void mips3_device::WWORD(offs_t address, UINT32 data)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_dword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); const UINT32 tlbaddress = (tlbval & ~0xfff) | (address & 0xfff);
for (int ramnum = 0; ramnum < m_fastram_select; ramnum++)
{
if (m_fastram[ramnum].readonly == TRUE || tlbaddress < m_fastram[ramnum].start || tlbaddress > m_fastram[ramnum].end)
{
continue;
}
void *fastbase = (UINT8*)m_fastram[ramnum].base - m_fastram[ramnum].start;
((UINT32*)fastbase)[tlbaddress >> 2] = data;
return;
}
(*m_memory.write_dword)(*m_program, tlbaddress, data);
} }
else else
{ {
@ -1214,10 +1274,9 @@ inline void mips3_device::WWORD(offs_t address, UINT32 data)
} }
} }
void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
inline void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); (*m_memory.write_dword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask);
@ -1239,14 +1298,12 @@ inline void mips3_device::WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_m
} }
} }
void mips3_device::WDOUBLE(offs_t address, UINT64 data)
inline void mips3_device::WDOUBLE(offs_t address, UINT64 data)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
//printf("%08x: %08x\n", (UINT32)address, (UINT32)tlbval);
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data); (*m_memory.write_qword)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data);
} }
else else
{ {
@ -1265,10 +1322,9 @@ inline void mips3_device::WDOUBLE(offs_t address, UINT64 data)
} }
} }
void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
inline void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask)
{ {
UINT32 tlbval = m_tlb_table[address >> 12]; const UINT32 tlbval = m_tlb_table[address >> 12];
if (tlbval & VTLB_WRITE_ALLOWED) if (tlbval & VTLB_WRITE_ALLOWED)
{ {
(*m_memory.write_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask); (*m_memory.write_qword_masked)(*m_program, (tlbval & ~0xfff) | (address & 0xfff), data, mem_mask);
@ -1296,7 +1352,7 @@ inline void mips3_device::WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem
COP0 (SYSTEM) EXECUTION HANDLING COP0 (SYSTEM) EXECUTION HANDLING
***************************************************************************/ ***************************************************************************/
inline UINT64 mips3_device::get_cop0_reg(int idx) UINT64 mips3_device::get_cop0_reg(int idx)
{ {
if (idx == COP0_Count) if (idx == COP0_Count)
{ {
@ -1329,7 +1385,7 @@ inline UINT64 mips3_device::get_cop0_reg(int idx)
return m_core->cpr[0][idx]; return m_core->cpr[0][idx];
} }
inline void mips3_device::set_cop0_reg(int idx, UINT64 val) void mips3_device::set_cop0_reg(int idx, UINT64 val)
{ {
switch (idx) switch (idx)
{ {
@ -1406,7 +1462,7 @@ inline void mips3_device::set_cop0_creg(int idx, UINT64 val)
m_core->ccr[0][idx] = val; m_core->ccr[0][idx] = val;
} }
inline void mips3_device::handle_cop0(UINT32 op) void mips3_device::handle_cop0(UINT32 op)
{ {
if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0)) if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
{ {
@ -1541,7 +1597,7 @@ inline void mips3_device::set_cop1_creg(int idx, UINT64 val)
} }
} }
inline void mips3_device::handle_cop1_fr0(UINT32 op) void mips3_device::handle_cop1_fr0(UINT32 op)
{ {
double dtemp; double dtemp;
@ -1900,7 +1956,7 @@ inline void mips3_device::handle_cop1_fr0(UINT32 op)
} }
inline void mips3_device::handle_cop1_fr1(UINT32 op) void mips3_device::handle_cop1_fr1(UINT32 op)
{ {
double dtemp; double dtemp;
@ -2264,7 +2320,7 @@ inline void mips3_device::handle_cop1_fr1(UINT32 op)
COP1X (FPU EXTRA) EXECUTION HANDLING COP1X (FPU EXTRA) EXECUTION HANDLING
***************************************************************************/ ***************************************************************************/
inline void mips3_device::handle_cop1x_fr0(UINT32 op) void mips3_device::handle_cop1x_fr0(UINT32 op)
{ {
UINT64 temp64; UINT64 temp64;
UINT32 temp; UINT32 temp;
@ -2342,8 +2398,7 @@ inline void mips3_device::handle_cop1x_fr0(UINT32 op)
} }
} }
void mips3_device::handle_cop1x_fr1(UINT32 op)
inline void mips3_device::handle_cop1x_fr1(UINT32 op)
{ {
UINT64 temp64; UINT64 temp64;
UINT32 temp; UINT32 temp;
@ -2447,34 +2502,7 @@ inline void mips3_device::set_cop2_creg(int idx, UINT64 val)
m_core->ccr[2][idx] = val; m_core->ccr[2][idx] = val;
} }
inline void mips3_device::handle_integer_divide_by_zero(UINT32 op) void mips3_device::handle_cop2(UINT32 op)
{
HIVAL64 = (INT32)RSVAL32;
if (m_flavor == MIPS3_TYPE_VR4300)
{
if (RSVAL32 >= 0)
{
LOVAL64 = (INT32)0x7fffffff;
}
else
{
LOVAL64 = (INT32)0x80000001;
}
}
else
{
if (RSVAL32 >= 0)
{
LOVAL64 = -1;
}
else
{
LOVAL64 = 1;
}
}
}
inline void mips3_device::handle_cop2(UINT32 op)
{ {
if (!(SR & SR_COP2)) if (!(SR & SR_COP2))
{ {
@ -2526,6 +2554,159 @@ inline void mips3_device::handle_cop2(UINT32 op)
CORE EXECUTION LOOP CORE EXECUTION LOOP
***************************************************************************/ ***************************************************************************/
void mips3_device::handle_regimm(UINT32 op)
{
switch (RTREG)
{
case 0x00: /* BLTZ */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); break;
case 0x01: /* BGEZ */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); break;
case 0x02: /* BLTZL */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
case 0x03: /* BGEZL */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
case 0x08: /* TGEI */ if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x09: /* TGEIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0a: /* TLTI */ if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0b: /* TLTIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0c: /* TEQI */ if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x10: /* BLTZAL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31); break;
case 0x11: /* BGEZAL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31); break;
case 0x12: /* BLTZALL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
case 0x13: /* BGEZALL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
default: /* ??? */ invalid_instruction(op); break;
}
}
void mips3_device::handle_special(UINT32 op)
{
switch (op & 63)
{
case 0x00: /* SLL */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 << SHIFT); break;
case 0x01: /* MOVF - R5000*/if (RDREG && GET_FCC((op >> 18) & 7) == ((op >> 16) & 1)) RDVAL64 = RSVAL64; break;
case 0x02: /* SRL */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> SHIFT); break;
case 0x03: /* SRA */ if (RDREG) RDVAL64 = (INT32)RTVAL32 >> SHIFT; break;
case 0x04: /* SLLV */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 << (RSVAL32 & 31)); break;
case 0x06: /* SRLV */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> (RSVAL32 & 31)); break;
case 0x07: /* SRAV */ if (RDREG) RDVAL64 = (INT32)RTVAL32 >> (RSVAL32 & 31); break;
case 0x08: /* JR */ SETPC(RSVAL32); break;
case 0x09: /* JALR */ SETPCL(RSVAL32,RDREG); break;
case 0x0a: /* MOVZ - R5000 */if (RTVAL64 == 0) { if (RDREG) RDVAL64 = RSVAL64; } break;
case 0x0b: /* MOVN - R5000 */if (RTVAL64 != 0) { if (RDREG) RDVAL64 = RSVAL64; } break;
case 0x0c: /* SYSCALL */ generate_exception(EXCEPTION_SYSCALL, 1); break;
case 0x0d: /* BREAK */ generate_exception(EXCEPTION_BREAK, 1); break;
case 0x0f: /* SYNC */ /* effective no-op */ break;
case 0x10: /* MFHI */ if (RDREG) RDVAL64 = HIVAL64; break;
case 0x11: /* MTHI */ HIVAL64 = RSVAL64; break;
case 0x12: /* MFLO */ if (RDREG) RDVAL64 = LOVAL64; break;
case 0x13: /* MTLO */ LOVAL64 = RSVAL64; break;
case 0x14: /* DSLLV */ if (RDREG) RDVAL64 = RTVAL64 << (RSVAL32 & 63); break;
case 0x16: /* DSRLV */ if (RDREG) RDVAL64 = RTVAL64 >> (RSVAL32 & 63); break;
case 0x17: /* DSRAV */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (RSVAL32 & 63); break;
case 0x18: /* MULT */
{
UINT64 temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
LOVAL64 = (INT32)temp64;
HIVAL64 = (INT32)(temp64 >> 32);
m_core->icount -= 3;
break;
}
case 0x19: /* MULTU */
{
UINT64 temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
LOVAL64 = (INT32)temp64;
HIVAL64 = (INT32)(temp64 >> 32);
m_core->icount -= 3;
break;
}
case 0x1a: /* DIV */
if (RTVAL32)
{
LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
}
m_core->icount -= 35;
break;
case 0x1b: /* DIVU */
if (RTVAL32)
{
LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
}
m_core->icount -= 35;
break;
case 0x1c: /* DMULT */
{
UINT64 temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
LOVAL64 = temp64;
HIVAL64 = (INT64)temp64 >> 63;
m_core->icount -= 7;
break;
}
case 0x1d: /* DMULTU */
{
UINT64 temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
LOVAL64 = temp64;
HIVAL64 = 0;
m_core->icount -= 7;
break;
}
case 0x1e: /* DDIV */
if (RTVAL64)
{
LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
}
m_core->icount -= 67;
break;
case 0x1f: /* DDIVU */
if (RTVAL64)
{
LOVAL64 = RSVAL64 / RTVAL64;
HIVAL64 = RSVAL64 % RTVAL64;
}
m_core->icount -= 67;
break;
case 0x20: /* ADD */
if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);
break;
case 0x21: /* ADDU */ if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32); break;
case 0x22: /* SUB */
if (ENABLE_OVERFLOWS && RSVAL32 < RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);
break;
case 0x23: /* SUBU */ if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32); break;
case 0x24: /* AND */ if (RDREG) RDVAL64 = RSVAL64 & RTVAL64; break;
case 0x25: /* OR */ if (RDREG) RDVAL64 = RSVAL64 | RTVAL64; break;
case 0x26: /* XOR */ if (RDREG) RDVAL64 = RSVAL64 ^ RTVAL64; break;
case 0x27: /* NOR */ if (RDREG) RDVAL64 = ~(RSVAL64 | RTVAL64); break;
case 0x2a: /* SLT */ if (RDREG) RDVAL64 = (INT64)RSVAL64 < (INT64)RTVAL64; break;
case 0x2b: /* SLTU */ if (RDREG) RDVAL64 = (UINT64)RSVAL64 < (UINT64)RTVAL64; break;
case 0x2c: /* DADD */
if (ENABLE_OVERFLOWS && RSVAL64 > ~RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;
break;
case 0x2d: /* DADDU */ if (RDREG) RDVAL64 = RSVAL64 + RTVAL64; break;
case 0x2e: /* DSUB */
if (ENABLE_OVERFLOWS && RSVAL64 < RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;
break;
case 0x2f: /* DSUBU */ if (RDREG) RDVAL64 = RSVAL64 - RTVAL64; break;
case 0x30: /* TGE */ if ((INT64)RSVAL64 >= (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x31: /* TGEU */ if (RSVAL64 >= RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x32: /* TLT */ if ((INT64)RSVAL64 < (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x33: /* TLTU */ if (RSVAL64 < RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x34: /* TEQ */ if (RSVAL64 == RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x36: /* TNE */ if (RSVAL64 != RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x38: /* DSLL */ if (RDREG) RDVAL64 = RTVAL64 << SHIFT; break;
case 0x3a: /* DSRL */ if (RDREG) RDVAL64 = RTVAL64 >> SHIFT; break;
case 0x3b: /* DSRA */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> SHIFT; break;
case 0x3c: /* DSLL32 */ if (RDREG) RDVAL64 = RTVAL64 << (SHIFT + 32); break;
case 0x3e: /* DSRL32 */ if (RDREG) RDVAL64 = RTVAL64 >> (SHIFT + 32); break;
case 0x3f: /* DSRA32 */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (SHIFT + 32); break;
default: /* ??? */ invalid_instruction(op); break;
}
}
void mips3_device::execute_run() void mips3_device::execute_run()
{ {
if (m_isdrc) if (m_isdrc)
@ -2602,154 +2783,11 @@ void mips3_device::execute_run()
switch (op >> 26) switch (op >> 26)
{ {
case 0x00: /* SPECIAL */ case 0x00: /* SPECIAL */
switch (op & 63) handle_special(op);
{
case 0x00: /* SLL */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 << SHIFT); break;
case 0x01: /* MOVF - R5000*/if (RDREG && GET_FCC((op >> 18) & 7) == ((op >> 16) & 1)) RDVAL64 = RSVAL64; break;
case 0x02: /* SRL */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> SHIFT); break;
case 0x03: /* SRA */ if (RDREG) RDVAL64 = (INT32)RTVAL32 >> SHIFT; break;
case 0x04: /* SLLV */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 << (RSVAL32 & 31)); break;
case 0x06: /* SRLV */ if (RDREG) RDVAL64 = (INT32)(RTVAL32 >> (RSVAL32 & 31)); break;
case 0x07: /* SRAV */ if (RDREG) RDVAL64 = (INT32)RTVAL32 >> (RSVAL32 & 31); break;
case 0x08: /* JR */ SETPC(RSVAL32); break;
case 0x09: /* JALR */ SETPCL(RSVAL32,RDREG); break;
case 0x0a: /* MOVZ - R5000 */if (RTVAL64 == 0) { if (RDREG) RDVAL64 = RSVAL64; } break;
case 0x0b: /* MOVN - R5000 */if (RTVAL64 != 0) { if (RDREG) RDVAL64 = RSVAL64; } break;
case 0x0c: /* SYSCALL */ generate_exception(EXCEPTION_SYSCALL, 1); break;
case 0x0d: /* BREAK */ generate_exception(EXCEPTION_BREAK, 1); break;
case 0x0f: /* SYNC */ /* effective no-op */ break;
case 0x10: /* MFHI */ if (RDREG) RDVAL64 = HIVAL64; break;
case 0x11: /* MTHI */ HIVAL64 = RSVAL64; break;
case 0x12: /* MFLO */ if (RDREG) RDVAL64 = LOVAL64; break;
case 0x13: /* MTLO */ LOVAL64 = RSVAL64; break;
case 0x14: /* DSLLV */ if (RDREG) RDVAL64 = RTVAL64 << (RSVAL32 & 63); break;
case 0x16: /* DSRLV */ if (RDREG) RDVAL64 = RTVAL64 >> (RSVAL32 & 63); break;
case 0x17: /* DSRAV */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (RSVAL32 & 63); break;
case 0x18: /* MULT */
temp64 = (INT64)(INT32)RSVAL32 * (INT64)(INT32)RTVAL32;
LOVAL64 = (INT32)temp64;
HIVAL64 = (INT32)(temp64 >> 32);
m_core->icount -= 3;
break;
case 0x19: /* MULTU */
temp64 = (UINT64)RSVAL32 * (UINT64)RTVAL32;
LOVAL64 = (INT32)temp64;
HIVAL64 = (INT32)(temp64 >> 32);
m_core->icount -= 3;
break;
case 0x1a: /* DIV */
if (RTVAL32)
{
LOVAL64 = (INT32)((INT32)RSVAL32 / (INT32)RTVAL32);
HIVAL64 = (INT32)((INT32)RSVAL32 % (INT32)RTVAL32);
}
else
{
handle_integer_divide_by_zero(op);
}
m_core->icount -= 35;
break;
case 0x1b: /* DIVU */
if (RTVAL32)
{
LOVAL64 = (INT32)(RSVAL32 / RTVAL32);
HIVAL64 = (INT32)(RSVAL32 % RTVAL32);
}
else
{
handle_integer_divide_by_zero(op);
}
m_core->icount -= 35;
break;
case 0x1c: /* DMULT */
temp64 = (INT64)RSVAL64 * (INT64)RTVAL64;
LOVAL64 = temp64;
HIVAL64 = (INT64)temp64 >> 63;
m_core->icount -= 7;
break;
case 0x1d: /* DMULTU */
temp64 = (UINT64)RSVAL64 * (UINT64)RTVAL64;
LOVAL64 = temp64;
HIVAL64 = 0;
m_core->icount -= 7;
break;
case 0x1e: /* DDIV */
if (RTVAL64)
{
LOVAL64 = (INT64)RSVAL64 / (INT64)RTVAL64;
HIVAL64 = (INT64)RSVAL64 % (INT64)RTVAL64;
}
m_core->icount -= 67;
break;
case 0x1f: /* DDIVU */
if (RTVAL64)
{
LOVAL64 = RSVAL64 / RTVAL64;
HIVAL64 = RSVAL64 % RTVAL64;
}
m_core->icount -= 67;
break;
case 0x20: /* ADD */
if (ENABLE_OVERFLOWS && RSVAL32 > ~RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32);
break;
case 0x21: /* ADDU */ if (RDREG) RDVAL64 = (INT32)(RSVAL32 + RTVAL32); break;
case 0x22: /* SUB */
if (ENABLE_OVERFLOWS && RSVAL32 < RTVAL32) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32);
break;
case 0x23: /* SUBU */ if (RDREG) RDVAL64 = (INT32)(RSVAL32 - RTVAL32); break;
case 0x24: /* AND */ if (RDREG) RDVAL64 = RSVAL64 & RTVAL64; break;
case 0x25: /* OR */ if (RDREG) RDVAL64 = RSVAL64 | RTVAL64; break;
case 0x26: /* XOR */ if (RDREG) RDVAL64 = RSVAL64 ^ RTVAL64; break;
case 0x27: /* NOR */ if (RDREG) RDVAL64 = ~(RSVAL64 | RTVAL64); break;
case 0x2a: /* SLT */ if (RDREG) RDVAL64 = (INT64)RSVAL64 < (INT64)RTVAL64; break;
case 0x2b: /* SLTU */ if (RDREG) RDVAL64 = (UINT64)RSVAL64 < (UINT64)RTVAL64; break;
case 0x2c: /* DADD */
if (ENABLE_OVERFLOWS && RSVAL64 > ~RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = RSVAL64 + RTVAL64;
break;
case 0x2d: /* DADDU */ if (RDREG) RDVAL64 = RSVAL64 + RTVAL64; break;
case 0x2e: /* DSUB */
if (ENABLE_OVERFLOWS && RSVAL64 < RTVAL64) generate_exception(EXCEPTION_OVERFLOW, 1);
else if (RDREG) RDVAL64 = RSVAL64 - RTVAL64;
break;
case 0x2f: /* DSUBU */ if (RDREG) RDVAL64 = RSVAL64 - RTVAL64; break;
case 0x30: /* TGE */ if ((INT64)RSVAL64 >= (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x31: /* TGEU */ if (RSVAL64 >= RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x32: /* TLT */ if ((INT64)RSVAL64 < (INT64)RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x33: /* TLTU */ if (RSVAL64 < RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x34: /* TEQ */ if (RSVAL64 == RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x36: /* TNE */ if (RSVAL64 != RTVAL64) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x38: /* DSLL */ if (RDREG) RDVAL64 = RTVAL64 << SHIFT; break;
case 0x3a: /* DSRL */ if (RDREG) RDVAL64 = RTVAL64 >> SHIFT; break;
case 0x3b: /* DSRA */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> SHIFT; break;
case 0x3c: /* DSLL32 */ if (RDREG) RDVAL64 = RTVAL64 << (SHIFT + 32); break;
case 0x3e: /* DSRL32 */ if (RDREG) RDVAL64 = RTVAL64 >> (SHIFT + 32); break;
case 0x3f: /* DSRA32 */ if (RDREG) RDVAL64 = (INT64)RTVAL64 >> (SHIFT + 32); break;
default: /* ??? */ invalid_instruction(op); break;
}
break; break;
case 0x01: /* REGIMM */ case 0x01: /* REGIMM */
switch (RTREG) handle_regimm(op);
{
case 0x00: /* BLTZ */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); break;
case 0x01: /* BGEZ */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); break;
case 0x02: /* BLTZL */ if ((INT64)RSVAL64 < 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
case 0x03: /* BGEZL */ if ((INT64)RSVAL64 >= 0) ADDPC(SIMMVAL); else m_core->pc += 4; break;
case 0x08: /* TGEI */ if ((INT64)RSVAL64 >= SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x09: /* TGEIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0a: /* TLTI */ if ((INT64)RSVAL64 < SIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0b: /* TLTIU */ if (RSVAL64 >= UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0c: /* TEQI */ if (RSVAL64 == UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x0e: /* TNEI */ if (RSVAL64 != UIMMVAL) generate_exception(EXCEPTION_TRAP, 1); break;
case 0x10: /* BLTZAL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31); break;
case 0x11: /* BGEZAL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31); break;
case 0x12: /* BLTZALL */ if ((INT64)RSVAL64 < 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
case 0x13: /* BGEZALL */ if ((INT64)RSVAL64 >= 0) ADDPCL(SIMMVAL,31) else m_core->pc += 4; break;
default: /* ??? */ invalid_instruction(op); break;
}
break; break;
case 0x02: /* J */ ABSPC(LIMMVAL); break; case 0x02: /* J */ ABSPC(LIMMVAL); break;
@ -2819,34 +2857,34 @@ void mips3_device::execute_run()
case 0x36: /* LDC2 */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop2_reg(RTREG, temp64); break; case 0x36: /* LDC2 */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64)) set_cop2_reg(RTREG, temp64); break;
case 0x37: /* LD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; break; case 0x37: /* LD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) RTVAL64 = temp64; break;
case 0x38: /* SC */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG) case 0x38: /* SC */ if (RWORD(SIMMVAL+RSVAL32, &temp) && RTREG)
{ {
if (temp == m_ll_value) if (temp == m_ll_value)
{ {
WWORD(SIMMVAL+RSVAL32, RTVAL32); WWORD(SIMMVAL+RSVAL32, RTVAL32);
RTVAL64 = (UINT32)1; RTVAL64 = (UINT32)1;
} }
else else
{ {
RTVAL64 = (UINT32)0; RTVAL64 = (UINT32)0;
} }
} }
break; break;
case 0x39: /* SWC1 */ WWORD(SIMMVAL+RSVAL32, get_cop1_reg32(RTREG)); break; case 0x39: /* SWC1 */ WWORD(SIMMVAL+RSVAL32, get_cop1_reg32(RTREG)); break;
case 0x3a: /* SWC2 */ WWORD(SIMMVAL+RSVAL32, get_cop2_reg(RTREG)); break; case 0x3a: /* SWC2 */ WWORD(SIMMVAL+RSVAL32, get_cop2_reg(RTREG)); break;
case 0x3b: /* SWC3 */ invalid_instruction(op); break; case 0x3b: /* SWC3 */ invalid_instruction(op); break;
case 0x3c: /* SCD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG) case 0x3c: /* SCD */ if (RDOUBLE(SIMMVAL+RSVAL32, &temp64) && RTREG)
{ {
if (temp64 == m_lld_value) if (temp64 == m_lld_value)
{ {
WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); WDOUBLE(SIMMVAL+RSVAL32, RTVAL64);
RTVAL64 = 1; RTVAL64 = 1;
} }
else else
{ {
RTVAL64 = 0; RTVAL64 = 0;
} }
} }
break; break;
case 0x3d: /* SDC1 */ WDOUBLE(SIMMVAL+RSVAL32, get_cop1_reg64(RTREG)); break; case 0x3d: /* SDC1 */ WDOUBLE(SIMMVAL+RSVAL32, get_cop1_reg64(RTREG)); break;
case 0x3e: /* SDC2 */ WDOUBLE(SIMMVAL+RSVAL32, get_cop2_reg(RTREG)); break; case 0x3e: /* SDC2 */ WDOUBLE(SIMMVAL+RSVAL32, get_cop2_reg(RTREG)); break;
case 0x3f: /* SD */ WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); break; case 0x3f: /* SD */ WDOUBLE(SIMMVAL+RSVAL32, RTVAL64); break;

50
src/emu/cpu/mips/mips3.h
View File

@ -194,7 +194,7 @@ enum
MIPS3_BADVADDR MIPS3_BADVADDR
}; };
#define MIPS3_MAX_FASTRAM 4 #define MIPS3_MAX_FASTRAM 3
#define MIPS3_MAX_HOTSPOTS 16 #define MIPS3_MAX_HOTSPOTS 16
enum enum
@ -296,8 +296,9 @@ public:
TIMER_CALLBACK_MEMBER(compare_int_callback); TIMER_CALLBACK_MEMBER(compare_int_callback);
void add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
void mips3drc_set_options(UINT32 options); void mips3drc_set_options(UINT32 options);
void mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base);
void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles); void mips3drc_add_hotspot(offs_t pc, UINT32 opcode, UINT32 cycles);
protected: protected:
@ -326,6 +327,7 @@ protected:
virtual UINT32 disasm_max_opcode_bytes() const { return 4; } virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private: private:
struct internal_mips3_state struct internal_mips3_state
{ {
@ -394,6 +396,8 @@ private:
/* memory accesses */ /* memory accesses */
bool m_bigendian; bool m_bigendian;
UINT32 m_byte_xor;
UINT32 m_word_xor;
data_accessors m_memory; data_accessors m_memory;
/* cache memory */ /* cache memory */
@ -404,6 +408,16 @@ private:
vtlb_state * m_vtlb; vtlb_state * m_vtlb;
mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES]; mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES];
/* fast RAM */
UINT32 m_fastram_select;
struct
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
UINT8 readonly; /* TRUE if read-only */
void * base; /* base in memory where the RAM lives */
} m_fastram[MIPS3_MAX_FASTRAM];
UINT64 m_debugger_temp; UINT64 m_debugger_temp;
/* core state */ /* core state */
@ -442,16 +456,6 @@ private:
uml::code_handle * m_exception[18/*EXCEPTION_COUNT*/]; /* array of exception handlers */ uml::code_handle * m_exception[18/*EXCEPTION_COUNT*/]; /* array of exception handlers */
uml::code_handle * m_exception_norecover[18/*EXCEPTION_COUNT*/]; /* array of no-recover exception handlers */ uml::code_handle * m_exception_norecover[18/*EXCEPTION_COUNT*/]; /* array of no-recover exception handlers */
/* fast RAM */
UINT32 m_fastram_select;
struct
{
offs_t start; /* start of the RAM block */
offs_t end; /* end of the RAM block */
UINT8 readonly; /* TRUE if read-only */
void * base; /* base in memory where the RAM lives */
} m_fastram[MIPS3_MAX_FASTRAM];
/* hotspots */ /* hotspots */
UINT32 m_hotspot_select; UINT32 m_hotspot_select;
struct struct
@ -477,25 +481,29 @@ public:
private: private:
UINT32 compute_config_register(); UINT32 compute_config_register();
UINT32 compute_prid_register(); UINT32 compute_prid_register();
void tlb_map_entry(int tlbindex); void tlb_map_entry(int tlbindex);
void tlb_write_common(int tlbindex); void tlb_write_common(int tlbindex);
int RBYTE(offs_t address, UINT32 *result);
int RHALF(offs_t address, UINT32 *result); bool RBYTE(offs_t address, UINT32 *result);
int RWORD(offs_t address, UINT32 *result); bool RHALF(offs_t address, UINT32 *result);
int RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask); bool RWORD(offs_t address, UINT32 *result);
int RDOUBLE(offs_t address, UINT64 *result); bool RWORD_MASKED(offs_t address, UINT32 *result, UINT32 mem_mask);
int RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask); bool RDOUBLE(offs_t address, UINT64 *result);
bool RDOUBLE_MASKED(offs_t address, UINT64 *result, UINT64 mem_mask);
void WBYTE(offs_t address, UINT8 data); void WBYTE(offs_t address, UINT8 data);
void WHALF(offs_t address, UINT16 data); void WHALF(offs_t address, UINT16 data);
void WWORD(offs_t address, UINT32 data); void WWORD(offs_t address, UINT32 data);
void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask); void WWORD_MASKED(offs_t address, UINT32 data, UINT32 mem_mask);
void WDOUBLE(offs_t address, UINT64 data); void WDOUBLE(offs_t address, UINT64 data);
void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask); void WDOUBLE_MASKED(offs_t address, UINT64 data, UINT64 mem_mask);
UINT64 get_cop0_reg(int idx); UINT64 get_cop0_reg(int idx);
void set_cop0_reg(int idx, UINT64 val); void set_cop0_reg(int idx, UINT64 val);
UINT64 get_cop0_creg(int idx); UINT64 get_cop0_creg(int idx);
void set_cop0_creg(int idx, UINT64 val); void set_cop0_creg(int idx, UINT64 val);
void handle_cop0(UINT32 op); void handle_cop0(UINT32 op);
UINT32 get_cop1_reg32(int idx); UINT32 get_cop1_reg32(int idx);
UINT64 get_cop1_reg64(int idx); UINT64 get_cop1_reg64(int idx);
void set_cop1_reg32(int idx, UINT32 val); void set_cop1_reg32(int idx, UINT32 val);
@ -506,12 +514,16 @@ private:
void handle_cop1_fr1(UINT32 op); void handle_cop1_fr1(UINT32 op);
void handle_cop1x_fr0(UINT32 op); void handle_cop1x_fr0(UINT32 op);
void handle_cop1x_fr1(UINT32 op); void handle_cop1x_fr1(UINT32 op);
UINT64 get_cop2_reg(int idx); UINT64 get_cop2_reg(int idx);
void set_cop2_reg(int idx, UINT64 val); void set_cop2_reg(int idx, UINT64 val);
UINT64 get_cop2_creg(int idx); UINT64 get_cop2_creg(int idx);
void set_cop2_creg(int idx, UINT64 val); void set_cop2_creg(int idx, UINT64 val);
void handle_cop2(UINT32 op); void handle_cop2(UINT32 op);
void handle_integer_divide_by_zero(UINT32 op);
void handle_special(UINT32 op);
void handle_regimm(UINT32 op);
void lwl_be(UINT32 op); void lwl_be(UINT32 op);
void lwr_be(UINT32 op); void lwr_be(UINT32 op);
void ldl_be(UINT32 op); void ldl_be(UINT32 op);

79
src/emu/cpu/mips/mips3drc.c
View File

@ -160,9 +160,8 @@ void mips3_device::mips3drc_set_options(UINT32 options)
region region
-------------------------------------------------*/ -------------------------------------------------*/
void mips3_device::mips3drc_add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base) void mips3_device::add_fastram(offs_t start, offs_t end, UINT8 readonly, void *base)
{ {
if (!machine().options().drc()) return;
if (m_fastram_select < ARRAY_LENGTH(m_fastram)) if (m_fastram_select < ARRAY_LENGTH(m_fastram))
{ {
m_fastram[m_fastram_select].start = start; m_fastram[m_fastram_select].start = start;
@ -2054,79 +2053,15 @@ int mips3_device::generate_special(drcuml_block *block, compiler_state *compiler
return TRUE; return TRUE;
case 0x1a: /* DIV - MIPS I */ case 0x1a: /* DIV - MIPS I */
{ UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg>
if (m_drcoptions & MIPS3DRC_ACCURATE_DIVZERO) UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
{ UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
code_label divzero, done;
UML_CMP(block, R32(RTREG), 0); // cmp <rtreg>, 0
UML_JMPc(block, COND_E, divzero = compiler->labelnum++); // jmp divzero,E
UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
UML_JMP(block, done = compiler->labelnum++); // jmp done
UML_LABEL(block, divzero); // divzero:
if (m_flavor != MIPS3_TYPE_VR4300)
{
UML_MOVc(block, COND_L, I0, 0x00000001); // mov i0,0x00000001,L
UML_MOVc(block, COND_GE, I0, 0xffffffff); // mov i0,0xffffffff,GE
}
else
{
UML_MOVc(block, COND_L, I0, 0x80000001); // mov i0,0x80000001,L
UML_MOVc(block, COND_GE, I0, 0x7fffffff); // mov i0,0x7fffffff,GE
}
UML_DSEXT(block, HI64, R32(RSREG), SIZE_DWORD); // dsext hi,<rsreg>,dword
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_LABEL(block, done); // done:
}
else
{
UML_DIVS(block, I0, I1, R32(RSREG), R32(RTREG)); // divs i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
}
return TRUE; return TRUE;
}
case 0x1b: /* DIVU - MIPS I */ case 0x1b: /* DIVU - MIPS I */
if (m_drcoptions & MIPS3DRC_ACCURATE_DIVZERO) UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg>
{ UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
code_label divzero, done; UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
UML_CMP(block, R32(RTREG), 0); // cmp <rtreg>, 0
UML_JMPc(block, COND_E, divzero = compiler->labelnum++); // jmp divzero,E
UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
UML_JMP(block, done = compiler->labelnum++); // jmp done
UML_LABEL(block, divzero); // divzero:
if (m_flavor != MIPS3_TYPE_VR4300)
{
UML_MOVc(block, COND_L, I0, 0x00000001); // mov i0,0x00000001,L
UML_MOVc(block, COND_GE, I0, 0xffffffff); // mov i0,0xffffffff,GE
}
else
{
UML_MOVc(block, COND_L, I0, 0x80000001); // mov i0,0x80000001,L
UML_MOVc(block, COND_GE, I0, 0x7fffffff); // mov i0,0x7fffffff,GE
}
UML_DSEXT(block, HI64, R32(RSREG), SIZE_DWORD); // dsext hi,<rsreg>,dword
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_LABEL(block, done); // done:
}
else
{
UML_DIVU(block, I0, I1, R32(RSREG), R32(RTREG)); // divu i0,i1,<rsreg>,<rtreg>
UML_DSEXT(block, LO64, I0, SIZE_DWORD); // dsext lo,i0,dword
UML_DSEXT(block, HI64, I1, SIZE_DWORD); // dsext hi,i1,dword
}
return TRUE; return TRUE;
case 0x1e: /* DDIV - MIPS III */ case 0x1e: /* DDIV - MIPS III */

8
src/mame/drivers/hng64.c
View File

@ -1490,10 +1490,10 @@ void hng64_state::machine_start()
/* set the fastest DRC options */ /* set the fastest DRC options */
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
/* configure fast RAM regions for DRC */ /* configure fast RAM regions */
m_maincpu->mips3drc_add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram); m_maincpu->add_fastram(0x00000000, 0x00ffffff, FALSE, m_mainram);
m_maincpu->mips3drc_add_fastram(0x04000000, 0x05ffffff, TRUE, m_cart); m_maincpu->add_fastram(0x04000000, 0x05ffffff, TRUE, m_cart);
m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
m_comm_rom = memregion("user2")->base(); m_comm_rom = memregion("user2")->base();
m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000); m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000);

8
src/mame/drivers/kinst.c
View File

@ -203,10 +203,10 @@ void kinst_state::machine_start()
/* set the fastest DRC options */ /* set the fastest DRC options */
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS); m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS);
/* configure fast RAM regions for DRC */ /* configure fast RAM regions */
m_maincpu->mips3drc_add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2); m_maincpu->add_fastram(0x08000000, 0x087fffff, FALSE, m_rambase2);
m_maincpu->mips3drc_add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase); m_maincpu->add_fastram(0x00000000, 0x0007ffff, FALSE, m_rambase);
m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
} }

2
src/mame/drivers/namcos23.c
View File

@ -3223,7 +3223,7 @@ void namcos23_state::machine_start()
m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this)); m_c361.timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namcos23_state::c361_timer_cb),this));
m_c361.timer->adjust(attotime::never); m_c361.timer->adjust(attotime::never);
m_maincpu->mips3drc_add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr())); m_maincpu->add_fastram(0, m_mainram.bytes()-1, FALSE, reinterpret_cast<UINT32 *>(memshare("mainram")->ptr()));
} }

6
src/mame/drivers/seattle.c
View File

@ -566,9 +566,9 @@ void seattle_state::machine_start()
/* set the fastest DRC options, but strict verification */ /* set the fastest DRC options, but strict verification */
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY); m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
/* configure fast RAM regions for DRC */ /* configure fast RAM regions */
m_maincpu->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase); m_maincpu->add_fastram(0x00000000, 0x007fffff, FALSE, m_rambase);
m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
/* register for save states */ /* register for save states */
save_item(NAME(m_galileo.reg)); save_item(NAME(m_galileo.reg));

6
src/mame/drivers/vegas.c
View File

@ -595,9 +595,9 @@ void vegas_state::machine_start()
/* set the fastest DRC options, but strict verification */ /* set the fastest DRC options, but strict verification */
m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC); m_maincpu->mips3drc_set_options(MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
/* configure fast RAM regions for DRC */ /* configure fast RAM regions */
m_maincpu->mips3drc_add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase); m_maincpu->add_fastram(0x00000000, m_rambase.bytes() - 1, FALSE, m_rambase);
m_maincpu->mips3drc_add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase); m_maincpu->add_fastram(0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
/* register for save states */ /* register for save states */
save_item(NAME(m_nile_irq_state)); save_item(NAME(m_nile_irq_state));

14
src/mame/machine/n64.c
View File

@ -1458,7 +1458,7 @@ void n64_periphs::pi_dma_tick()
//pi_status |= 8; // Set INTERRUPT ?? Does this bit exist ?? //pi_status |= 8; // Set INTERRUPT ?? Does this bit exist ??
if(update_bm) if(update_bm)
dd_update_bm(); dd_update_bm();
signal_rcp_interrupt(PI_INTERRUPT); signal_rcp_interrupt(PI_INTERRUPT);
@ -2189,7 +2189,7 @@ void n64_periphs::dd_update_bm()
{ {
if(((dd_track_reg & 0xFFF) == 6) && (dd_start_block == 0)) if(((dd_track_reg & 0xFFF) == 6) && (dd_start_block == 0))
{ {
dd_status_reg &= ~DD_ASIC_STATUS_DREQ; dd_status_reg &= ~DD_ASIC_STATUS_DREQ;
} }
else if(dd_current_reg < SECTORS_PER_BLOCK) else if(dd_current_reg < SECTORS_PER_BLOCK)
{ {
@ -2239,7 +2239,7 @@ void n64_periphs::dd_write_sector()
sector += (dd_current_reg - 1) * ddZoneSecSize[dd_zone]; sector += (dd_current_reg - 1) * ddZoneSecSize[dd_zone];
//logerror("Write Block %d, Sector %d\n", dd_start_block, dd_current_reg - 1); //logerror("Write Block %d, Sector %d\n", dd_start_block, dd_current_reg - 1);
for(int i = 0; i < ddZoneSecSize[dd_zone]/4; i++) for(int i = 0; i < ddZoneSecSize[dd_zone]/4; i++)
{ {
sector[i*4 + 0] = (dd_sector_data[i] >> 24) & 0xFF; sector[i*4 + 0] = (dd_sector_data[i] >> 24) & 0xFF;
@ -2492,12 +2492,12 @@ WRITE32_MEMBER( n64_periphs::dd_reg_w )
logerror("dd BM Status write\n"); logerror("dd BM Status write\n");
dd_start_sector = (data >> 16) & 0xFF; dd_start_sector = (data >> 16) & 0xFF;
if(dd_start_sector == 0x00) if(dd_start_sector == 0x00)
{ {
dd_start_block = 0; dd_start_block = 0;
dd_current_reg = 0; dd_current_reg = 0;
} }
else if (dd_start_sector == 0x5A) else if (dd_start_sector == 0x5A)
{ {
dd_start_block = 1; dd_start_block = 1;
dd_current_reg = 0; dd_current_reg = 0;
} }
@ -2620,8 +2620,8 @@ void n64_state::machine_start()
dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS); dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_set_options(MIPS3DRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */ /* configure fast RAM regions */
dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram); dynamic_cast<mips3_device *>(machine().device("maincpu"))->add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
rsp_device *rsp = machine().device<rsp_device>("rsp"); rsp_device *rsp = machine().device<rsp_device>("rsp");
rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY); rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);