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mcs96: Fix V setting on divb [O. Galibert]

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This commit is contained in:
Olivier Galibert 2012-12-18 09:36:12 +00:00
parent 30f660cc76
commit 4e8389ee4f
1 changed files with 2 additions and 2 deletions
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4
src/emu/cpu/mcs96/mcs96ops.lst
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@ -1157,7 +1157,7 @@ fe9c divb direct_2
if(OP1) {
TMP = reg_r16(OP2);
UINT32 TMP2 = INT16(TMP) / INT8(OP1);
if(INT8(TMP2) > 127 || INT8(TMP2) < -128)
if(INT16(TMP2) > 127 || INT16(TMP2) < -128)
PSW |= F_V|F_VT;
TMP = INT16(TMP) % INT8(OP1);
TMP = (TMP2 & 0xff) | ((TMP & 0xff) << 8);
@ -1170,7 +1170,7 @@ fe9d divb immed_2b
if(OP1) {
TMP = reg_r16(OP2);
UINT32 TMP2 = INT16(TMP) / INT8(OP1);
if(INT8(TMP2) > 127 || INT8(TMP2) < -128)
if(INT16(TMP2) > 127 || INT16(TMP2) < -128)
PSW |= F_V|F_VT;
TMP = INT16(TMP) % INT8(OP1);
TMP = (TMP2 & 0xff) | ((TMP & 0xff) << 8);