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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
added mb8421 to segaybd.c pdriftl. untested, since linkcpu doesnt enable interrupts?
This commit is contained in:
Michaël Banaan Ananas
parent
267b7da48a
commit
4e93ebed36
@ -4,6 +4,10 @@
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Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
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CMOS 16K-bit (2KB) dual-port SRAM
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MB84x2 lacks interrupt pins, it's basically as simple as AM_RAM AM_SHARE("x")
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MB843x is same as MB842x, except that it supports slave mode. It makes
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sure there are no clashes, with the _BUSY pin.
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**********************************************************************/
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@ -30,6 +30,7 @@
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#include "cpu/z80/z80.h"
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#include "includes/segaybd.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/mb8421.h"
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#include "machine/segaic16.h"
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#include "machine/nvram.h"
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#include "sound/2151intf.h"
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@ -45,7 +46,6 @@
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const UINT32 MASTER_CLOCK = 50000000;
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const UINT32 SOUND_CLOCK = 32215900;
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const UINT32 LINK_CLOCK = XTAL_16MHz;
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// use this to fiddle with the IRQ2 timing
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#define TWEAK_IRQ2_SCANLINE (0)
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@ -651,32 +651,6 @@ void segaybd_state::update_irqs()
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}
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READ16_MEMBER(segaybd_state::link_r)
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{
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return rand();
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}
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READ16_MEMBER(segaybd_state::link2_r)
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{
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return 0x0000;
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}
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WRITE16_MEMBER(segaybd_state::link2_w)
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{
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data &= mem_mask;
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logerror("link2_w %04x\n", data);
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}
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READ8_MEMBER(segaybd_state::linkram_r)
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{
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return m_linkram[offset];
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}
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WRITE8_MEMBER(segaybd_state::linkram_w)
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{
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m_linkram[offset] = data;
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}
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//**************************************************************************
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// MAIN CPU ADDRESS MAPS
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//**************************************************************************
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@ -695,13 +669,6 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, segaybd_state )
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AM_RANGE(0x1f0000, 0x1fffff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( main_map_link, AS_PROGRAM, 16, segaybd_state )
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AM_RANGE(0x190000, 0x190fff) AM_READWRITE8(linkram_r, linkram_w, 0x00ff) // ram to share with link CPU?
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AM_RANGE(0x191000, 0x191001) AM_READ(link_r)
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AM_RANGE(0x192000, 0x192001) AM_READWRITE(link2_r, link2_w)
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AM_IMPORT_FROM(main_map)
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ADDRESS_MAP_END
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//**************************************************************************
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// SUB CPU ADDRESS MAPS
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@ -734,7 +701,6 @@ static ADDRESS_MAP_START( suby_map, AS_PROGRAM, 16, segaybd_state )
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ADDRESS_MAP_END
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//**************************************************************************
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// Z80 SOUND CPU ADDRESS MAPS
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//**************************************************************************
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@ -753,15 +719,54 @@ static ADDRESS_MAP_START( sound_portmap, AS_IO, 8, segaybd_state )
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AM_RANGE(0x40, 0x40) AM_MIRROR(0x3f) AM_READ(sound_data_r)
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ADDRESS_MAP_END
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//**************************************************************************
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// Z80 LINK BOARD CPU ADDRESS MAPS
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// LINK BOARD
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//**************************************************************************
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WRITE_LINE_MEMBER(segaybd_state::mb8421_intl)
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{
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// shared ram interrupt request from linkcpu side
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// unused?
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}
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WRITE_LINE_MEMBER(segaybd_state::mb8421_intr)
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{
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// shared ram interrupt request from maincpu side
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m_linkcpu->set_input_line_and_vector(0, state ? ASSERT_LINE : CLEAR_LINE, 0xef); // RST $28
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}
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READ16_MEMBER(segaybd_state::link_r)
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{
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return rand();
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}
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READ16_MEMBER(segaybd_state::link2_r)
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{
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return 0x0000;
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}
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WRITE16_MEMBER(segaybd_state::link2_w)
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{
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data &= mem_mask;
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logerror("link2_w %04x\n", data);
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}
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static ADDRESS_MAP_START( main_map_link, AS_PROGRAM, 16, segaybd_state )
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AM_RANGE(0x190000, 0x190fff) AM_DEVREADWRITE8("mb8421", mb8421_device, left_r, left_w, 0x00ff)
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AM_RANGE(0x191000, 0x191001) AM_READ(link_r)
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AM_RANGE(0x192000, 0x192001) AM_READWRITE(link2_r, link2_w)
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AM_IMPORT_FROM(main_map)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( link_map, AS_PROGRAM, 8, segaybd_state )
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE(0x0000, 0x0fff) AM_ROM
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AM_RANGE(0x2000, 0x3fff) AM_RAM
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AM_RANGE(0x4000, 0x47ff) AM_RAM AM_SHARE("linkram") // MB8421
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AM_RANGE(0x4000, 0x47ff) AM_DEVREADWRITE("mb8421", mb8421_device, right_r, right_w)
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ADDRESS_MAP_END
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READ8_MEMBER(segaybd_state::link_portc0_r)
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@ -773,11 +778,11 @@ static ADDRESS_MAP_START( link_portmap, AS_IO, 8, segaybd_state )
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ADDRESS_MAP_UNMAP_HIGH
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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// AM_RANGE(0x40, 0x40) AM_READ_PORT("LinkDSW")
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// AM_RANGE(0x40, 0x40) AM_READ_PORT("LinkDSW")
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AM_RANGE(0xc0, 0xc0) AM_READ(link_portc0_r)
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ADDRESS_MAP_END
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//**************************************************************************
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// GENERIC PORT DEFINITIONS
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//**************************************************************************
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@ -1336,16 +1341,23 @@ static MACHINE_CONFIG_START( yboard, segaybd_state )
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MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
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MACHINE_CONFIG_END
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// LINK PCB is 834-6740
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// has 1x 8 switch dip bank, z80E CPU, ribbon connector? (to main board?), RX/TX ports, 16Mhz OSC
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// LINK PCB is 834-6740, similar to the one for Super Monaco GP
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// has 1x 8 switch dip bank, Z80E CPU, ribbon connector? (to main board?), RX/TX ports, 16Mhz OSC,
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// MB8421 DPSRAM, MB89372 (UART?)
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// irq at 0x28 is from mb8421, and irq at 0x38 probably from uart?
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static MACHINE_CONFIG_DERIVED( yboard_link, yboard )
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// basic machine hardware
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MCFG_CPU_MODIFY("maincpu")
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MCFG_CPU_PROGRAM_MAP(main_map_link)
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MCFG_CPU_ADD("linkcpu", Z80, LINK_CLOCK/2 ) // 8 mhz?
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MCFG_CPU_ADD("linkcpu", Z80, XTAL_16MHz/2 ) // 8 mhz?
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MCFG_CPU_PROGRAM_MAP(link_map)
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MCFG_CPU_IO_MAP(link_portmap)
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// valid code at 0x28 and 0x38
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MCFG_DEVICE_ADD("mb8421", MB8421, 0)
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MCFG_MB8421_INTL_HANDLER(WRITELINE(segaybd_state, mb8421_intl))
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MCFG_MB8421_INTR_HANDLER(WRITELINE(segaybd_state, mb8421_intr))
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MACHINE_CONFIG_END
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//**************************************************************************
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@ -457,11 +457,13 @@ static const int dendego_pressure_table[0x100] =
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WRITE_LINE_MEMBER(taitojc_state::mb8421_intl)
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{
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// shared ram interrupt request from dsp side
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m_maincpu->set_input_line(6, state ? ASSERT_LINE : CLEAR_LINE);
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}
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WRITE_LINE_MEMBER(taitojc_state::mb8421_intr)
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{
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// shared ram interrupt request from maincpu side
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// this is hacky, acquiring the internal dsp romdump should allow it to be cleaned up
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if (state)
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{
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@ -25,6 +25,7 @@ public:
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m_subx(*this, "subx"),
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m_suby(*this, "suby"),
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m_soundcpu(*this, "soundcpu"),
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m_linkcpu(*this, "linkcpu"),
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m_bsprites(*this, "bsprites"),
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m_ysprites(*this, "ysprites"),
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m_segaic16vid(*this, "segaic16vid"),
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@ -33,8 +34,7 @@ public:
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m_irq2_scanline(0),
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m_timer_irq_state(0),
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m_vblank_irq_state(0),
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m_tmp_bitmap(512, 512),
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m_linkram(*this, "linkram")
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m_tmp_bitmap(512, 512)
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{
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memset(m_analog_data, 0, sizeof(m_analog_data));
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memset(m_misc_io_data, 0, sizeof(m_misc_io_data));
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@ -53,6 +53,14 @@ public:
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// sound Z80 CPU read/write handlers
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DECLARE_READ8_MEMBER( sound_data_r );
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// linked cabinet specific handlers
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DECLARE_WRITE_LINE_MEMBER( mb8421_intl );
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DECLARE_WRITE_LINE_MEMBER( mb8421_intr );
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DECLARE_READ16_MEMBER( link_r );
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DECLARE_READ16_MEMBER( link2_r );
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DECLARE_WRITE16_MEMBER( link2_w );
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DECLARE_READ8_MEMBER( link_portc0_r );
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// game-specific output handlers
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void gforce2_output_cb2(UINT16 data);
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void gloc_output_cb1(UINT16 data);
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@ -97,6 +105,7 @@ protected:
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required_device<m68000_device> m_subx;
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required_device<m68000_device> m_suby;
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required_device<z80_device> m_soundcpu;
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optional_device<z80_device> m_linkcpu;
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required_device<sega_sys16b_sprite_device> m_bsprites;
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required_device<sega_yboard_sprite_device> m_ysprites;
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required_device<segaic16_video_device> m_segaic16vid;
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@ -114,17 +123,4 @@ protected:
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UINT8 m_vblank_irq_state;
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UINT8 m_misc_io_data[0x10];
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bitmap_ind16 m_tmp_bitmap;
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public:
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// linkpcb support
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DECLARE_READ16_MEMBER(link_r);
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DECLARE_READ16_MEMBER(link2_r);
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DECLARE_WRITE16_MEMBER(link2_w);
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DECLARE_READ8_MEMBER(linkram_r);
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DECLARE_WRITE8_MEMBER(linkram_w);
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DECLARE_READ8_MEMBER(link_portc0_r);
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optional_shared_ptr<UINT8> m_linkram;
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};
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