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https://github.com/holub/mame
synced 2025-04-20 15:32:45 +03:00
sym1: fixed crash at start, added POR circuit.
This commit is contained in:
Robbbert
parent
ed624da99d
commit
4f01783c9f
@ -40,20 +40,16 @@ class sym1_state : public driver_device
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{
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public:
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sym1_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_ram_1k(*this, "ram_1k"),
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m_ram_2k(*this, "ram_2k"),
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m_ram_3k(*this, "ram_3k"),
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m_monitor(*this, "monitor"),
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m_riot_ram(*this, "riot_ram"),
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m_maincpu(*this, "maincpu"),
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m_ram(*this, RAM_TAG),
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m_ttl74145(*this, "ttl74145"),
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m_crt(*this, "crt"),
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m_tty(*this, "tty"),
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m_row(*this, "ROW-%u", 0),
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m_wp(*this, "WP"),
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m_digits(*this, "digit%u", 0U)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_ram(*this, RAM_TAG)
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, m_banks(*this, "bank%u", 0U)
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, m_ttl74145(*this, "ttl74145")
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, m_crt(*this, "crt")
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, m_tty(*this, "tty")
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, m_row(*this, "ROW-%u", 0U)
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, m_wp(*this, "WP")
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, m_digits(*this, "digit%u", 0U)
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{ }
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void sym1(machine_config &config);
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@ -61,11 +57,6 @@ public:
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void init_sym1();
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private:
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required_shared_ptr<uint8_t> m_ram_1k;
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required_shared_ptr<uint8_t> m_ram_2k;
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required_shared_ptr<uint8_t> m_ram_3k;
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required_shared_ptr<uint8_t> m_monitor;
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required_shared_ptr<uint8_t> m_riot_ram;
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uint8_t m_riot_port_a;
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uint8_t m_riot_port_b;
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emu_timer *m_led_update;
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@ -78,16 +69,20 @@ private:
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DECLARE_WRITE_LINE_MEMBER(sym1_74145_output_3_w);
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DECLARE_WRITE_LINE_MEMBER(sym1_74145_output_4_w);
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DECLARE_WRITE_LINE_MEMBER(sym1_74145_output_5_w);
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DECLARE_WRITE_LINE_MEMBER(via1_ca2_w);
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uint8_t riot_a_r();
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uint8_t riot_b_r();
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void riot_a_w(uint8_t data);
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void riot_b_w(uint8_t data);
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void via3_a_w(uint8_t data);
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std::unique_ptr<u8[]> m_riot_ram;
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std::unique_ptr<u8[]> m_dummy_ram;
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void sym1_map(address_map &map);
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required_device<m6502_device> m_maincpu;
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required_device<ram_device> m_ram;
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required_memory_bank_array<10> m_banks;
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required_device<ttl74145_device> m_ttl74145;
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required_device<rs232_port_device> m_crt;
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required_device<rs232_port_device> m_tty;
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@ -246,6 +241,13 @@ INPUT_PORTS_END
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// MACHINE EMULATION
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//**************************************************************************
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// CA2 will be forced high when the VIA is reset, causing the ROM to be switched in
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// When the bios clears POR, FF80-FFFF becomes a mirror of A67F-A6FF
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WRITE_LINE_MEMBER( sym1_state::via1_ca2_w )
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{
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m_banks[8]->set_entry(state);
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}
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/*
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PA0: Write protect R6532 RAM
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PA1: Write protect RAM 0x400-0x7ff
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@ -254,39 +256,63 @@ INPUT_PORTS_END
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*/
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void sym1_state::via3_a_w(uint8_t data)
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{
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address_space &cpu0space = m_maincpu->space( AS_PROGRAM );
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logerror("SYM1 VIA2 W 0x%02x\n", data);
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if ((m_wp->read() & 0x01) && !(data & 0x01)) {
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cpu0space.nop_write(0xa600, 0xa67f);
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} else {
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cpu0space.install_write_bank(0xa600, 0xa67f, membank("bank5"));
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}
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if ((m_wp->read() & 0x02) && !(data & 0x02)) {
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cpu0space.nop_write(0x0400, 0x07ff);
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} else {
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cpu0space.install_write_bank(0x0400, 0x07ff, membank("bank2"));
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}
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if ((m_wp->read() & 0x04) && !(data & 0x04)) {
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cpu0space.nop_write(0x0800, 0x0bff);
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} else {
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cpu0space.install_write_bank(0x0800, 0x0bff, membank("bank3"));
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}
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if ((m_wp->read() & 0x08) && !(data & 0x08)) {
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cpu0space.nop_write(0x0c00, 0x0fff);
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} else {
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cpu0space.install_write_bank(0x0c00, 0x0fff, membank("bank4"));
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u8 sw = m_wp->read();
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// apply or remove write-protection as directed
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for (u8 i = 0; i < 4; i++)
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{
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// considered readonly if DIP is on AND databit is low; OR if memory not fitted
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if ((BIT(sw, i) && !BIT(data, i)) || m_banks[i*2]->entry() )
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m_banks[i*2+1]->set_entry(1); // readonly
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else
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m_banks[i*2+1]->set_entry(0); // readwrite
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//printf("Bank %d has entry %d\n",i*2+1,m_banks[i*2+1]->entry());
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}
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// POR write is same as bank1
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m_banks[9]->set_entry(m_banks[1]->entry());
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}
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void sym1_state::init_sym1()
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{
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// wipe expansion memory banks that are not installed
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if (m_ram->size() < 4*1024)
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{
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m_maincpu->space(AS_PROGRAM).nop_readwrite(m_ram->size(), 0x0fff);
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}
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// m_ram 000-3FF not allocated to anything, so we use it as a dummy write area
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u8 *const m = memregion("maincpu")->base()+0x8f80;
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m_riot_ram = make_unique_clear<u8[]>(0x80);
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m_dummy_ram = make_unique_clear<u8[]>(0x400); // dummy read area, preset to FF
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u8 *w = m_riot_ram.get();
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u8 *x = m_dummy_ram.get();
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std::memset(x, 0xff, 0x400);
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u8 *r = m_ram->pointer();
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// RAM 400-7FF
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m_banks[2]->configure_entry(0, r+0x400); // ram exist, readable
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m_banks[2]->configure_entry(1, x); // ram not present
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m_banks[3]->configure_entry(0, r+0x400); // ram exist, writable
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m_banks[3]->configure_entry(1, r); // ram not present or readonly
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// RAM 800-BFF
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m_banks[4]->configure_entry(0, r+0x800);
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m_banks[4]->configure_entry(1, x);
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m_banks[5]->configure_entry(0, r+0x800);
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m_banks[5]->configure_entry(1, r);
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// RAM C00-FFF
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m_banks[6]->configure_entry(0, r+0xc00);
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m_banks[6]->configure_entry(1, x);
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m_banks[7]->configure_entry(0, r+0xc00);
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m_banks[7]->configure_entry(1, r);
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// RIOT RAM A600-A67F
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m_banks[0]->configure_entry(0, w); // riot ram, readable
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m_banks[0]->configure_entry(1, w);
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m_banks[1]->configure_entry(0, w); // riot ram, writable
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m_banks[1]->configure_entry(1, r); // riot ram, readonly
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// POR
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m_banks[8]->configure_entry(0, w); // point at riot-ram
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m_banks[8]->configure_entry(1, m); // point at rom
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m_banks[9]->configure_entry(0, w); // riot ram, writable
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m_banks[9]->configure_entry(1, r); // riot ram, readonly
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for (auto &bank : m_banks)
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bank->set_entry(1);
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// allocate a timer to refresh the led display
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m_led_update = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sym1_state::led_refresh), this));
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@ -294,11 +320,25 @@ void sym1_state::init_sym1()
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void sym1_state::machine_reset()
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{
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// make 0xf800 to 0xffff point to the last half of the monitor ROM
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// so that the CPU can find its reset vectors
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m_maincpu->space(AS_PROGRAM).install_rom(0xf800, 0xffff, m_monitor + 0x800);
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m_maincpu->space(AS_PROGRAM).nop_write(0xf800, 0xffff);
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m_maincpu->reset();
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// Enable extra ram if it is fitted
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switch (m_ram->size())
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{
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case 4*1024:
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m_banks[6]->set_entry(0);
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[[fallthrough]];
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case 3*1024:
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m_banks[4]->set_entry(0);
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[[fallthrough]];
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case 2*1024:
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m_banks[2]->set_entry(0);
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[[fallthrough]];
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default:
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m_banks[0]->set_entry(0);
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break;
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}
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// Enable POR
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via1_ca2_w(1);
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}
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@ -309,16 +349,17 @@ void sym1_state::machine_reset()
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void sym1_state::sym1_map(address_map &map)
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{
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map(0x0000, 0x03ff).ram(); // U12/U13 RAM
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map(0x0400, 0x07ff).bankrw("bank2").share("ram_1k");
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map(0x0800, 0x0bff).bankrw("bank3").share("ram_2k");
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map(0x0c00, 0x0fff).bankrw("bank4").share("ram_3k");
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map(0x8000, 0x8fff).rom().share("monitor"); // U20 Monitor ROM
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map(0x0400, 0x07ff).bankr("bank2").bankw("bank3"); // U14/U15 OPT RAM
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map(0x0800, 0x0bff).bankr("bank4").bankw("bank5"); // U16/U17 OPT RAM
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map(0x0c00, 0x0fff).bankr("bank6").bankw("bank7"); // U18/U19 OPT RAM
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map(0x8000, 0x8fff).rom(); // U20 Monitor ROM
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map(0xa000, 0xa00f).m("via1", FUNC(via6522_device::map)); // U25 VIA #1
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map(0xa400, 0xa41f).m("riot", FUNC(mos6532_new_device::io_map)); // U27 RIOT
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map(0xa600, 0xa67f).bankrw("bank5").share("riot_ram"); // U27 RIOT RAM
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map(0xa600, 0xa67f).bankr("bank0").bankw("bank1"); // U27 RIOT RAM
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map(0xa800, 0xa80f).m("via2", FUNC(via6522_device::map)); // U28 VIA #2
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map(0xac00, 0xac0f).m("via3", FUNC(via6522_device::map)); // U29 VIA #3
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map(0xb000, 0xefff).rom();
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map(0xff80, 0xffff).bankr("bank8").bankw("bank9"); // POR
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}
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@ -355,7 +396,10 @@ void sym1_state::sym1(machine_config &config)
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m_ttl74145->output_line_callback<6>().set("speaker", FUNC(speaker_sound_device::level_w));
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// lines 7-9 not connected
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VIA6522(config, "via1", SYM1_CLOCK).irq_handler().set("mainirq", FUNC(input_merger_device::in_w<0>));
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via6522_device &via1(VIA6522(config, "via1", SYM1_CLOCK));
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via1.irq_handler().set("mainirq", FUNC(input_merger_device::in_w<0>));
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via1.ca2_handler().set(FUNC(sym1_state::via1_ca2_w));
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VIA6522(config, "via2", SYM1_CLOCK).irq_handler().set("mainirq", FUNC(input_merger_device::in_w<1>));
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via6522_device &via3(VIA6522(config, "via3", SYM1_CLOCK));
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