diff --git a/.gitattributes b/.gitattributes
index c1d7bbb310c..e7ed5deecaf 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -380,6 +380,10 @@ src/emu/cpu/t11/t11ops.c svneol=native#text/plain
 src/emu/cpu/t11/t11table.c svneol=native#text/plain
 src/emu/cpu/tlcs90/tlcs90.c svneol=native#text/plain
 src/emu/cpu/tlcs90/tlcs90.h svneol=native#text/plain
+src/emu/cpu/tlcs900/900tbl.c svneol=native#text/plain
+src/emu/cpu/tlcs900/dasm900.c svneol=native#text/plain
+src/emu/cpu/tlcs900/tlcs900.c svneol=native#text/plain
+src/emu/cpu/tlcs900/tlcs900.h svneol=native#text/plain
 src/emu/cpu/tms32010/32010dsm.c svneol=native#text/plain
 src/emu/cpu/tms32010/dis32010.c svneol=native#text/plain
 src/emu/cpu/tms32010/tms32010.c svneol=native#text/plain
diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak
index 2b01e1432b0..fba66648b41 100644
--- a/src/emu/cpu/cpu.mak
+++ b/src/emu/cpu/cpu.mak
@@ -1420,6 +1420,24 @@ $(CPUOBJ)/tlcs90/tlcs90.o:	$(CPUSRC)/tlcs90/tlcs90.c \
 
 
 
+#-------------------------------------------------
+# Toshiba TLCS-900 Series
+#-------------------------------------------------
+
+ifneq ($(filter TLCS900,$(CPUS)),)
+OBJDIRS += $(CPUOBJ)/tlcs900
+CPUOBJS += $(CPUOBJ)/tlcs900/tlcs900.o
+DBGOBJS += $(CPUOBJ)/tlcs900/dasm900.o
+endif
+
+$(CPUOBJ)/tlcs900/tlcs900.o:	$(CPUSRC)/tlcs900/tlcs900.c \
+								$(CPUSRC)/tlcs900/900tbl.c \
+								$(CPUSRC)/tlcs900/tlcs900.h
+
+$(CPUOBJ)/tlcs900/dasm900.o:	$(CPUSRC)/tlcs900/dasm900.c
+
+
+
 #-------------------------------------------------
 # Zilog Z80
 #-------------------------------------------------
diff --git a/src/emu/cpu/tlcs900/900tbl.c b/src/emu/cpu/tlcs900/900tbl.c
new file mode 100644
index 00000000000..280c3f761aa
--- /dev/null
+++ b/src/emu/cpu/tlcs900/900tbl.c
@@ -0,0 +1,6022 @@
+/*******************************************************************
+
+TLCS-900/H instruction set
+
+*******************************************************************/
+
+
+enum e_operand
+{
+	_A=1,		/* currect register set register A */
+	_C8,		/* current register set byte */
+	_C16,		/* current register set word */
+	_C32,		/* current register set long word */
+	_MC16,		/* current register set mul/div register word */
+	_CC,		/* condition */
+	_CR8,
+	_CR16,
+	_CR32,
+	_D8,		/* byte displacement */
+	_D16,		/* word displacement */
+	_F,			/* F register */
+	_I3,		/* immediate 3 bit (part of last byte) */
+	_I8,		/* immediate byte */
+	_I16,		/* immediate word */
+	_I24,		/* immediate 3 byte address */
+	_I32,		/* immediate long word */
+	_M,			/* memory location (defined by extension) */
+	_M8,		/* (8) */
+	_M16,		/* (i16) */
+	_R,		/* register (defined by extension) */
+	_SR,		/* status register */
+};
+
+
+INLINE int condition_true( tlcs900_state *cpustate, UINT8 cond )
+{
+	switch ( cond & 0x0f )
+	{
+	/* F */
+	case 0x00:
+		return 0;
+
+	/* LT */
+	case 0x01:
+		return ( ( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
+			( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) );
+
+	/* LE */
+	case 0x02:
+		return ( ( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
+			( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) ||
+			( cpustate->sr.b.l & FLAG_ZF ) );
+
+	/* ULE */
+	case 0x03:
+		return ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_CF ) );
+
+	/* OV */
+	case 0x04:
+		return ( cpustate->sr.b.l & FLAG_VF );
+
+	/* MI */
+	case 0x05:
+		return ( cpustate->sr.b.l & FLAG_SF );
+
+	/* Z */
+	case 0x06:
+		return ( cpustate->sr.b.l & FLAG_ZF );
+
+	/* C */
+	case 0x07:
+		return ( cpustate->sr.b.l & FLAG_CF );
+
+	/* T */
+	case 0x08:
+		return 1;
+
+	/* GE */
+	case 0x09:
+		return ! ( ( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
+			( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) );
+
+	/* GT */
+	case 0x0A:
+		return ! ( ( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
+			( ( cpustate->sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) ||
+			( cpustate->sr.b.l & FLAG_ZF ) );
+
+	/* UGT */
+	case 0x0B:
+		return ! ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_CF ) );
+
+	/* NOV */
+	case 0x0C:
+		return ! ( cpustate->sr.b.l & FLAG_VF );
+
+	/* PL */
+	case 0x0D:
+		return ! ( cpustate->sr.b.l & FLAG_SF );
+
+	/* NZ */
+	case 0x0E:
+		return ! ( cpustate->sr.b.l & FLAG_ZF );
+
+	/* NC */
+	case 0x0F:
+		return ! ( cpustate->sr.b.l & FLAG_CF );
+	}
+	return 0;
+}
+
+
+INLINE UINT8 *get_reg8_current( tlcs900_state *cpustate, UINT8 reg )
+{
+	switch( reg & 7 )
+	{
+	/* W */
+	case 0:
+		return &cpustate->xwa[cpustate->regbank].b.h;
+
+	/* A */
+	case 1:
+		return &cpustate->xwa[cpustate->regbank].b.l;
+
+	/* B */
+	case 2:
+		return &cpustate->xbc[cpustate->regbank].b.h;
+
+	/* C */
+	case 3:
+		return &cpustate->xbc[cpustate->regbank].b.l;
+
+	/* D */
+	case 4:
+		return &cpustate->xde[cpustate->regbank].b.h;
+
+	/* E */
+	case 5:
+		return &cpustate->xde[cpustate->regbank].b.l;
+
+	/* H */
+	case 6:
+		return &cpustate->xhl[cpustate->regbank].b.h;
+
+	/* L */
+	case 7:
+		return &cpustate->xhl[cpustate->regbank].b.l;
+	}
+	/* keep compiler happy */
+	return &cpustate->dummy.b.l;
+}
+
+
+INLINE UINT16 *get_reg16_current( tlcs900_state *cpustate, UINT8 reg )
+{
+	switch( reg & 7 )
+	{
+	/* WA */
+	case 0:
+		return &cpustate->xwa[cpustate->regbank].w.l;
+
+	/* BC */
+	case 1:
+		return &cpustate->xbc[cpustate->regbank].w.l;
+
+	/* DE */
+	case 2:
+		return &cpustate->xde[cpustate->regbank].w.l;
+
+	/* HL */
+	case 3:
+		return &cpustate->xhl[cpustate->regbank].w.l;
+
+	/* IX */
+	case 4:
+		return &cpustate->xix.w.l;
+
+	/* IY */
+	case 5:
+		return &cpustate->xiy.w.l;
+
+	/* IZ */
+	case 6:
+		return &cpustate->xiz.w.l;
+
+	/* SP */
+	/* TODO: Use correct user/system SP */
+	case 7:
+		return &cpustate->xssp.w.l;
+	}
+	/* keep compiler happy */
+	return &cpustate->dummy.w.l;
+}
+
+
+INLINE UINT32 *get_reg32_current( tlcs900_state *cpustate, UINT8 reg )
+{
+	switch( reg & 7 )
+	{
+	/* XWA */
+	case 0:
+		return &cpustate->xwa[cpustate->regbank].d;
+
+	/* XBC */
+	case 1:
+		return &cpustate->xbc[cpustate->regbank].d;
+
+	/* XDE */
+	case 2:
+		return &cpustate->xde[cpustate->regbank].d;
+
+	/* XHL */
+	case 3:
+		return &cpustate->xhl[cpustate->regbank].d;
+
+	/* XIX */
+	case 4:
+		return &cpustate->xix.d;
+
+	/* XIY */
+	case 5:
+		return &cpustate->xiy.d;
+
+	/* XIZ */
+	case 6:
+		return &cpustate->xiz.d;
+
+	/* XSP */
+	case 7: 
+		/* TODO: Add selector for user/system stack pointer */
+		return &cpustate->xssp.d;
+	}
+	/* keep compiler happy */
+	return &cpustate->dummy.d;
+}
+
+
+INLINE PAIR *get_reg( tlcs900_state *cpustate, UINT8 reg )
+{
+	UINT8	regbank;
+
+	switch( reg & 0xf0 )
+	{
+	case 0x00: case 0x10: case 0x20: case 0x30:	/* explicit register bank */
+	case 0xd0:									/* "previous" register bank */
+	case 0xe0:									/* current register bank */
+		regbank = ( reg & 0xf0 ) >> 4;
+		if ( regbank == 0x0d )
+			regbank = ( cpustate->regbank - 1 ) & 0x03;
+
+		if ( regbank == 0x0e )
+			regbank = cpustate->regbank;
+
+		switch ( reg & 0x0c )
+		{
+		case 0x00:	return &cpustate->xwa[regbank];
+		case 0x04:	return &cpustate->xbc[regbank];
+		case 0x08:	return &cpustate->xde[regbank];
+		case 0x0c:	return &cpustate->xhl[regbank];
+		}
+		break;
+	case 0xf0:	/* index registers and sp */
+		switch ( reg & 0x0c )
+		{
+		case 0x00:	return &cpustate->xix;
+		case 0x04:	return &cpustate->xiy;
+		case 0x08:	return &cpustate->xiz;
+		/* TODO: Use correct SP */
+		case 0x0c:	return &cpustate->xssp;
+		}
+		break;
+	}
+
+	/* illegal/unknown register reference */
+	logerror( "Access to unknown tlcs-900 cpu register %02x\n", reg );
+	return &cpustate->dummy;
+}
+
+
+INLINE UINT8 *get_reg8( tlcs900_state *cpustate, UINT8 reg )
+{
+	PAIR	*r = get_reg( cpustate, reg );
+
+	switch ( reg & 0x03 )
+	{
+	case 0x00:		return &r->b.l;
+	case 0x01:		return &r->b.h;
+	case 0x02:		return &r->b.h2;
+	case 0x03:		return &r->b.h3;
+	}
+
+	return &r->b.l;
+}
+
+
+INLINE UINT16 *get_reg16( tlcs900_state *cpustate, UINT8 reg )
+{
+	PAIR	*r = get_reg( cpustate, reg );
+
+	return ( reg & 0x02 ) ? &r->w.h : &r->w.l;
+}
+
+
+INLINE UINT32 *get_reg32( tlcs900_state *cpustate, UINT8 reg )
+{
+	PAIR	*r = get_reg( cpustate, reg );
+
+	return &r->d;
+}
+
+
+
+INLINE void parity8( tlcs900_state *cpustate, UINT8 a )
+{
+	int	i, j;
+
+	j = 0;
+	for ( i = 0; i < 8; i++ )
+	{
+		if ( a & 1 ) j++;
+		a >>= 1;
+	}
+	cpustate->sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
+}
+
+
+INLINE void parity16( tlcs900_state *cpustate, UINT16 a )
+{
+	int	i, j;
+
+	j = 0;
+	for ( i = 0; i < 16; i++ )
+	{
+		if ( a & 1 ) j++;
+		a >>= 1;
+	}
+	cpustate->sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
+}
+
+
+INLINE void parity32( tlcs900_state *cpustate, UINT32 a )
+{
+	int	i, j;
+
+	j = 0;
+	for ( i = 0; i < 32; i++ )
+	{
+		if ( a & 1 ) j++;
+		a >>= 1;
+	}
+	cpustate->sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
+}
+
+
+INLINE UINT8 adc8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT8 result = a + b + cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
+		( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT16 adc16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT16 result = a + b + cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
+		( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT32 adc32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT32 result = a + b + cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
+		( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT8 add8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 result = a + b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
+		( ( result < a ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT16 add16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT16 result = a + b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
+		( ( result < a ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT32 add32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT32 result = a + b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( result ^ a ) & ( result ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
+		( ( result < a ) ? FLAG_CF : 0 );
+
+	return result;
+}
+
+
+INLINE UINT8 sbc8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT8 result = a - b - cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
+		( ( ( result > a ) || ( cy && b == 0xFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT16 sbc16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT16 result = a - b - cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
+		( ( ( result > a ) || ( cy && b == 0xFFFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT32 sbc32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT8 cy = cpustate->sr.b.l & FLAG_CF;
+	UINT32 result = a - b - cy;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
+		( ( ( result > a ) || ( cy && b == 0xFFFFFFFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT8 sub8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 result = a - b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
+		( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT16 sub16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT16 result = a - b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
+		( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT32 sub32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT32 result = a - b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
+		( ( ( result ^ a ) & ( a ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
+		( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
+
+	return result;
+}
+
+
+INLINE UINT8 and8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 result = a & b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
+
+	parity8( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT16 and16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT16 result = a & b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
+
+	parity16( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT32 and32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT32 result = a & b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
+
+	return result;
+}
+
+
+INLINE UINT8 or8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 result = a | b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	parity8( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT16 or16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT16 result = a | b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	parity16( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT32 or32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT32 result = a | b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	return result;
+}
+
+
+INLINE UINT8 xor8( tlcs900_state *cpustate, UINT8 a, UINT8 b)
+{
+	UINT8 result = a ^ b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	parity8( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT16 xor16( tlcs900_state *cpustate, UINT16 a, UINT16 b)
+{
+	UINT16 result = a ^ b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	parity16( cpustate, result );
+
+	return result;
+}
+
+
+INLINE UINT32 xor32( tlcs900_state *cpustate, UINT32 a, UINT32 b)
+{
+	UINT32 result = a ^ b;
+
+	cpustate->sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
+	cpustate->sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
+
+	return result;
+}
+
+
+INLINE void ldcf8( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x07 ) ) )
+		cpustate->sr.b.l |= FLAG_CF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_CF;
+}
+
+
+INLINE void ldcf16( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x0f ) ) )
+		cpustate->sr.b.l |= FLAG_CF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_CF;
+}
+
+
+INLINE void andcf8( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( ( b & ( 1 << ( a & 0x07 ) ) ) && ( cpustate->sr.b.l & FLAG_CF ) )
+		cpustate->sr.b.l |= FLAG_CF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_CF;
+}
+
+
+INLINE void andcf16( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( ( b & ( 1 << ( a & 0x0f ) ) ) && ( cpustate->sr.b.l & FLAG_CF ) )
+		cpustate->sr.b.l |= FLAG_CF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_CF;
+}
+
+
+INLINE void orcf8( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x07 ) ) )
+		cpustate->sr.b.l |= FLAG_CF;
+}
+
+
+INLINE void orcf16( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x0f ) ) )
+		cpustate->sr.b.l |= FLAG_CF;
+}
+
+
+INLINE void xorcf8( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x07 ) ) )
+		cpustate->sr.b.l ^= FLAG_CF;
+}
+
+
+INLINE void xorcf16( tlcs900_state *cpustate, UINT8 a, UINT8 b )
+{
+	if ( b & ( 1 << ( a & 0x0f ) ) )
+		cpustate->sr.b.l ^= FLAG_CF;
+}
+
+
+INLINE UINT8 rl8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( a & 0x80 )
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l |= FLAG_CF;
+		}
+		else
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l &= ~ FLAG_CF;
+		}
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 rl16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( a & 0x8000 )
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l |= FLAG_CF;
+		}
+		else
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l &= ~ FLAG_CF;
+		}
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 rl32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( a & 0x80000000 )
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l |= FLAG_CF;
+		}
+		else
+		{
+			a = ( a << 1 ) | ( cpustate->sr.b.l & FLAG_CF );
+			cpustate->sr.b.l &= ~ FLAG_CF;
+		}
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+INLINE UINT8 rlc8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a << 1 ) | ( ( a & 0x80 ) ? 1 : 0 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 rlc16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a << 1 ) | ( ( a & 0x8000 ) ? 1 : 0 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 rlc32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a << 1 ) | ( ( a & 0x80000000 ) ? 1 : 0 );
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT8 rr8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( cpustate->sr.b.l & FLAG_CF )
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 ) | 0x80;
+		}
+		else
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 );
+		}
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 rr16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( cpustate->sr.b.l & FLAG_CF )
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 ) | 0x8000;
+		}
+		else
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 );
+		}
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 rr32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		if ( cpustate->sr.b.l & FLAG_CF )
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 ) | 0x80000000;
+		}
+		else
+		{
+			cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+			a = ( a >> 1 );
+		}
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT8 rrc8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a >> 1 ) | ( ( a & 0x01 ) ? 0x80 : 0 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( a & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 rrc16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a >> 1 ) | ( ( a & 0x0001 ) ? 0x8000 : 0 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( ( a >> 8 ) & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 rrc32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		a = ( a >> 1 ) | ( ( a & 0x00000001 ) ? 0x80000000 : 0 );
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( ( a >> 24 ) & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT8 sla8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( ( a & 0x80 ) ? FLAG_CF : 0 );
+		a = ( a << 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 sla16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( ( a & 0x8000 ) ? FLAG_CF : 0 );
+		a = ( a << 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 sla32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( ( a & 0x80000000 ) ? FLAG_CF : 0 );
+		a = ( a << 1 );
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT8 sra8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a & 0x80 ) | ( a >> 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 sra16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a & 0x8000 ) | ( a >> 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 sra32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a & 0x80000000 ) | ( a >> 1 );
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT8 srl8( tlcs900_state *cpustate, UINT8 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a >> 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity8( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 srl16( tlcs900_state *cpustate, UINT16 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a >> 1 );
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity16( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT32 srl32( tlcs900_state *cpustate, UINT32 a, UINT8 s )
+{
+	UINT8 count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
+
+	for ( ; count > 0; count-- )
+	{
+		cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
+		a = ( a >> 1 );
+		cpustate->cycles += 2;
+	}
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
+	parity32( cpustate, a );
+
+	return a;
+}
+
+
+INLINE UINT16 div8( tlcs900_state *cpustate, UINT16 a, UINT8 b )
+{
+	ldiv_t	result;
+
+	if ( !b )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		return ( a << 8 ) | ( ( a >> 8 ) ^ 0xff );
+	}
+
+	if ( a >= ( 0x0200 * b ) ) {
+		UINT16 diff = a - ( 0x0200 * b );
+		UINT16 range = 0x100 - b;
+
+		result = ldiv( diff, range );
+		result.quot = 0x1ff - result.quot;
+		result.rem = result.rem + b;
+	}
+	else
+	{
+		result = ldiv( a, b );
+	}
+
+	if ( result.quot > 0xff )
+		cpustate->sr.b.l |= FLAG_VF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_VF;
+
+	return ( result.quot & 0xff ) | ( ( result.rem & 0xff ) << 8 );
+}
+
+
+INLINE UINT32 div16( tlcs900_state *cpustate, UINT32 a, UINT16 b )
+{
+	ldiv_t	result;
+
+	if ( !b )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		return ( a << 16 ) | ( ( a >> 16 ) ^ 0xffff );
+	}
+
+//	if ( a >= ( 0x02000000 * b ) ) {
+//		UINT32 diff = a - ( 0x02000000 * b );
+//		UINT32 range = 0x1000000 - b;
+//
+//		result = ldiv( diff, range );
+//		result.quot = 0x1ffffff - result.quot;
+//		result.rem = result.rem + b;
+//	}
+//	else
+//	{
+		result = ldiv( a, b );
+//	}
+
+	if ( result.quot > 0xffff )
+		cpustate->sr.b.l |= FLAG_VF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_VF;
+
+	return ( result.quot & 0xffff ) | ( ( result.rem & 0xffff ) << 16 );
+}
+
+
+INLINE UINT16 divs8( tlcs900_state *cpustate, INT16 a, INT8 b )
+{
+	ldiv_t	result;
+
+	if ( !b )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		return ( a << 8 ) | ( ( a >> 8 ) ^ 0xff );
+	}
+
+	result = ldiv( a, b );
+
+	if ( result.quot > 0xff )
+		cpustate->sr.b.l |= FLAG_VF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_VF;
+
+	return ( result.quot & 0xff ) | ( ( result.rem & 0xff ) << 8 );
+}
+
+
+INLINE UINT32 divs16( tlcs900_state *cpustate, INT32 a, INT16 b )
+{
+	ldiv_t	result;
+
+	if ( !b )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		return ( a << 16 ) | ( ( a >> 16 ) ^ 0xffff );
+	}
+
+	result = ldiv( a, b );
+
+	if ( result.quot > 0xffff )
+		cpustate->sr.b.l |= FLAG_VF;
+	else
+		cpustate->sr.b.l &= ~ FLAG_VF;
+
+	return ( result.quot & 0xffff ) | ( ( result.rem & 0xffff ) << 16 );
+}
+
+
+static void _ADCBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, adc8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _ADCBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, adc8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _ADCBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = adc8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _ADCBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = adc8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ADCBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = adc8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ADCWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, adc16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _ADCWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, adc16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _ADCWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = adc16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _ADCWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = adc16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _ADCWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = adc16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _ADCLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, adc32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _ADCLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = adc32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _ADCLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = adc32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _ADCLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = adc32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _ADDBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, add8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _ADDBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, add8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _ADDBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = add8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _ADDBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = add8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ADDBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = add8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ADDWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, add16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _ADDWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, add16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _ADDWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = add16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _ADDWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = add16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _ADDWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = add16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _ADDLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, add32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _ADDLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = add32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _ADDLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = add32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _ADDLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = add32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _ANDBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, and8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _ANDBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, and8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _ANDBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = and8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _ANDBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = and8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ANDBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = and8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ANDWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, and16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _ANDWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, and16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _ANDWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = and16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _ANDWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = and16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _ANDWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = and16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _ANDLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, and32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _ANDLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = and32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _ANDLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = and32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _ANDLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = and32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _ANDCFBIM(tlcs900_state *cpustate)
+{
+	andcf8( cpustate, cpustate->imm1.b.l, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ANDCFBIR(tlcs900_state *cpustate)
+{
+	andcf8( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg8 );
+}
+
+
+static void _ANDCFBRM(tlcs900_state *cpustate)
+{
+	andcf8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ANDCFBRR(tlcs900_state *cpustate)
+{
+	andcf8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ANDCFWIR(tlcs900_state *cpustate)
+{
+	andcf16( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg16 );
+}
+
+
+static void _ANDCFWRR(tlcs900_state *cpustate)
+{
+	andcf16( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg16 );
+}
+
+
+static void _BITBIM(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	if ( RDMEM( cpustate->ea2.d ) & ( 1 << ( cpustate->imm1.b.l & 0x07 ) ) )
+		cpustate->sr.b.l |= FLAG_HF;
+	else
+		cpustate->sr.b.l |= FLAG_HF | FLAG_ZF;
+}
+
+
+static void _BITBIR(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	if ( *cpustate->p2_reg8 & ( 1 << ( cpustate->imm1.b.l & 0x07 ) ) )
+		cpustate->sr.b.l |= FLAG_HF;
+	else
+		cpustate->sr.b.l |= FLAG_HF | FLAG_ZF;
+}
+
+
+static void _BITWIR(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	if ( *cpustate->p2_reg16 & ( 1 << ( cpustate->imm1.b.l & 0x0f ) ) )
+		cpustate->sr.b.l |= FLAG_HF;
+	else
+		cpustate->sr.b.l |= FLAG_HF | FLAG_ZF;
+}
+
+
+static void _BS1BRR(tlcs900_state *cpustate)
+{
+	UINT16	r = *cpustate->p2_reg16;
+
+	if ( r )
+	{
+		cpustate->sr.b.l &= ~ FLAG_VF;
+		*cpustate->p1_reg8 = 15;
+		while( r < 0x8000 )
+		{
+			r <<= 1;
+			*cpustate->p1_reg8 -= 1;
+		}
+	}
+	else
+		cpustate->sr.b.l |= FLAG_VF;
+}
+
+
+static void _BS1FRR(tlcs900_state *cpustate)
+{
+	UINT16	r = *cpustate->p2_reg16;
+
+	if ( r )
+	{
+		cpustate->sr.b.l &= ~ FLAG_VF;
+		*cpustate->p1_reg8 = 0;
+		while( ! ( r & 0x0001 ) )
+		{
+			r >>= 1;
+			*cpustate->p1_reg8 += 1;
+		}
+	}
+	else
+		cpustate->sr.b.l |= FLAG_VF;
+}
+
+
+static void _CALLI(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 4;
+	WRMEML( cpustate->xssp.d, cpustate->pc.d );
+	cpustate->pc.d = cpustate->imm1.d;
+}
+
+
+static void _CALLM(tlcs900_state *cpustate)
+{
+	if ( condition_true( cpustate, cpustate->op ) )
+	{
+		cpustate->xssp.d -= 4;
+		WRMEML( cpustate->xssp.d, cpustate->pc.d );
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 6;
+	}
+}
+
+
+static void _CALR(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 4;
+	WRMEML( cpustate->xssp.d, cpustate->pc.d );
+	cpustate->pc.d = cpustate->ea1.d;
+}
+
+
+static void _CCF(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ FLAG_NF;
+	cpustate->sr.b.l ^= FLAG_CF;
+}
+
+
+static void _CHGBIM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) ^ ( 1 << ( cpustate->imm1.b.l & 0x07 ) ) );
+}
+
+
+static void _CHGBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 ^= ( 1 << ( cpustate->imm1.b.l & 0x07 ) );
+}
+
+
+static void _CHGWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 ^= ( 1 << ( cpustate->imm1.b.l & 0x0f ) );
+}
+
+
+static void _CPBMI(tlcs900_state *cpustate)
+{
+	sub8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l );
+}
+
+
+static void _CPBMR(tlcs900_state *cpustate)
+{
+	sub8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 );
+}
+
+
+static void _CPBRI(tlcs900_state *cpustate)
+{
+	sub8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _CPBRM(tlcs900_state *cpustate)
+{
+	sub8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _CPBRR(tlcs900_state *cpustate)
+{
+	sub8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _CPWMI(tlcs900_state *cpustate)
+{
+	sub16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l );
+}
+
+
+static void _CPWMR(tlcs900_state *cpustate)
+{
+	sub16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 );
+}
+
+
+static void _CPWRI(tlcs900_state *cpustate)
+{
+	sub16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _CPWRM(tlcs900_state *cpustate)
+{
+	sub16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _CPWRR(tlcs900_state *cpustate)
+{
+	sub16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _CPLMR(tlcs900_state *cpustate)
+{
+	sub32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 );
+}
+
+
+static void _CPLRI(tlcs900_state *cpustate)
+{
+	sub32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _CPLRM(tlcs900_state *cpustate)
+{
+	sub32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _CPLRR(tlcs900_state *cpustate)
+{
+	sub32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _CPD(tlcs900_state *cpustate)
+{
+	UINT8	result = *get_reg8_current( cpustate, 1 ) - RDMEM( *cpustate->p1_reg32 );
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	*cpustate->p1_reg32 -= 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
+		( *bc ? FLAG_VF : 0 );
+}
+
+
+static void _CPDR(tlcs900_state *cpustate)
+{
+	_CPD( cpustate );
+
+	if ( ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
+	{
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _CPDW(tlcs900_state *cpustate)
+{
+	UINT16	result = *get_reg16_current( cpustate, 0 ) - RDMEMW( *cpustate->p1_reg32 );
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	*cpustate->p1_reg32 -= 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
+		( *bc ? FLAG_VF : 0 );
+}
+
+
+static void _CPDRW(tlcs900_state *cpustate)
+{
+	_CPDW( cpustate );
+
+	if ( ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
+	{
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _CPI(tlcs900_state *cpustate)
+{
+	UINT8	result = *get_reg8_current( cpustate, 1 ) - RDMEM( *cpustate->p1_reg32 );
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	*cpustate->p1_reg32 += 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
+	cpustate->sr.b.l |= ( result & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
+		( *bc ? FLAG_VF : 0 );
+}
+
+
+static void _CPIR(tlcs900_state *cpustate)
+{
+	_CPI( cpustate );
+
+	if ( ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
+	{
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _CPIW(tlcs900_state *cpustate)
+{
+	UINT16	result = *get_reg16_current( cpustate, 0 ) - RDMEMW( *cpustate->p1_reg32 );
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	*cpustate->p1_reg32 += 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
+	cpustate->sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
+		( *bc ? FLAG_VF : 0 );
+}
+
+
+static void _CPIRW(tlcs900_state *cpustate)
+{
+	_CPIW( cpustate );
+
+	if ( ( cpustate->sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
+	{
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _CPLBR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = ~ *cpustate->p1_reg8;
+	cpustate->sr.b.l |= FLAG_HF | FLAG_NF;
+}
+
+
+static void _CPLWR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = ~ *cpustate->p1_reg16;
+	cpustate->sr.b.l |= FLAG_HF | FLAG_NF;
+}
+
+
+static void _DAABR(tlcs900_state *cpustate)
+{
+	UINT8	oldval = *cpustate->p1_reg8;
+	UINT8	fixval = 0;
+	UINT8	carry = 0;
+	UINT8	high = *cpustate->p1_reg8 & 0xf0;
+	UINT8	low = *cpustate->p1_reg8 & 0x0f;
+
+	if ( cpustate->sr.b.l & FLAG_CF )
+	{
+		if ( cpustate->sr.b.l & FLAG_HF )
+		{
+			fixval = 0x66;
+		}
+		else
+		{
+			if ( low < 0x0a )
+				fixval = 0x60;
+			else
+				fixval = 0x66;
+		}
+		carry = 1;
+	}
+	else
+	{
+		if ( cpustate->sr.b.l & FLAG_HF )
+		{
+			if ( *cpustate->p1_reg8 < 0x9a )
+				fixval = 0x06;
+			else
+				fixval = 0x66;
+		}
+		else
+		{
+			if ( high < 0x90 && low > 0x09 )
+				fixval = 0x06;
+			else if ( high > 0x80 && low > 0x09 )
+				fixval = 0x66;
+			else if ( high > 0x90 && low < 0x0a )
+				fixval = 0x60;
+		}
+	}
+	cpustate->sr.b.l &= ~ ( FLAG_VF | FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_CF );
+	if ( cpustate->sr.b.l & FLAG_NF )
+	{
+		/* after SUB, SBC, or NEG operation */
+		*cpustate->p1_reg8 -= fixval;
+		cpustate->sr.b.l |= ( ( *cpustate->p1_reg8 > oldval || carry ) ? FLAG_CF : 0 );
+	}
+	else
+	{
+		/* after ADD or ADC operation */
+		*cpustate->p1_reg8 += fixval;
+		cpustate->sr.b.l |= ( ( *cpustate->p1_reg8 < oldval || carry ) ? FLAG_CF : 0 );
+	}
+	cpustate->sr.b.l |= ( *cpustate->p1_reg8 & FLAG_SF ) | ( *cpustate->p1_reg8 ? 0 : FLAG_ZF ) |
+		( ( ( oldval ^ fixval ) ^ *cpustate->p1_reg8 ) & FLAG_HF );
+
+	parity8( cpustate, *cpustate->p1_reg8 );
+}
+
+
+static void _DB(tlcs900_state *cpustate)
+{
+}
+
+
+static void _DECBIM(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	WRMEM( cpustate->ea2.d, sub8( cpustate, RDMEM( cpustate->ea2.d ), cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 ) );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _DECBIR(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	*cpustate->p2_reg8 = sub8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _DECWIM(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	WRMEMW( cpustate->ea2.d, sub16( cpustate, RDMEMW( cpustate->ea2.d ), cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 ) );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _DECWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 -= cpustate->imm1.b.l ? cpustate->imm1.b.l : 8;
+}
+
+
+static void _DECLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 -= cpustate->imm1.b.l ? cpustate->imm1.b.l : 8;
+}
+
+
+static void _DECF(tlcs900_state *cpustate)
+{
+	/* 0x03 for MAX mode, 0x07 for MIN mode */
+	cpustate->sr.b.h = ( cpustate->sr.b.h & 0xf8 ) | ( ( cpustate->sr.b.h - 1 ) & 0x07 );
+	cpustate->regbank = cpustate->sr.b.h & 0x03;
+}
+
+
+static void _DIVBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = div8( cpustate, *cpustate->p1_reg16, cpustate->imm2.b.l );
+}
+
+
+static void _DIVBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = div8( cpustate, *cpustate->p1_reg16, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _DIVBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = div8( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg8 );
+}
+
+
+static void _DIVWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = div16( cpustate, *cpustate->p1_reg32, cpustate->imm2.w.l );
+}
+
+
+static void _DIVWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = div16( cpustate, *cpustate->p1_reg32, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _DIVWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = div16( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg16 );
+}
+
+
+static void _DIVSBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = divs8( cpustate, *cpustate->p1_reg16, cpustate->imm2.b.l );
+}
+
+
+static void _DIVSBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = divs8( cpustate, *cpustate->p1_reg16, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _DIVSBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = divs8( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg8 );
+}
+
+
+static void _DIVSWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = divs16( cpustate, *cpustate->p1_reg32, cpustate->imm2.w.l );
+}
+
+
+static void _DIVSWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = divs16( cpustate, *cpustate->p1_reg32, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _DIVSWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = divs16( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg16 );
+}
+
+
+static void _DJNZB(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 -= 1;
+	if ( *cpustate->p1_reg8 )
+	{
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _DJNZW(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 -= 1;
+	if ( *cpustate->p1_reg16 )
+	{
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _EI(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.h = ( cpustate->sr.b.h & 0x8f ) | ( ( cpustate->imm1.b.l & 0x07 ) << 4 );
+	cpustate->check_irqs = 1;
+}
+
+
+static void _EXBMR(tlcs900_state *cpustate)
+{
+	UINT8	i = RDMEM( cpustate->ea1.d );
+
+	WRMEM( cpustate->ea1.d, *cpustate->p1_reg8 );
+	*cpustate->p1_reg8 = i;
+}
+
+
+static void _EXBRR(tlcs900_state *cpustate)
+{
+	UINT8	i = *cpustate->p2_reg8;
+
+	*cpustate->p2_reg8 = *cpustate->p1_reg8;
+	*cpustate->p1_reg8 = i;
+}
+
+
+static void _EXWMR(tlcs900_state *cpustate)
+{
+	UINT16	i = RDMEMW( cpustate->ea1.d );
+
+	WRMEMW( cpustate->ea1.d, *cpustate->p1_reg16 );
+	*cpustate->p1_reg16 = i;
+}
+
+
+static void _EXWRR(tlcs900_state *cpustate)
+{
+	UINT16	i = *cpustate->p2_reg16;
+
+	*cpustate->p2_reg16 = *cpustate->p1_reg16;
+	*cpustate->p1_reg16 = i;
+}
+
+
+static void _EXTSWR(tlcs900_state *cpustate)
+{
+	if ( *cpustate->p1_reg16 & 0x0080 )
+		*cpustate->p1_reg16 |= 0xff00;
+	else
+		*cpustate->p1_reg16 &= 0x00ff;
+}
+
+
+static void _EXTSLR(tlcs900_state *cpustate)
+{
+	if ( *cpustate->p1_reg32 & 0x00008000 )
+		*cpustate->p1_reg32 |= 0xffff0000;
+	else
+		*cpustate->p1_reg32 &= 0x0000ffff;
+}
+
+
+static void _EXTZWR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 &= 0x00ff;
+}
+
+
+static void _EXTZLR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 &= 0x0000ffff;
+}
+
+
+static void _HALT(tlcs900_state *cpustate)
+{
+	cpustate->halted = 1;
+}
+
+
+static void _INCBIM(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	WRMEM( cpustate->ea2.d, add8( cpustate, RDMEM( cpustate->ea2.d ), cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 ) );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _INCBIR(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	*cpustate->p2_reg8 = add8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _INCWIM(tlcs900_state *cpustate)
+{
+	UINT8	cy = cpustate->sr.b.l & FLAG_CF;
+
+	WRMEMW( cpustate->ea2.d, add16( cpustate, RDMEMW( cpustate->ea2.d ), cpustate->imm1.b.l ? cpustate->imm1.b.l : 8 ) );
+	cpustate->sr.b.l = ( cpustate->sr.b.l & ~ FLAG_CF ) | cy;
+}
+
+
+static void _INCWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 += cpustate->imm1.b.l ? cpustate->imm1.b.l : 8;
+}
+
+
+static void _INCLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 += cpustate->imm1.b.l ? cpustate->imm1.b.l : 8;
+}
+
+
+static void _INCF(tlcs900_state *cpustate)
+{
+	/* 0x03 for MAX mode, 0x07 for MIN mode */
+	cpustate->sr.b.h = ( cpustate->sr.b.h & 0xf8 ) | ( ( cpustate->sr.b.h + 1 ) & 0x07 );
+	cpustate->regbank = cpustate->sr.b.h & 0x03;
+}
+
+
+static void _JPI(tlcs900_state *cpustate)
+{
+	cpustate->pc.d = cpustate->imm1.d;
+}
+
+
+static void _JPM(tlcs900_state *cpustate)
+{
+	if ( condition_true( cpustate, cpustate->op ) )
+	{
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _JR(tlcs900_state *cpustate)
+{
+	if ( condition_true( cpustate, cpustate->op ) )
+	{
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _JRL(tlcs900_state *cpustate)
+{
+	if ( condition_true( cpustate, cpustate->op ) )
+	{
+		cpustate->pc.d = cpustate->ea2.d;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _LDBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, cpustate->imm2.b.l );
+}
+
+
+static void _LDBMM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _LDBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, *cpustate->p2_reg8 );
+}
+
+
+static void _LDBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = cpustate->imm2.b.l;
+}
+
+
+static void _LDBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = RDMEM( cpustate->ea2.d );
+}
+
+
+static void _LDBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = *cpustate->p2_reg8;
+}
+
+
+static void _LDWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, cpustate->imm2.w.l );
+}
+
+
+static void _LDWMM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _LDWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, *cpustate->p2_reg16 );
+}
+
+
+static void _LDWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = cpustate->imm2.w.l;
+}
+
+
+static void _LDWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = RDMEMW( cpustate->ea2.d );
+}
+
+
+static void _LDWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = *cpustate->p2_reg16;
+}
+
+
+static void _LDLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = cpustate->imm2.d;
+}
+
+
+static void _LDLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = RDMEML( cpustate->ea2.d );
+}
+
+
+static void _LDLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = *cpustate->p2_reg32;
+}
+
+
+static void _LDLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, *cpustate->p2_reg32 );
+}
+
+
+static void _LDAW(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = cpustate->ea2.w.l;
+}
+
+
+static void _LDAL(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = cpustate->ea2.d;
+}
+
+
+static void _LDCBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = *cpustate->p2_reg8;
+}
+
+
+static void _LDCWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = *cpustate->p2_reg16;
+}
+
+
+static void _LDCLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = *cpustate->p2_reg32;
+}
+
+
+static void _LDCFBIM(tlcs900_state *cpustate)
+{
+	ldcf8( cpustate, cpustate->imm1.b.l, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _LDCFBIR(tlcs900_state *cpustate)
+{
+	ldcf8( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg8 );
+}
+
+
+static void _LDCFBRM(tlcs900_state *cpustate)
+{
+	ldcf8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _LDCFBRR(tlcs900_state *cpustate)
+{
+	ldcf8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _LDCFWIR(tlcs900_state *cpustate)
+{
+	ldcf16( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg16 );
+}
+
+
+static void _LDCFWRR(tlcs900_state *cpustate)
+{
+	ldcf16( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg16 );
+}
+
+
+static void _LDD(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEM( *cpustate->p1_reg32, RDMEM( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 -= 1;
+	*cpustate->p2_reg32 -= 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+	}
+}
+
+
+static void _LDDR(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEM( *cpustate->p1_reg32, RDMEM( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 -= 1;
+	*cpustate->p2_reg32 -= 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _LDDRW(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEMW( *cpustate->p1_reg32, RDMEMW( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 -= 2;
+	*cpustate->p2_reg32 -= 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _LDDW(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEMW( *cpustate->p1_reg32, RDMEMW( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 -= 2;
+	*cpustate->p2_reg32 -= 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+	}
+}
+
+
+static void _LDF(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.h = ( cpustate->sr.b.h & 0xf8 ) | ( cpustate->imm1.b.l & 0x07 );
+	cpustate->regbank = cpustate->imm1.b.l & 0x03;
+}
+
+
+static void _LDI(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEM( *cpustate->p1_reg32, RDMEM( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 += 1;
+	*cpustate->p2_reg32 += 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+	}
+}
+
+
+static void _LDIR(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEM( *cpustate->p1_reg32, RDMEM( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 += 1;
+	*cpustate->p2_reg32 += 1;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _LDIRW(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEMW( *cpustate->p1_reg32, RDMEMW( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 += 2;
+	*cpustate->p2_reg32 += 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+		cpustate->pc.d -= 2;
+		cpustate->cycles += 4;
+	}
+}
+
+
+static void _LDIW(tlcs900_state *cpustate)
+{
+	UINT16	*bc = get_reg16_current( cpustate, 1 );
+
+	WRMEMW( *cpustate->p1_reg32, RDMEMW( *cpustate->p2_reg32 ) );
+	*cpustate->p1_reg32 += 2;
+	*cpustate->p2_reg32 += 2;
+	*bc -= 1;
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
+	if ( *bc )
+	{
+		cpustate->sr.b.l |= FLAG_VF;
+	}
+}
+
+
+static void _LDX(tlcs900_state *cpustate)
+{
+	UINT8	a, b;
+
+	RDOP();
+	a = RDOP();
+	RDOP();
+	b = RDOP();
+	RDOP();
+	WRMEM( a, b );
+}
+
+
+static void _LINK(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 4;
+	WRMEML( cpustate->xssp.d, *cpustate->p1_reg32 );
+	*cpustate->p1_reg32 = cpustate->xssp.d;
+	cpustate->xssp.d += cpustate->imm2.sw.l;
+}
+
+
+static void _MAX(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.h |= 0x04;
+}
+
+
+static void _MDEC1(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 += cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 -= 1;
+}
+
+
+static void _MDEC2(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 += cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 -= 2;
+}
+
+
+static void _MDEC4(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 += cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 -= 4;
+}
+
+
+static void _MINC1(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 -= cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 += 1;
+}
+
+
+static void _MINC2(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 -= cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 += 2;
+}
+
+
+static void _MINC4(tlcs900_state *cpustate)
+{
+	if ( ( *cpustate->p2_reg16 & cpustate->imm1.w.l ) == cpustate->imm1.w.l )
+		*cpustate->p2_reg16 -= cpustate->imm1.w.l;
+	else
+		*cpustate->p2_reg16 += 4;
+}
+
+
+static void _MIRRW(tlcs900_state *cpustate)
+{
+	UINT16	r = *cpustate->p1_reg16;
+	UINT16	s = ( r & 0x01 );
+	int i;
+
+
+	for ( i = 0; i < 15; i++ )
+	{
+		r >>= 1;
+		s <<= 1;
+		s |= ( r & 0x01 );
+	}
+
+	*cpustate->p1_reg16 = s;
+}
+
+
+static void _MULBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = ( *cpustate->p1_reg16 & 0xff ) * cpustate->imm2.b.l;
+}
+
+
+static void _MULBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = ( *cpustate->p1_reg16 & 0xff ) * RDMEM( cpustate->ea2.d );
+}
+
+
+static void _MULBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = ( *cpustate->p1_reg16 & 0xff ) * *cpustate->p2_reg8;
+}
+
+
+static void _MULWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = ( *cpustate->p1_reg32 & 0xffff ) * cpustate->imm2.w.l;
+}
+
+
+static void _MULWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = ( *cpustate->p1_reg32 & 0xffff ) * RDMEMW( cpustate->ea2.d );
+}
+
+
+static void _MULWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = ( *cpustate->p1_reg32 & 0xffff ) * *cpustate->p2_reg16;
+}
+
+
+static void _MULAR(tlcs900_state *cpustate)
+{
+	UINT32	*xde = get_reg32_current( cpustate, 2 );
+	UINT32	*xhl = get_reg32_current( cpustate, 3 );
+
+	*cpustate->p1_reg32 = *cpustate->p1_reg32 + ( ((INT16)RDMEMW( *xde )) * ((INT16)RDMEMW( *xhl )) );
+	*xhl -= 2;
+
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_VF );
+	cpustate->sr.b.l |= ( ( *cpustate->p1_reg32 >> 24 ) & FLAG_SF ) | ( *cpustate->p1_reg32 ? 0 : FLAG_ZF );
+}
+
+
+static void _MULSBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = (INT8)( *cpustate->p1_reg16 & 0xff ) * cpustate->imm2.sb.l;
+}
+
+
+static void _MULSBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = (INT8)( *cpustate->p1_reg16 & 0xff ) * (INT8)RDMEM( cpustate->ea2.d );
+}
+
+
+static void _MULSBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = (INT8)( *cpustate->p1_reg16 & 0xff ) * (INT8)*cpustate->p2_reg8;
+}
+
+
+static void _MULSWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = (INT16)( *cpustate->p1_reg32 & 0xffff ) * cpustate->imm2.sw.l;
+}
+
+
+static void _MULSWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = (INT16)( *cpustate->p1_reg32 & 0xffff ) * (INT16)RDMEMW( cpustate->ea2.d );
+}
+
+
+static void _MULSWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = (INT16)( *cpustate->p1_reg32 & 0xffff ) * (INT16)*cpustate->p2_reg16;
+}
+
+
+static void _NEGBR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sub8( cpustate, 0, *cpustate->p1_reg8 );
+}
+
+
+static void _NEGWR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sub16( cpustate, 0, *cpustate->p1_reg16 );
+}
+
+
+static void _NOP(tlcs900_state *cpustate)
+{
+	/* Do nothing */
+}
+
+
+static void _NORMAL(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.h &= 0x7F;
+}
+
+
+static void _ORBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, or8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _ORBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, or8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _ORBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = or8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _ORBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = or8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ORBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = or8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ORWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, or16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _ORWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, or16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _ORWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = or16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _ORWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = or16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _ORWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = or16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _ORLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, or32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _ORLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = or32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _ORLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = or32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _ORLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = or32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _ORCFBIM(tlcs900_state *cpustate)
+{
+	orcf8( cpustate, cpustate->imm1.b.l, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ORCFBIR(tlcs900_state *cpustate)
+{
+	orcf8( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg8 );
+}
+
+
+static void _ORCFBRM(tlcs900_state *cpustate)
+{
+	orcf8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _ORCFBRR(tlcs900_state *cpustate)
+{
+	orcf8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _ORCFWIR(tlcs900_state *cpustate)
+{
+	orcf16( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg16 );
+}
+
+
+static void _ORCFWRR(tlcs900_state *cpustate)
+{
+	orcf16( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg16 );
+}
+
+
+static void _PAAWR(tlcs900_state *cpustate)
+{
+	if ( *cpustate->p1_reg16 & 1 )
+		*cpustate->p1_reg16 += 1;
+}
+
+
+static void _PAALR(tlcs900_state *cpustate)
+{
+	if ( *cpustate->p1_reg32 & 1 )
+		*cpustate->p1_reg32 += 1;
+}
+
+
+static void _POPBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, RDMEM( cpustate->xssp.d ) );
+	cpustate->xssp.d += 1;
+}
+
+
+static void _POPBR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = RDMEM( cpustate->xssp.d );
+	cpustate->xssp.d += 1;
+}
+
+
+static void _POPWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, RDMEMW( cpustate->xssp.d ) );
+	cpustate->xssp.d += 2;
+}
+
+
+static void _POPWR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = RDMEMW( cpustate->xssp.d );
+	cpustate->xssp.d += 2;
+}
+
+
+static void _POPWSR(tlcs900_state *cpustate)
+{
+	_POPWR( cpustate );
+	cpustate->regbank = cpustate->sr.b.h & 0x07;
+	cpustate->check_irqs = 1;
+}
+
+
+static void _POPLR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = RDMEML( cpustate->xssp.d );
+	cpustate->xssp.d += 4;
+}
+
+
+static void _PUSHBI(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 1;
+	WRMEM( cpustate->xssp.d, cpustate->imm1.b.l );
+}
+
+
+static void _PUSHBM(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 1;
+	WRMEM( cpustate->xssp.d, RDMEM( cpustate->ea1.d ) );
+}
+
+
+static void _PUSHBR(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 1;
+	WRMEM( cpustate->xssp.d, *cpustate->p1_reg8 );
+}
+
+
+static void _PUSHWI(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 2;
+	WRMEMW( cpustate->xssp.d, cpustate->imm1.w.l );
+}
+
+
+static void _PUSHWM(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 2;
+	WRMEMW( cpustate->xssp.d, RDMEMW( cpustate->ea1.d ) );
+}
+
+
+static void _PUSHWR(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 2;
+	WRMEMW( cpustate->xssp.d, *cpustate->p1_reg16 );
+}
+
+
+static void _PUSHLR(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 4;
+	WRMEML( cpustate->xssp.d, *cpustate->p1_reg32 );
+}
+
+
+static void _RCF(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_NF | FLAG_CF );
+}
+
+
+static void _RESBIM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) & ~( 1 << ( cpustate->imm1.d & 0x07 ) ) );
+}
+
+
+static void _RESBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = *cpustate->p2_reg8 & ~( 1 << ( cpustate->imm1.d & 0x07 ) );
+}
+
+
+static void _RESWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = *cpustate->p2_reg16 & ~( 1 << ( cpustate->imm1.d & 0x0f ) );
+}
+
+
+static void _RET(tlcs900_state *cpustate)
+{
+	cpustate->pc.d = RDMEML( cpustate->xssp.d );
+	cpustate->xssp.d += 4;
+}
+
+
+static void _RETCC(tlcs900_state *cpustate)
+{
+	if ( condition_true( cpustate, cpustate->op ) )
+	{
+		cpustate->pc.d = RDMEML( cpustate->xssp.d );
+		cpustate->xssp.d += 4;
+		cpustate->cycles += 6;
+	}
+}
+
+
+static void _RETD(tlcs900_state *cpustate)
+{
+	cpustate->pc.d = RDMEML( cpustate->xssp.d );
+	cpustate->xssp.d += 4 + cpustate->imm1.sw.l;
+}
+
+
+static void _RETI(tlcs900_state *cpustate)
+{
+	cpustate->sr.w.l = RDMEMW( cpustate->xssp.d );
+	cpustate->xssp.d += 2;
+	cpustate->pc.d = RDMEML( cpustate->xssp.d );
+	cpustate->xssp.d += 4;
+	cpustate->regbank = cpustate->sr.b.h & 0x03;
+	cpustate->check_irqs = 1;
+}
+
+
+static void _RLBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, rl8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RLWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, rl16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RLBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rl8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _RLBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rl8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _RLWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rl16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _RLWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rl16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _RLLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rl32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _RLLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rl32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _RLCBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, rlc8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RLCWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, rlc16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RLCBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rlc8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _RLCBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rlc8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _RLCWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rlc16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _RLCWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rlc16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _RLCLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rlc32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _RLCLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rlc32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _RLDRM(tlcs900_state *cpustate)
+{
+	UINT8	a = *cpustate->p1_reg8 & 0x0f;
+	UINT8	b = RDMEM( cpustate->ea2.d );
+
+	*cpustate->p1_reg8 = ( *cpustate->p1_reg8 & 0xf0 ) | ( ( b & 0xf0 ) >> 4 );
+	WRMEM( cpustate->ea2.d, ( ( b & 0x0f ) << 4 ) | a );
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( *cpustate->p1_reg8 & FLAG_SF ) | ( *cpustate->p1_reg8 ? 0 : FLAG_ZF );
+	parity8( cpustate, *cpustate->p1_reg8 );
+}
+
+
+static void _RRBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, rr8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RRWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, rr16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RRBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rr8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _RRBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rr8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _RRWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rr16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _RRWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rr16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _RRLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rr32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _RRLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rr32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _RRCBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, rrc8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RRCWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, rrc16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _RRCBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rrc8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _RRCBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = rrc8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _RRCWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rrc16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _RRCWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = rrc16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _RRCLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rrc32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _RRCLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = rrc32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _RRDRM(tlcs900_state *cpustate)
+{
+	UINT8	a = *cpustate->p1_reg8 & 0x0f;
+	UINT8	b = RDMEM( cpustate->ea2.d );
+
+	*cpustate->p1_reg8 = ( *cpustate->p1_reg8 & 0xf0 ) | ( b & 0x0f );
+	WRMEM( cpustate->ea2.d, ( ( b & 0xf0 ) >> 4 ) | ( a << 4 ) );
+	cpustate->sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( *cpustate->p1_reg8 & FLAG_SF ) | ( *cpustate->p1_reg8 ? 0 : FLAG_ZF );
+	parity8( cpustate, *cpustate->p1_reg8 );
+}
+
+
+static void _SBCBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, sbc8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _SBCBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, sbc8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _SBCBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sbc8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _SBCBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sbc8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _SBCBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sbc8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _SBCWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, sbc16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _SBCWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, sbc16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _SBCWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sbc16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _SBCWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sbc16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _SBCWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sbc16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _SBCLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, sbc32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _SBCLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sbc32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _SBCLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sbc32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _SBCLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sbc32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _SCCBR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = condition_true( cpustate, cpustate->op ) ? 1 : 0;
+}
+
+
+static void _SCCWR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = condition_true( cpustate, cpustate->op ) ? 1 : 0;
+}
+
+
+static void _SCF(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_HF | FLAG_NF );
+	cpustate->sr.b.l |= FLAG_CF;
+}
+
+
+static void _SETBIM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) | ( 1 << ( cpustate->imm1.d & 0x07 ) ) );
+}
+
+
+static void _SETBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = *cpustate->p2_reg8 | ( 1 << ( cpustate->imm1.d & 0x07 ) );
+}
+
+
+static void _SETWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = *cpustate->p2_reg16 | ( 1 << ( cpustate->imm1.d & 0x0f ) );
+}
+
+
+static void _SLABM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, sla8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SLAWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, sla16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SLABIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sla8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _SLABRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sla8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _SLAWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sla16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _SLAWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sla16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _SLALIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sla32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _SLALRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sla32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _SLLBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, sla8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SLLWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, sla16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SLLBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sla8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _SLLBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sla8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _SLLWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sla16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _SLLWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sla16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _SLLLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sla32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _SLLLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sla32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _SRABM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, sra8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SRAWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, sra16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SRABIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sra8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _SRABRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = sra8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _SRAWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sra16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _SRAWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = sra16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _SRALIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sra32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _SRALRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = sra32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _SRLBM(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea2.d, srl8( cpustate, RDMEM( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SRLWM(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea2.d, srl16( cpustate, RDMEMW( cpustate->ea2.d ), 1 ) );
+}
+
+
+static void _SRLBIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = srl8( cpustate, *cpustate->p2_reg8, cpustate->imm1.b.l );
+}
+
+
+static void _SRLBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg8 = srl8( cpustate, *cpustate->p2_reg8, *cpustate->p1_reg8 );
+}
+
+
+static void _SRLWIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = srl16( cpustate, *cpustate->p2_reg16, cpustate->imm1.b.l );
+}
+
+
+static void _SRLWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg16 = srl16( cpustate, *cpustate->p2_reg16, *cpustate->p1_reg8 );
+}
+
+
+static void _SRLLIR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = srl32( cpustate, *cpustate->p2_reg32, cpustate->imm1.b.l );
+}
+
+
+static void _SRLLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p2_reg32 = srl32( cpustate, *cpustate->p2_reg32, *cpustate->p1_reg8 );
+}
+
+
+static void _STCFBIM(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) | ( 1 << ( cpustate->imm1.b.l & 0x07 ) ) );
+	else
+		WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) & ~ ( 1 << ( cpustate->imm1.b.l & 0x07 ) ) );
+}
+
+
+static void _STCFBIR(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		*cpustate->p2_reg8 |= ( 1 << ( cpustate->imm1.b.l & 0x07 ) );
+	else
+		*cpustate->p2_reg8 &= ~ ( 1 << ( cpustate->imm1.b.l & 0x07 ) );
+}
+
+
+static void _STCFBRM(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) | ( 1 << ( *cpustate->p1_reg8 & 0x07 ) ) );
+	else
+		WRMEM( cpustate->ea2.d, RDMEM( cpustate->ea2.d ) & ~ ( 1 << ( *cpustate->p1_reg8 & 0x07 ) ) );
+}
+
+
+static void _STCFBRR(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		*cpustate->p2_reg8 |= ( 1 << ( *cpustate->p1_reg8 & 0x07 ) );
+	else
+		*cpustate->p2_reg8 &= ~ ( 1 << ( *cpustate->p1_reg8 & 0x07 ) );
+}
+
+
+static void _STCFWIR(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		*cpustate->p2_reg16 |= ( 1 << ( cpustate->imm1.b.l & 0x0f ) );
+	else
+		*cpustate->p2_reg16 &= ~ ( 1 << ( cpustate->imm1.b.l & 0x0f ) );
+}
+
+
+static void _STCFWRR(tlcs900_state *cpustate)
+{
+	if ( cpustate->sr.b.l & FLAG_CF )
+		*cpustate->p2_reg16 |= ( 1 << ( *cpustate->p1_reg8 & 0x0f ) );
+	else
+		*cpustate->p2_reg16 &= ~ ( 1 << ( *cpustate->p1_reg8 & 0x0f ) );
+}
+
+
+static void _SUBBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, sub8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _SUBBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, sub8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _SUBBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sub8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _SUBBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sub8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _SUBBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = sub8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _SUBWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, sub16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _SUBWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, sub16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _SUBWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sub16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _SUBWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sub16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _SUBWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = sub16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _SUBLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, sub32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _SUBLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sub32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _SUBLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sub32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _SUBLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = sub32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _SWI(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d -= 4;
+	WRMEML( cpustate->xssp.d, cpustate->pc.d );
+	cpustate->xssp.d -= 2;
+	WRMEMW( cpustate->xssp.d, cpustate->sr.w.l );
+	cpustate->pc.d = RDMEML( 0x00ffff00 + 4 * cpustate->imm1.b.l );
+}
+
+
+static void _TSETBIM(tlcs900_state *cpustate)
+{
+	UINT8	b = 1 << ( cpustate->imm1.b.l & 0x07 );
+	UINT8	a = RDMEM( cpustate->ea2.d );
+
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( a & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
+	WRMEM( cpustate->ea2.d, a | b );
+}
+
+
+static void _TSETBIR(tlcs900_state *cpustate)
+{
+	UINT8	b = 1 << ( cpustate->imm1.b.l & 0x07 );
+
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( *cpustate->p2_reg8 & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
+	*cpustate->p2_reg8 |= b;
+}
+
+
+static void _TSETWIR(tlcs900_state *cpustate)
+{
+	UINT16	b = 1 << ( cpustate->imm1.b.l & 0x0f );
+
+	cpustate->sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
+	cpustate->sr.b.l |= ( ( *cpustate->p2_reg16 & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
+	*cpustate->p2_reg16 |= b;
+}
+
+
+static void _UNLK(tlcs900_state *cpustate)
+{
+	cpustate->xssp.d = *cpustate->p1_reg32;
+	*cpustate->p1_reg32 = RDMEML( cpustate->xssp.d );
+	cpustate->xssp.d += 4;
+}
+
+
+static void _XORBMI(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, xor8( cpustate, RDMEM( cpustate->ea1.d ), cpustate->imm2.b.l ) );
+}
+
+
+static void _XORBMR(tlcs900_state *cpustate)
+{
+	WRMEM( cpustate->ea1.d, xor8( cpustate, RDMEM( cpustate->ea1.d ), *cpustate->p2_reg8 ) );
+}
+
+
+static void _XORBRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = xor8( cpustate, *cpustate->p1_reg8, cpustate->imm2.b.l );
+}
+
+
+static void _XORBRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = xor8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _XORBRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg8 = xor8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _XORWMI(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, xor16( cpustate, RDMEMW( cpustate->ea1.d ), cpustate->imm2.w.l ) );
+}
+
+
+static void _XORWMR(tlcs900_state *cpustate)
+{
+	WRMEMW( cpustate->ea1.d, xor16( cpustate, RDMEMW( cpustate->ea1.d ), *cpustate->p2_reg16 ) );
+}
+
+
+static void _XORWRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = xor16( cpustate, *cpustate->p1_reg16, cpustate->imm2.w.l );
+}
+
+
+static void _XORWRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = xor16( cpustate, *cpustate->p1_reg16, RDMEMW( cpustate->ea2.d ) );
+}
+
+
+static void _XORWRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg16 = xor16( cpustate, *cpustate->p1_reg16, *cpustate->p2_reg16 );
+}
+
+
+static void _XORLMR(tlcs900_state *cpustate)
+{
+	WRMEML( cpustate->ea1.d, xor32( cpustate, RDMEML( cpustate->ea1.d ), *cpustate->p2_reg32 ) );
+}
+
+
+static void _XORLRI(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = xor32( cpustate, *cpustate->p1_reg32, cpustate->imm2.d );
+}
+
+
+static void _XORLRM(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = xor32( cpustate, *cpustate->p1_reg32, RDMEML( cpustate->ea2.d ) );
+}
+
+
+static void _XORLRR(tlcs900_state *cpustate)
+{
+	*cpustate->p1_reg32 = xor32( cpustate, *cpustate->p1_reg32, *cpustate->p2_reg32 );
+}
+
+
+static void _XORCFBIM(tlcs900_state *cpustate)
+{
+	xorcf8( cpustate, cpustate->imm1.b.l, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _XORCFBIR(tlcs900_state *cpustate)
+{
+	xorcf8( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg8 );
+}
+
+
+static void _XORCFBRM(tlcs900_state *cpustate)
+{
+	xorcf8( cpustate, *cpustate->p1_reg8, RDMEM( cpustate->ea2.d ) );
+}
+
+
+static void _XORCFBRR(tlcs900_state *cpustate)
+{
+	xorcf8( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg8 );
+}
+
+
+static void _XORCFWIR(tlcs900_state *cpustate)
+{
+	xorcf16( cpustate, cpustate->imm1.b.l, *cpustate->p2_reg16 );
+}
+
+
+static void _XORCFWRR(tlcs900_state *cpustate)
+{
+	xorcf16( cpustate, *cpustate->p1_reg8, *cpustate->p2_reg16 );
+}
+
+
+static void _ZCF(tlcs900_state *cpustate)
+{
+	cpustate->sr.b.l &= ~ ( FLAG_NF | FLAG_CF );
+	cpustate->sr.b.l |= ( ( cpustate->sr.b.l & FLAG_ZF ) ? 0 : FLAG_CF );
+}
+
+
+typedef struct 
+{
+	void (*opfunc)(tlcs900_state *cpustate);
+	int		operand1;
+	int		operand2;
+	int		cycles;
+} tlcs900inst;
+
+
+static void prepare_operands(tlcs900_state *cpustate, const tlcs900inst *inst)
+{
+	switch ( inst->operand1 )
+	{
+	case _A:
+		cpustate->p1_reg8 = &cpustate->xwa[cpustate->regbank].b.l;
+		break;
+	case _F:
+		cpustate->p1_reg8 = &cpustate->sr.b.l;
+		break;
+	case _SR:
+		cpustate->p1_reg16 = &cpustate->sr.w.l;
+		break;
+	case _C8:
+		cpustate->p1_reg8 = get_reg8_current( cpustate, cpustate->op );
+		break;
+	case _C16:
+		cpustate->p1_reg16 = get_reg16_current( cpustate, cpustate->op );
+		break;
+	case _MC16:	/* For MUL and DIV operations */
+		cpustate->p1_reg16 = get_reg16_current( cpustate, ( cpustate->op >> 1 ) & 0x03 );
+		break;
+	case _C32:
+		cpustate->p1_reg32 = get_reg32_current( cpustate, cpustate->op );
+		break;
+	case _CR8:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x22:
+			cpustate->p1_reg8 = &cpustate->dmam[0].b.l;
+			break;
+		case 0x26:
+			cpustate->p1_reg8 = &cpustate->dmam[1].b.l;
+			break;
+		case 0x2a:
+			cpustate->p1_reg8 = &cpustate->dmam[2].b.l;
+			break;
+		case 0x2e:
+			cpustate->p1_reg8 = &cpustate->dmam[3].b.l;
+			break;
+		default:
+			cpustate->p1_reg8 = &cpustate->dummy.b.l;
+			break;
+		}
+		break;
+	case _CR16:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x20:
+			cpustate->p1_reg16 = &cpustate->dmac[0].w.l;
+			break;
+		case 0x24:
+			cpustate->p1_reg16 = &cpustate->dmac[1].w.l;
+			break;
+		case 0x28:
+			cpustate->p1_reg16 = &cpustate->dmac[2].w.l;
+			break;
+		case 0x2c:
+			cpustate->p1_reg16 = &cpustate->dmac[3].w.l;
+			break;
+		default:
+			cpustate->p1_reg16 = &cpustate->dummy.w.l;
+			break;
+		}
+		break;
+	case _CR32:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x00:
+			cpustate->p1_reg32 = &cpustate->dmas[0].d;
+			break;
+		case 0x04:
+			cpustate->p1_reg32 = &cpustate->dmas[1].d;
+			break;
+		case 0x08:
+			cpustate->p1_reg32 = &cpustate->dmas[2].d;
+			break;
+		case 0x0c:
+			cpustate->p1_reg32 = &cpustate->dmas[3].d;
+			break;
+		case 0x10:
+			cpustate->p1_reg32 = &cpustate->dmad[0].d;
+			break;
+		case 0x14:
+			cpustate->p1_reg32 = &cpustate->dmad[1].d;
+			break;
+		case 0x18:
+			cpustate->p1_reg32 = &cpustate->dmad[2].d;
+			break;
+		case 0x1c:
+			cpustate->p1_reg32 = &cpustate->dmad[3].d;
+			break;
+		default:
+			cpustate->p1_reg32 = &cpustate->dummy.d;
+			break;
+		}
+		break;
+	case _D8:
+		cpustate->ea1.d = RDOP();
+		cpustate->ea1.d = cpustate->pc.d + cpustate->ea1.sb.l;
+		break;
+	case _D16:
+		cpustate->ea1.d = RDOP();
+		cpustate->ea1.b.h = RDOP();
+		cpustate->ea1.d = cpustate->pc.d + cpustate->ea1.sw.l;
+		break;
+	case _I3:
+		cpustate->imm1.d = cpustate->op & 0x07;
+		break;
+	case _I8:
+		cpustate->imm1.d = RDOP();
+		break;
+	case _I16:
+		cpustate->imm1.d = RDOP();
+		cpustate->imm1.b.h = RDOP();
+		break;
+	case _I24:
+		cpustate->imm1.d = RDOP();
+		cpustate->imm1.b.h = RDOP();
+		cpustate->imm1.b.h2 = RDOP();
+		break;
+	case _I32:
+		cpustate->imm1.d = RDOP();
+		cpustate->imm1.b.h = RDOP();
+		cpustate->imm1.b.h2 = RDOP();
+		cpustate->imm1.b.h3 = RDOP();
+		break;
+	case _M:
+		cpustate->ea1.d = cpustate->ea2.d;
+		break;
+	case _M8:
+		cpustate->ea1.d = RDOP();
+		break;
+	case _M16:
+		cpustate->ea1.d = RDOP();
+		cpustate->ea1.b.h = RDOP();
+		break;
+	case _R:
+		cpustate->p1_reg8 = cpustate->p2_reg8;
+		cpustate->p1_reg16 = cpustate->p2_reg16;
+		cpustate->p1_reg32 = cpustate->p2_reg32;
+		break;
+	}
+
+	switch ( inst->operand2 )
+	{
+	case _A:
+		cpustate->p2_reg8 = &cpustate->xwa[cpustate->regbank].b.l;
+		break;
+	case _F:		/* F' */
+		cpustate->p2_reg8 = &cpustate->f2.b.l;
+		break;
+	case _SR:
+		cpustate->p2_reg16 = &cpustate->sr.w.l;
+		break;
+	case _C8:
+		cpustate->p2_reg8 = get_reg8_current( cpustate, cpustate->op );
+		break;
+	case _C16:
+		cpustate->p2_reg16 = get_reg16_current( cpustate, cpustate->op );
+		break;
+	case _C32:
+		cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op );
+		break;
+	case _CR8:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x22:
+			cpustate->p2_reg8 = &cpustate->dmam[0].b.l;
+			break;
+		case 0x26:
+			cpustate->p2_reg8 = &cpustate->dmam[1].b.l;
+			break;
+		case 0x2a:
+			cpustate->p2_reg8 = &cpustate->dmam[2].b.l;
+			break;
+		case 0x2e:
+			cpustate->p2_reg8 = &cpustate->dmam[3].b.l;
+			break;
+		default:
+			cpustate->p2_reg8 = &cpustate->dummy.b.l;
+			break;
+		}
+		break;
+	case _CR16:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x20:
+			cpustate->p2_reg16 = &cpustate->dmac[0].w.l;
+			break;
+		case 0x24:
+			cpustate->p2_reg16 = &cpustate->dmac[1].w.l;
+			break;
+		case 0x28:
+			cpustate->p2_reg16 = &cpustate->dmac[2].w.l;
+			break;
+		case 0x2c:
+			cpustate->p2_reg16 = &cpustate->dmac[3].w.l;
+			break;
+		default:
+			cpustate->p2_reg16 = &cpustate->dummy.w.l;
+			break;
+		}
+		break;
+	case _CR32:
+		cpustate->imm1.d = RDOP();
+		switch( cpustate->imm1.d )
+		{
+		case 0x00:
+			cpustate->p2_reg32 = &cpustate->dmas[0].d;
+			break;
+		case 0x04:
+			cpustate->p2_reg32 = &cpustate->dmas[1].d;
+			break;
+		case 0x08:
+			cpustate->p2_reg32 = &cpustate->dmas[2].d;
+			break;
+		case 0x0c:
+			cpustate->p2_reg32 = &cpustate->dmas[3].d;
+			break;
+		case 0x10:
+			cpustate->p2_reg32 = &cpustate->dmad[0].d;
+			break;
+		case 0x14:
+			cpustate->p2_reg32 = &cpustate->dmad[1].d;
+			break;
+		case 0x18:
+			cpustate->p2_reg32 = &cpustate->dmad[2].d;
+			break;
+		case 0x1c:
+			cpustate->p2_reg32 = &cpustate->dmad[3].d;
+			break;
+		default:
+			cpustate->p2_reg32 = &cpustate->dummy.d;
+			break;
+		}
+		break;
+	case _D8:
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sb.l;
+		break;
+	case _D16:
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l;
+		break;
+	case _I3:
+		cpustate->imm2.d = cpustate->op & 0x07;
+		break;
+	case _I8:
+		cpustate->imm2.d = RDOP();
+		break;
+	case _I16:
+		cpustate->imm2.d = RDOP();
+		cpustate->imm2.b.h = RDOP();
+		break;
+	case _I32:
+		cpustate->imm2.d = RDOP();
+		cpustate->imm2.b.h = RDOP();
+		cpustate->imm2.b.h2 = RDOP();
+		cpustate->imm2.b.h3 = RDOP();
+		break;
+	case _M8:
+		cpustate->ea2.d = RDOP();
+		break;
+	case _M16:
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		break;
+	}
+}
+
+
+static const tlcs900inst mnemonic_80[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHBM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _RLDRM, _A, _M, 12 }, { _RRDRM, _A, _M, 12 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDI, 0, 0, 10 }, { _LDIR, 0, 0, 10 }, { _LDD, 0, 0, 10 }, { _LDDR, 0, 0, 10 },
+	{ _CPI, 0, 0, 8 }, { _CPIR, 0, 0, 10 }, { _CPD, 0, 0, 8 }, { _CPDR, 0, 0, 10 },
+	{ _DB, 0, 0, 1 }, { _LDBMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _ADDBMI, _M, _I8, 7 }, { _ADCBMI, _M, _I8, 7 }, { _SUBBMI, _M, _I8, 7 }, { _SBCBMI, _M, _I8, 7 },
+	{ _ANDBMI, _M, _I8, 7 }, { _XORBMI, _M, _I8, 7 }, { _ORBMI, _M, _I8, 7 }, { _CPBMI, _M, _I8, 6 },
+
+	/* 40 - 5F */
+	{ _MULBRM, _MC16, _M, 18}, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, 
+	{ _MULBRM, _MC16, _M, 18}, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+
+	/* 60 - 7F */
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCBM, _M, 0, 8 }, { _RRCBM, _M, 0, 8 }, { _RLBM, _M, 0, 8 }, { _RRBM, _M, 0, 8 },
+	{ _SLABM, _M, 0, 8 }, { _SRABM, _M, 0, 8 }, { _SLLBM, _M, 0, 8 }, { _SRLBM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+
+	/* A0 - BF */
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+
+	/* C0 - DF */
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+
+	/* E0 - FF */
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+};
+
+
+static const tlcs900inst mnemonic_88[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHBM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _RLDRM, _A, _M, 12 }, { _RRDRM, _A, _M, 12 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _LDBMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _ADDBMI, _M, _I8, 7 }, { _ADCBMI, _M, _I8, 7 }, { _SUBBMI, _M, _I8, 7 }, { _SBCBMI, _M, _I8, 7 },
+	{ _ANDBMI, _M, _I8, 7 }, { _XORBMI, _M, _I8, 7 }, { _ORBMI, _M, _I8, 7 }, { _CPBMI, _M, _I8, 6 },
+
+	/* 40 - 5F */
+	{ _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, 
+	{ _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+
+	/* 60 - 7F */
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCBM, _M, 0, 8 }, { _RRCBM, _M, 0, 8 }, { _RLBM, _M, 0, 8 }, { _RRBM, _M, 0, 8 },
+	{ _SLABM, _M, 0, 8 }, { _SRABM, _M, 0, 8 }, { _SLLBM, _M, 0, 8 }, { _SRLBM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+
+	/* A0 - BF */
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+
+	/* C0 - DF */
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+
+	/* E0 - FF */
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+};
+
+
+static const tlcs900inst mnemonic_90[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHWM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDIW, 0, 0, 10 }, { _LDIRW, 0, 0, 10 }, { _LDDW, 0, 0, 10 }, { _LDDRW, 0, 0, 10 },
+	{ _CPIW, 0, 0, 8 }, { _CPIRW, 0, 0, 10 }, { _CPDW, 0, 0, 8 }, { _CPDRW, 0, 0, 10 },
+	{ _DB, 0, 0, 1 }, { _LDWMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _ADDWMI, _M, _I16, 8 }, { _ADCWMI, _M, _I16, 8 }, { _SUBWMI, _M, _I16, 8 }, { _SBCWMI, _M, _I16, 8 },
+	{ _ANDWMI, _M, _I16, 8 }, { _XORWMI, _M, _I16, 8 }, { _ORWMI, _M, _I16, 8 }, { _CPWMI, _M, _I16, 6 },
+
+	/* 40 - 5F */
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, 
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+
+	/* 60 - 7F */
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCWM, _M, 0, 8 }, { _RRCWM, _M, 0, 8 }, { _RLWM, _M, 0, 8 }, { _RRWM, _M, 0, 8 },
+	{ _SLAWM, _M, 0, 8 }, { _SRAWM, _M, 0, 8 }, { _SLLWM, _M, 0, 8 }, { _SRLWM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+
+	/* A0 - BF */
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+
+	/* C0 - DF */
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+
+	/* E0 - FF */
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+};
+
+
+static const tlcs900inst mnemonic_98[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHWM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _LDWMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _ADDWMI, _M, _I16, 8 }, { _ADCWMI, _M, _I16, 8 }, { _SUBWMI, _M, _I16, 8 }, { _SBCWMI, _M, _I16, 8 },
+	{ _ANDWMI, _M, _I16, 8 }, { _XORWMI, _M, _I16, 8 }, { _ORWMI, _M, _I16, 8 }, { _CPWMI, _M, _I16, 6 },
+
+	/* 40 - 5F */
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, 
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+
+	/* 60 - 7F */
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCWM, _M, 0, 8 }, { _RRCWM, _M, 0, 8 }, { _RLWM, _M, 0, 8 }, { _RRWM, _M, 0, 8 },
+	{ _SLAWM, _M, 0, 8 }, { _SRAWM, _M, 0, 8 }, { _SLLWM, _M, 0, 8 }, { _SRLWM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+
+	/* A0 - BF */
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+
+	/* C0 - DF */
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+
+	/* E0 - FF */
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+};
+
+
+static const tlcs900inst mnemonic_a0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 },
+	{ _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 },
+	{ _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 },
+	{ _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 },
+	{ _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 },
+	{ _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 },
+	{ _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 },
+	{ _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 },
+	{ _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 },
+
+	/* A0 - BF */
+	{ _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 },
+	{ _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 },
+	{ _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 },
+	{ _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 },
+	{ _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 },
+	{ _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 },
+	{ _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 },
+	{ _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 },
+
+	/* C0 - DF */
+	{ _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 },
+	{ _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 },
+	{ _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 },
+	{ _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 },
+	{ _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 },
+	{ _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 },
+	{ _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 },
+	{ _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 },
+
+	/* E0 - FF */
+	{ _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 },
+	{ _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 },
+	{ _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 },
+	{ _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 },
+	{ _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 },
+	{ _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 },
+	{ _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 },
+	{ _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 },
+};
+
+
+static const tlcs900inst mnemonic_b0[256] =
+{
+	/* 00 - 1F */
+	{ _LDBMI, _M, _I8, 5 }, { _DB, 0, 0, 1 }, { _LDWMI, _M, _I16, 6 }, { _DB, 0, 0, 1 },
+	{ _POPBM, _M, 0, 6 }, { _DB, 0, 0, 1 }, { _POPWM, _M, 0, 6 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDBMM, _M, _M16, 8 }, { _DB, 0, 0, 1 }, { _LDWMM, _M, _M16, 8 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _ANDCFBRM, _A, _M, 8 }, { _ORCFBRM, _A, _M, 8 }, { _XORCFBRM, _A, _M, 8 }, { _LDCFBRM, _A, _M, 8 },
+	{ _STCFBRM, _A, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 },
+	{ _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 },
+	{ _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 },
+	{ _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 },
+	{ _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 },
+	{ _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 },
+	{ _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 },
+	{ _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 },
+
+	/* A0 - BF */
+	{ _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 },
+	{ _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+
+	/* C0 - DF */
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, 
+	{ _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+
+	/* E0 - FF */
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 },
+	{ _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 },
+	{ _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 },
+	{ _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }, { _RETCC, _CC, 0, 6 }
+};
+
+
+static const tlcs900inst mnemonic_b8[256] =
+{
+	/* 00 - 1F */
+	{ _LDBMI, _M, _I8, 5 }, { _DB, 0, 0, 1 }, { _LDWMI, _M, _I16, 6 }, { _DB, 0, 0, 1 },
+	{ _POPBM, _M, 0, 6 }, { _DB, 0, 0, 1 }, { _POPWM, _M, 0, 6 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDBMM, _M, _M16, 8 }, { _DB, 0, 0, 1 }, { _LDWMM, _M, _M16, 8 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _ANDCFBRM, _A, _M, 8 }, { _ORCFBRM, _A, _M, 8 }, { _XORCFBRM, _A, _M, 8 }, { _LDCFBRM, _A, _M, 8 },
+	{ _STCFBRM, _A, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 },
+	{ _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 }, { _ANDCFBIM, _I3, _M, 8 },
+	{ _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 },
+	{ _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 }, { _ORCFBIM, _I3, _M, 8 },
+	{ _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 },
+	{ _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 }, { _XORCFBIM, _I3, _M, 8 },
+	{ _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 },
+	{ _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 }, { _LDCFBIM, _I3, _M, 8 },
+
+	/* A0 - BF */
+	{ _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 },
+	{ _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 }, { _STCFBIM, _I3, _M, 8 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+
+	/* C0 - DF */
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, 
+	{ _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 }, { _BITBIM, _I3, _M, 8 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+
+	/* E0 - FF */
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }
+};
+
+
+static const tlcs900inst mnemonic_c0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHBM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _RLDRM, _A, _M, 12 }, { _RRDRM, _A, _M, 12 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _LDBMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 }, { _LDBRM, _C8, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 }, { _EXBMR, _M, _C8, 6 },
+	{ _ADDBMI, _M, _I8, 7 }, { _ADCBMI, _M, _I8, 7 }, { _SUBBMI, _M, _I8, 7 }, { _SBCBMI, _M, _I8, 7 },
+	{ _ANDBMI, _M, _I8, 7 }, { _XORBMI, _M, _I8, 7 }, { _ORBMI, _M, _I8, 7 }, { _CPBMI, _M, _I8, 6 },
+
+	/* 40 - 5F */
+	{ _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, 
+	{ _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 }, { _MULBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 }, { _MULSBRM, _MC16, _M, 18 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 }, { _DIVBRM, _MC16, _M, 22 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+	{ _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 }, { _DIVSBRM, _MC16, _M, 24 },
+
+	/* 60 - 7F */
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 }, { _INCBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 }, { _DECBIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCBM, _M, 0, 8 }, { _RRCBM, _M, 0, 8 }, { _RLBM, _M, 0, 8 }, { _RRBM, _M, 0, 8 },
+	{ _SLABM, _M, 0, 8 }, { _SRABM, _M, 0, 8 }, { _SLLBM, _M, 0, 8 }, { _SRLBM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 }, { _ADDBRM, _C8, _M, 4 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 }, { _ADDBMR, _M, _C8, 6 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 }, { _ADCBRM, _C8, _M, 4 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+	{ _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 }, { _ADCBMR, _M, _C8, 6 },
+
+	/* A0 - BF */
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 }, { _SUBBRM, _C8, _M, 4 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 }, { _SUBBMR, _M, _C8, 6 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 }, { _SBCBRM, _C8, _M, 4 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+	{ _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 }, { _SBCBMR, _M, _C8, 6 },
+
+	/* C0 - DF */
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 }, { _ANDBRM, _C8, _M, 4 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 }, { _ANDBMR, _M, _C8, 6 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 }, { _XORBRM, _C8, _M, 4 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+	{ _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 }, { _XORBMR, _M, _C8, 6 },
+
+	/* E0 - FF */
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 }, { _ORBRM, _C8, _M, 4 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 }, { _ORBMR, _M, _C8, 6 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 }, { _CPBRM, _C8, _M, 4 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+	{ _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 }, { _CPBMR, _M, _C8, 6 },
+};
+
+
+static const tlcs900inst mnemonic_c8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _LDBRI, _R, _I8, 4 },
+	{ _PUSHBR, _R, 0, 6 }, { _POPBR, _R, 0, 6 }, { _CPLBR, _R, 0, 4 }, { _NEGBR, _R, 0, 5 },
+	{ _MULBRI, _R, _I8, 18}, { _MULSBRI, _R, _I8, 18 }, { _DIVBRI, _R, _I8, 22 }, { _DIVSBRI, _R, _I8, 24 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DAABR, _R, 0, 6 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DJNZB, _R, _D8, 7 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _ANDCFBIR, _I8, _R, 4 }, { _ORCFBIR, _I8, _R, 4 }, { _XORCFBIR, _I8, _R, 4 }, { _LDCFBIR, _I8, _R, 4 },
+	{ _STCFBIR, _I8, _R, 4 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _ANDCFBRR, _A, _R, 4 }, { _ORCFBRR, _A, _R, 4 }, { _XORCFBRR, _A, _R, 4 }, { _LDCFBRR, _A, _R, 4 },
+	{ _STCFBRR, _A, _R, 4 }, { _DB, 0, 0, 1 }, { _LDCBRR, _CR8, _R, 1 }, { _LDCBRR, _R, _CR8, 1 },
+	{ _RESBIR, _I8, _R, 4 }, { _SETBIR, _I8, _R, 4 }, { _CHGBIR, _I8, _R, 4 }, { _BITBIR, _I8, _R, 4 },
+	{ _TSETBIR, _I8, _R, 6 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 },
+	{ _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 }, { _MULBRR, _MC16, _R, 18 },
+	{ _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 },
+	{ _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 }, { _MULSBRR, _MC16, _R, 18 },
+	{ _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 },
+	{ _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 }, { _DIVBRR, _MC16, _R, 22 },
+	{ _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 },
+	{ _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 }, { _DIVSBRR, _MC16, _R, 24 },
+
+	/* 60 - 7F */
+	{ _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 },
+	{ _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 }, { _INCBIR, _I3, _R, 4 },
+	{ _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 },
+	{ _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 }, { _DECBIR, _I3, _R, 4 },
+	{ _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 },
+	{ _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 },
+	{ _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 },
+	{ _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 }, { _SCCBR, _CC, _R, 6 },
+
+	/* 80 - 9F */
+	{ _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 },
+	{ _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 }, { _ADDBRR, _C8, _R, 4 },
+	{ _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 },
+	{ _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 }, { _LDBRR, _C8, _R, 4 },
+	{ _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 },
+	{ _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 }, { _ADCBRR, _C8, _R, 4 }, 
+	{ _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 },
+	{ _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 }, { _LDBRR, _R, _C8, 4 },
+
+	/* A0 - BF */
+	{ _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 },
+	{ _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 }, { _SUBBRR, _C8, _R, 4 },
+	{ _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 },
+	{ _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 }, { _LDBRI, _R, _I3, 4 },
+	{ _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 },
+	{ _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 }, { _SBCBRR, _C8, _R, 4 },
+	{ _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 },
+	{ _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 }, { _EXBRR, _C8, _R, 5 },
+
+	/* C0 - DF */
+	{ _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 },
+	{ _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 }, { _ANDBRR, _C8, _R, 4 },
+	{ _ADDBRI, _R, _I8, 4 }, { _ADCBRI, _R, _I8, 4 }, { _SUBBRI, _R, _I8, 4 }, { _SBCBRI, _R, _I8, 4 },
+	{ _ANDBRI, _R, _I8, 4 }, { _XORBRI, _R, _I8, 4 }, { _ORBRI, _R, _I8, 4 }, { _CPBRI, _R, _I8, 4 },
+	{ _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 },
+	{ _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 }, { _XORBRR, _C8, _R, 4 },
+	{ _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 },
+	{ _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 }, { _CPBRI, _R, _I3, 4 },
+
+	/* E0 - FF */
+	{ _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 },
+	{ _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 }, { _ORBRR, _C8, _R, 4 },
+	{ _RLCBIR, _I8, _R, 6 }, { _RRCBIR, _I8, _R, 6 }, { _RLBIR, _I8, _R, 6 }, { _RRBIR, _I8, _R, 6 },
+	{ _SLABIR, _I8, _R, 6 }, { _SRABIR, _I8, _R, 6 }, { _SLLBIR, _I8, _R, 6 }, { _SRLBIR, _I8, _R, 6 },
+	{ _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 },
+	{ _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 }, { _CPBRR, _C8, _R, 4 },
+	{ _RLCBRR, _A, _R, 6 }, { _RRCBRR, _A, _R, 6 }, { _RLBRR, _A, _R, 6 }, { _RRBRR, _A, _R, 6 },
+	{ _SLABRR, _A, _R, 6 }, { _SRABRR, _A, _R, 6 }, { _SLLBRR, _A, _R, 6 }, { _SRLBRR, _A, _R, 6 }
+};
+
+
+static const tlcs900inst mnemonic_d0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _PUSHWM, _M, 0, 7 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _LDWMM, _M16, _M, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 }, { _LDWRM, _C16, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 }, { _EXWMR, _M, _C16, 6 },
+	{ _ADDWMI, _M, _I16, 8 }, { _ADCWMI, _M, _I16, 8 }, { _SUBWMI, _M, _I16, 8 }, { _SBCWMI, _M, _I16, 8 },
+	{ _ANDWMI, _M, _I16, 8 }, { _XORWMI, _M, _I16, 8 }, { _ORWMI, _M, _I16, 8 }, { _CPWMI, _M, _I16, 6 },
+
+	/* 40 - 5F */
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, 
+	{ _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 }, { _MULWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 }, { _MULSWRM, _C32, _M, 26 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 }, { _DIVWRM, _C32, _M, 30 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+	{ _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 }, { _DIVSWRM, _C32, _M, 32 },
+
+	/* 60 - 7F */
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 }, { _INCWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 }, { _DECWIM, _I3, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _RLCWM, _M, 0, 8 }, { _RRCWM, _M, 0, 8 }, { _RLWM, _M, 0, 8 }, { _RRWM, _M, 0, 8 },
+	{ _SLAWM, _M, 0, 8 }, { _SRAWM, _M, 0, 8 }, { _SLLWM, _M, 0, 8 }, { _SRLWM, _M, 0, 8 },
+
+	/* 80 - 9F */
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 }, { _ADDWRM, _C16, _M, 4 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 }, { _ADDWMR, _M, _C16, 6 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 }, { _ADCWRM, _C16, _M, 4 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+	{ _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 }, { _ADCWMR, _M, _C16, 6 },
+
+	/* A0 - BF */
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 }, { _SUBWRM, _C16, _M, 4 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 }, { _SUBWMR, _M, _C16, 6 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 }, { _SBCWRM, _C16, _M, 4 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+	{ _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 }, { _SBCWMR, _M, _C16, 6 },
+
+	/* C0 - DF */
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 }, { _ANDWRM, _C16, _M, 4 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 }, { _ANDWMR, _M, _C16, 6 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 }, { _XORWRM, _C16, _M, 4 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+	{ _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 }, { _XORWMR, _M, _C16, 6 },
+
+	/* E0 - FF */
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 }, { _ORWRM, _C16, _M, 4 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 }, { _ORWMR, _M, _C16, 6 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 }, { _CPWRM, _C16, _M, 4 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+	{ _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 }, { _CPWMR, _M, _C16, 6 },
+};
+
+
+static const tlcs900inst mnemonic_d8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _LDWRI, _R, _I16, 4 },
+	{ _PUSHWR, _R, 0, 5 }, { _POPWR, _R, 0, 6 }, { _CPLWR, _R, 0, 4 }, { _NEGWR, _R, 0, 5 },
+	{ _MULWRI, _R, _I16, 26 }, { _MULSWRI, _R, _I16, 26 }, { _DIVWRI, _R, _I16, 30 }, { _DIVSWRI, _R, _I16, 32 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _BS1FRR, _A, _R, 4 }, { _BS1BRR, _A, _R, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _EXTZWR, _R, 0, 4 }, { _EXTSWR, _R, 0, 5 },
+	{ _PAAWR, _R, 0, 4 }, { _DB, 0, 0, 1 }, { _MIRRW, _R, 0, 4 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _MULAR, _R, 0, 31 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DJNZW, _R, _D8, 7 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _ANDCFWIR, _I8, _R, 4 }, { _ORCFWIR, _I8, _R, 4 }, { _XORCFWIR, _I8, _R, 4 }, { _LDCFWIR, _I8, _R, 4 },
+	{ _STCFWIR, _I8, _R, 4 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _ANDCFWRR, _A, _R, 4 }, { _ORCFWRR, _A, _R, 4 }, { _XORCFWRR, _A, _R, 4 }, { _LDCFWRR, _A, _R, 4 },
+	{ _STCFWRR, _A, _R, 4 }, { _DB, 0, 0, 1 }, { _LDCWRR, _CR16, _R, 1 }, { _LDCWRR, _R, _CR16, 1 },
+	{ _RESWIR, _I8, _R, 4 }, { _SETWIR, _I8, _R, 4 }, { _CHGWIR, _I8, _R, 4 }, { _BITWIR, _I8, _R, 4 },
+	{ _TSETWIR, _I8, _R, 6 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _MINC1, _I16, _R, 8 }, { _MINC2, _I16, _R, 8 }, { _MINC4, _I16, _R, 8 }, { _DB, 0, 0, 1 },
+	{ _MDEC1, _I16, _R, 7 }, { _MDEC2, _I16, _R, 7 }, { _MDEC4, _I16, _R, 7 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 },
+	{ _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 }, { _MULWRR, _C32, _R, 26 },
+	{ _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 },
+	{ _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 }, { _MULSWRR, _C32, _R, 26 },
+	{ _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 },
+	{ _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 }, { _DIVWRR, _C32, _R, 30 },
+	{ _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 },
+	{ _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 }, { _DIVSWRR, _C32, _R, 32 },
+
+	/* 60 - 7F */
+	{ _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 },
+	{ _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 }, { _INCWIR, _I3, _R, 4 },
+	{ _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 },
+	{ _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 }, { _DECWIR, _I3, _R, 4 },
+	{ _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 },
+	{ _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 },
+	{ _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 },
+	{ _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 }, { _SCCWR, _CC, _R, 6 },
+
+	/* 80 - 9F */
+	{ _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 },
+	{ _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 }, { _ADDWRR, _C16, _R, 4 },
+	{ _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 },
+	{ _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 }, { _LDWRR, _C16, _R, 4 },
+	{ _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 },
+	{ _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 }, { _ADCWRR, _C16, _R, 4 }, 
+	{ _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 },
+	{ _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 }, { _LDWRR, _R, _C16, 4 },
+
+	/* A0 - BF */
+	{ _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 },
+	{ _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 }, { _SUBWRR, _C16, _R, 4 },
+	{ _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 },
+	{ _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 }, { _LDWRI, _R, _I3, 4 },
+	{ _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 },
+	{ _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 }, { _SBCWRR, _C16, _R, 4 },
+	{ _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 },
+	{ _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 }, { _EXWRR, _C16, _R, 5 },
+
+	/* C0 - DF */
+	{ _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 },
+	{ _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 }, { _ANDWRR, _C16, _R, 4 },
+	{ _ADDWRI, _R, _I16, 4 }, { _ADCWRI, _R, _I16, 4 }, { _SUBWRI, _R, _I16, 4 }, { _SBCWRI, _R, _I16, 4 },
+	{ _ANDWRI, _R, _I16, 4 }, { _XORWRI, _R, _I16, 4 }, { _ORWRI, _R, _I16, 4 }, { _CPWRI, _R, _I16, 4 },
+	{ _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 },
+	{ _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 }, { _XORWRR, _C16, _R, 4 },
+	{ _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 },
+	{ _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 }, { _CPWRI, _R, _I3, 4 },
+
+	/* E0 - FF */
+	{ _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 },
+	{ _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 }, { _ORWRR, _C16, _R, 4 },
+	{ _RLCWIR, _I8, _R, 6 }, { _RRCWIR, _I8, _R, 6 }, { _RLWIR, _I8, _R, 6 }, { _RRWIR, _I8, _R, 6 },
+	{ _SLAWIR, _I8, _R, 6 }, { _SRAWIR, _I8, _R, 6 }, { _SLLWIR, _I8, _R, 6 }, { _SRLWIR, _I8, _R, 6 },
+	{ _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 },
+	{ _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 }, { _CPWRR, _C16, _R, 4 },
+	{ _RLCWRR, _A, _R, 6 }, { _RRCWRR, _A, _R, 6 }, { _RLWRR, _A, _R, 6 }, { _RRWRR, _A, _R, 6 },
+	{ _SLAWRR, _A, _R, 6 }, { _SRAWRR, _A, _R, 6 }, { _SLLWRR, _A, _R, 6 }, { _SRLWRR, _A, _R, 6 }
+};
+
+
+static const tlcs900inst mnemonic_e0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 },
+	{ _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 }, { _LDLRM, _C32, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 },
+	{ _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 }, { _ADDLRM, _C32, _M, 6 },
+	{ _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 },
+	{ _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 }, { _ADDLMR, _M, _C32, 10 },
+	{ _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 },
+	{ _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 }, { _ADCLRM, _C32, _M, 6 },
+	{ _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 },
+	{ _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 }, { _ADCLMR, _M, _C32, 10 },
+
+	/* A0 - BF */
+	{ _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 },
+	{ _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 }, { _SUBLRM, _C32, _M, 6 },
+	{ _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 },
+	{ _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 }, { _SUBLMR, _M, _C32, 10 },
+	{ _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 },
+	{ _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 }, { _SBCLRM, _C32, _M, 6 },
+	{ _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 },
+	{ _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 }, { _SBCLMR, _M, _C32, 10 },
+
+	/* C0 - DF */
+	{ _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 },
+	{ _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 }, { _ANDLRM, _C32, _M, 6 },
+	{ _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 },
+	{ _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 }, { _ANDLMR, _M, _C32, 10 },
+	{ _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 },
+	{ _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 }, { _XORLRM, _C32, _M, 6 },
+	{ _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 },
+	{ _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 }, { _XORLMR, _M, _C32, 10 },
+
+	/* E0 - FF */
+	{ _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 },
+	{ _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 }, { _ORLRM, _C32, _M, 6 },
+	{ _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 },
+	{ _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 }, { _ORLMR, _M, _C32, 10 },
+	{ _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 },
+	{ _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 }, { _CPLRM, _C32, _M, 6 },
+	{ _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 },
+	{ _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 }, { _CPLMR, _M, _C32, 6 },
+};
+
+
+static const tlcs900inst mnemonic_e8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _LDLRI, _R, _I32, 6 },
+	{ _PUSHLR, _R, 0, 7 }, { _POPLR, _R, 0, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LINK, _R, _I16, 10 }, { _UNLK, _R, 0, 8 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _EXTZLR, _R, 0, 4 }, { _EXTSLR, _R, 0, 5 },
+	{ _PAALR, _R, 0, 4 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _LDCLRR, _CR32, _R, 1 }, { _LDCLRR, _R, _CR32, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 },
+	{ _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 }, { _INCLIR, _I3, _R, 4 },
+	{ _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 },
+	{ _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 }, { _DECLIR, _I3, _R, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 },
+	{ _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 }, { _ADDLRR, _C32, _R, 7 },
+	{ _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 },
+	{ _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 }, { _LDLRR, _C32, _R, 4 },
+	{ _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 },
+	{ _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 }, { _ADCLRR, _C32, _R, 7 }, 
+	{ _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 },
+	{ _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 }, { _LDLRR, _R, _C32, 4 },
+
+	/* A0 - BF */
+	{ _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 },
+	{ _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 }, { _SUBLRR, _C32, _R, 7 },
+	{ _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 },
+	{ _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 }, { _LDLRI, _R, _I3, 4 },
+	{ _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 },
+	{ _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 }, { _SBCLRR, _C32, _R, 7 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* C0 - DF */
+	{ _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 },
+	{ _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 }, { _ANDLRR, _C32, _R, 7 },
+	{ _ADDLRI, _R, _I32, 7 }, { _ADCLRI, _R, _I32, 7 }, { _SUBLRI, _R, _I32, 7 }, { _SBCLRI, _R, _I32, 7 },
+	{ _ANDLRI, _R, _I32, 7 }, { _XORLRI, _R, _I32, 7 }, { _ORLRI, _R, _I32, 7 }, { _CPLRI, _R, _I32, 7 },
+	{ _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 },
+	{ _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 }, { _XORLRR, _C32, _R, 7 },
+	{ _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 },
+	{ _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 }, { _CPLRI, _R, _I3, 6 },
+
+	/* E0 - FF */
+	{ _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 },
+	{ _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 }, { _ORLRR, _C32, _R, 7 },
+	{ _RLCLIR, _I8, _R, 8 }, { _RRCLIR, _I8, _R, 8 }, { _RLLIR, _I8, _R, 8 }, { _RRLIR, _I8, _R, 8 },
+	{ _SLALIR, _I8, _R, 8 }, { _SRALIR, _I8, _R, 8 }, { _SLLLIR, _I8, _R, 8 }, { _SRLLIR, _I8, _R, 8 },
+	{ _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 },
+	{ _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 }, { _CPLRR, _C32, _R, 7 },
+	{ _RLCLRR, _A, _R, 8 }, { _RRCLRR, _A, _R, 8 }, { _RLLRR, _A, _R, 8 }, { _RRLRR, _A, _R, 8 },
+	{ _SLALRR, _A, _R, 8 }, { _SRALRR, _A, _R, 8 }, { _SLLLRR, _A, _R, 8 }, { _SRLLRR, _A, _R, 8 }
+};
+
+
+static const tlcs900inst mnemonic_f0[256] =
+{
+	/* 00 - 1F */
+	{ _LDBMI, _M, _I8, 5 }, { _DB, 0, 0, 1 }, { _LDWMI, _M, _I16, 6 }, { _DB, 0, 0, 1 },
+	{ _POPBM, _M, 0, 6 }, { _DB, 0, 0, 1 }, { _POPWM, _M, 0, 6 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDBMM, _M, _M16, 8 }, { _DB, 0, 0, 1 }, { _LDWMM, _M, _M16, 8 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 }, { _LDAW, _C16, _M, 4 },
+	{ _ANDCFBRM, _A, _M, 4 }, { _ORCFBRM, _A, _M, 4 }, { _XORCFBRM, _A, _M, 4 }, { _LDCFBRM, _A, _M, 4 },
+	{ _STCFBRM, _A, _M, 4 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 }, { _LDAL, _C32, _M, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 40 - 5F */
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 }, { _LDBMR, _M, _C8, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 }, { _LDWMR, _M, _C16, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 60 - 7F */
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 }, { _LDLMR, _M, _C32, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+
+	/* 80 - 9F */
+	{ _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 },
+	{ _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 }, { _ANDCFBIM, _I3, _M, 4 },
+	{ _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 },
+	{ _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 }, { _ORCFBIM, _I3, _M, 4 },
+	{ _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 },
+	{ _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 }, { _XORCFBIM, _I3, _M, 4 },
+	{ _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 },
+	{ _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 }, { _LDCFBIM, _I3, _M, 4 },
+
+	/* A0 - BF */
+	{ _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 },
+	{ _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 }, { _STCFBIM, _I3, _M, 4 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 }, { _TSETBIM, _I3, _M, 10 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 }, { _RESBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+	{ _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 }, { _SETBIM, _I3, _M, 8 },
+
+	/* C0 - DF */
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 }, { _CHGBIM, _I3, _M, 8 },
+	{ _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 }, 
+	{ _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 }, { _BITBIM, _I3, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+	{ _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 }, { _JPM, _CC, _M, 4 },
+
+	/* E0 - FF */
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 }, { _CALLM, _CC, _M, 6 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }
+};
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as source in byte operations */
+static void _80(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	/* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
+	cpustate->p1_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 4 : 2 );
+	cpustate->p2_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 5 : 3 );
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	inst = &mnemonic_80[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in byte operations */
+static void _88(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	/* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
+	cpustate->p1_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 4 : 2 );
+	cpustate->p2_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 5 : 3 );
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	cpustate->ea2.d += (INT8)cpustate->op;
+	cpustate->cycles += 2;
+	cpustate->op = RDOP();
+	inst = &mnemonic_80[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIXI/XIY/XIZ/XSP) used as source in word operations */
+static void _90(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	/* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
+	cpustate->p1_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 4 : 2 );
+	cpustate->p2_reg32 = get_reg32_current( cpustate, ( cpustate->op & 4 ) ? 5 : 3 );
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	inst = &mnemonic_90[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in word operations */
+static void _98(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	cpustate->ea2.d += (INT8)cpustate->op;
+	cpustate->cycles += 2;
+	cpustate->op = RDOP();
+	inst = &mnemonic_98[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as source in long word operations */
+static void _A0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	inst = &mnemonic_a0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in long word operations */
+static void _A8(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	cpustate->ea2.d += (INT8)cpustate->op;
+	cpustate->cycles += 2;
+	cpustate->op = RDOP();
+	inst = &mnemonic_a0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as destination in operations */
+static void _B0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	inst = &mnemonic_b0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as destination in operations */
+static void _B8(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	cpustate->ea2.d = *get_reg32_current( cpustate, cpustate->op );
+	cpustate->op = RDOP();
+	cpustate->ea2.d += (INT8)cpustate->op;
+	cpustate->cycles += 2;
+	cpustate->op = RDOP();
+	inst = &mnemonic_b8[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* memory used as source in byte operations */
+static void _C0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+	UINT32 *reg = NULL;
+
+	switch ( cpustate->op & 0x07 )
+	{
+	case 0x00:	/* (n) */
+		cpustate->ea2.d = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x01:	/* (nn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x02:	/* (nnn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->ea2.b.h2 = RDOP();
+		cpustate->cycles += 3;
+		break;
+
+	case 0x03:
+		cpustate->op = RDOP();
+		switch ( cpustate->op & 0x03 )
+		{
+		/* (xrr) */
+		case 0x00:
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+			cpustate->cycles += 5;
+			break;
+
+		/* (xrr+d16) */
+		case 0x01:
+			cpustate->ea2.b.l = RDOP();
+			cpustate->ea2.b.h = RDOP();
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l;
+			cpustate->cycles += 5;
+			break;
+
+		/* unknown/illegal */
+		case 0x02:
+			break;
+
+		case 0x03:
+			switch ( cpustate->op )
+			{
+			/* (xrr+r8) */
+			case 0x03:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (xrr+r16) */
+			case 0x07:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (pc+d16) */
+			case 0x13:
+				cpustate->ea2.b.l = RDOP();
+				cpustate->ea2.b.h = RDOP();
+				cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l;
+				cpustate->cycles += 5;
+				break;
+			}
+		}
+		break;
+
+	case 0x04:	/* (-xrr) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		*reg -= ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->ea2.d = *reg;
+		cpustate->cycles += 3;
+		break;
+
+	case 0x05:	/* (xrr+) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		cpustate->ea2.d = *reg;
+		*reg += ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->cycles += 3;
+		break;
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_c0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+static void oC8(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	if ( cpustate->op & 0x08 )
+	{
+		cpustate->p2_reg8 = get_reg8_current( cpustate, cpustate->op );
+		/* For MUL and DIV operations */
+		cpustate->p2_reg16 = get_reg16_current( cpustate, ( cpustate->op >> 1 ) & 0x03 );
+	}
+	else
+	{
+		cpustate->op = RDOP();
+		cpustate->p2_reg8 = get_reg8( cpustate, cpustate->op );
+		/* For MUL and DIV operations */
+		cpustate->p2_reg16 = get_reg16( cpustate, cpustate->op );
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_c8[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* memory used as source in word operations */
+static void _D0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+	UINT32 *reg = NULL;
+
+	switch ( cpustate->op & 0x07 )
+	{
+	case 0x00:	/* (n) */
+		cpustate->ea2.d = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x01:	/* (nn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x02:	/* (nnn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->ea2.b.h2 = RDOP();
+		cpustate->cycles += 3;
+		break;
+
+	case 0x03:
+		cpustate->op = RDOP();
+		switch ( cpustate->op & 0x03 )
+		{
+		/* (xrr) */
+		case 0x00:
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+			cpustate->cycles += 5;
+			break;
+
+		/* (xrr+d16) */
+		case 0x01:
+			cpustate->ea2.b.l = RDOP();
+			cpustate->ea2.b.h = RDOP();
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l;
+			cpustate->cycles += 5;
+			break;
+
+		/* unknown/illegal */
+		case 0x02:
+			break;
+
+		case 0x03:
+			switch ( cpustate->op )
+			{
+			/* (xrr+r8) */
+			case 0x03:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (xrr+r16) */
+			case 0x07:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (pc+d16) */
+			case 0x13:
+				cpustate->ea2.b.l = RDOP();
+				cpustate->ea2.b.h = RDOP();
+				cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l;
+				cpustate->cycles += 5;
+				break;
+			}
+		}
+		break;
+
+	case 0x04:	/* (-xrr) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		*reg -= ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->ea2.d = *reg;
+		cpustate->cycles += 3;
+		break;
+
+	case 0x05:	/* (xrr+) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		cpustate->ea2.d = *reg;
+		*reg += ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->cycles += 3;
+		break;
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_d0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+static void oD8(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	if ( cpustate->op & 0x08 )
+	{
+		cpustate->p2_reg16 = get_reg16_current( cpustate, cpustate->op );
+		cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op );
+	}
+	else
+	{
+		cpustate->op = RDOP();
+		cpustate->p2_reg16 = get_reg16( cpustate, cpustate->op );
+		cpustate->p2_reg32 = get_reg32( cpustate, cpustate->op );
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_d8[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* memory used as source in long word operations */
+static void _E0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+	UINT32 *reg = NULL;
+
+	switch ( cpustate->op & 0x07 )
+	{
+	case 0x00:	/* (n) */
+		cpustate->ea2.d = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x01:	/* (nn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x02:	/* (nnn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->ea2.b.h2 = RDOP();
+		cpustate->cycles += 3;
+		break;
+
+	case 0x03:
+		cpustate->op = RDOP();
+		switch ( cpustate->op & 0x03 )
+		{
+		/* (xrr) */
+		case 0x00:
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+			cpustate->cycles += 5;
+			break;
+
+		/* (xrr+d16) */
+		case 0x01:
+			cpustate->ea2.b.l = RDOP();
+			cpustate->ea2.b.h = RDOP();
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l;
+			cpustate->cycles += 5;
+			break;
+
+		/* unknown/illegal */
+		case 0x02:
+			break;
+
+		case 0x03:
+			switch ( cpustate->op )
+			{
+			/* (xrr+r8) */
+			case 0x03:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (xrr+r16) */
+			case 0x07:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (pc+d16) */
+			case 0x13:
+				cpustate->ea2.b.l = RDOP();
+				cpustate->ea2.b.h = RDOP();
+				cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l;
+				cpustate->cycles += 5;
+				break;
+			}
+		}
+		break;
+
+	case 0x04:	/* (-xrr) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		*reg -= ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->ea2.d = *reg;
+		cpustate->cycles += 3;
+		break;
+
+	case 0x05:	/* (xrr+) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		cpustate->ea2.d = *reg;
+		*reg += ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->cycles += 3;
+		break;
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_e0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+static void _E8(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+
+	if ( cpustate->op & 0x08 )
+	{
+		cpustate->p2_reg32 = get_reg32_current( cpustate, cpustate->op );
+	}
+	else
+	{
+		cpustate->op = RDOP();
+		cpustate->p2_reg32 = get_reg32( cpustate, cpustate->op );
+	}
+	cpustate->op = RDOP();
+	inst = &mnemonic_e8[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+/* memory used as destination operations */
+static void _F0(tlcs900_state *cpustate)
+{
+	const tlcs900inst *inst;
+	UINT32 *reg = NULL;
+
+	switch ( cpustate->op & 0x07 )
+	{
+	case 0x00:	/* (n) */
+		cpustate->ea2.d = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x01:	/* (nn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->cycles += 2;
+		break;
+
+	case 0x02:	/* (nnn) */
+		cpustate->ea2.d = RDOP();
+		cpustate->ea2.b.h = RDOP();
+		cpustate->ea2.b.h2 = RDOP();
+		cpustate->cycles += 3;
+		break;
+
+	case 0x03:
+		cpustate->op = RDOP();
+		switch ( cpustate->op & 0x03 )
+		{
+		/* (xrr) */
+		case 0x00:
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+			cpustate->cycles += 5;
+			break;
+
+		/* (xrr+d16) */
+		case 0x01:
+			cpustate->ea2.b.l = RDOP();
+			cpustate->ea2.b.h = RDOP();
+			cpustate->ea2.d = *get_reg32( cpustate, cpustate->op ) + cpustate->ea2.sw.l;
+			cpustate->cycles += 5;
+			break;
+
+		/* unknown/illegal */
+		case 0x02:
+			break;
+
+		case 0x03:
+			switch ( cpustate->op )
+			{
+			/* (xrr+r8) */
+			case 0x03:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT8) *get_reg8( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (xrr+r16) */
+			case 0x07:
+				cpustate->op = RDOP();
+				cpustate->ea2.d = *get_reg32( cpustate, cpustate->op );
+				cpustate->op = RDOP();
+				cpustate->ea2.d += (INT16) *get_reg16( cpustate, cpustate->op );
+				cpustate->cycles += 8;
+				break;
+
+			/* (pc+d16) */
+			case 0x13:
+				cpustate->ea2.b.l = RDOP();
+				cpustate->ea2.b.h = RDOP();
+				cpustate->ea2.d = cpustate->pc.d + cpustate->ea2.sw.l;
+				cpustate->cycles += 5;
+				break;
+			}
+		}
+		break;
+
+	case 0x04:	/* (-xrr) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		*reg -= ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->ea2.d = *reg;
+		cpustate->cycles += 3;
+		break;
+
+	case 0x05:	/* (xrr+) */
+		cpustate->op = RDOP();
+		reg = get_reg32( cpustate, cpustate->op );
+		cpustate->ea2.d = *reg;
+		*reg += ( 1 << ( cpustate->op & 0x03 ) );
+		cpustate->cycles += 3;
+		break;
+	}
+
+	cpustate->op = RDOP();
+	inst = &mnemonic_f0[cpustate->op];
+	prepare_operands( cpustate, inst );
+	inst->opfunc( cpustate );
+	cpustate->cycles += inst->cycles;
+}
+
+
+static const tlcs900inst mnemonic[256] =
+{
+	/* 00 - 1F */
+	{ _NOP, 0, 0, 1 }, { _NORMAL, 0, 0, 4 }, { _PUSHWR, _SR, 0, 4 }, { _POPWSR, _SR, 0, 6 },
+	{ _MAX, 0, 0, 4 }, { _HALT, 0, 0, 8 }, { _EI, _I8, 0, 5 }, { _RETI, 0, 0, 12 },
+	{ _LDBMI, _M8, _I8, 5 }, { _PUSHBI, _I8, 0, 4 }, { _LDWMI, _M8, _I16, 6 }, { _PUSHWI, _I16, 0, 5 },
+	{ _INCF, 0, 0, 2 }, { _DECF, 0, 0, 2 }, { _RET, 0, 0, 9 }, { _RETD, _I16, 0, 9 },
+	{ _RCF, 0, 0, 2 }, { _SCF, 0, 0, 2 }, { _CCF, 0, 0, 2 }, { _ZCF, 0, 0, 2 },
+	{ _PUSHBR, _A, 0, 3 }, { _POPBR, _A, 0, 4 }, { _EXBRR, _F, _F, 2 }, { _LDF, _I8, 0, 2 },
+	{ _PUSHBR, _F, 0, 3 }, { _POPBR, _F, 0, 4 }, { _JPI, _I16, 0, 7 }, { _JPI, _I24, 0, 7 },
+	{ _CALLI, _I16, 0, 12 }, { _CALLI, _I24, 0, 12 }, { _CALR, _D16, 0, 12 }, { _DB, 0, 0, 1 },
+
+	/* 20 - 3F */
+	{ _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 },
+	{ _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 }, { _LDBRI, _C8, _I8, 2 },
+	{ _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 },
+	{ _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 }, { _PUSHWR, _C16, 0, 3 },
+	{ _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 },
+	{ _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 }, { _LDWRI, _C16, _I16, 3 },
+	{ _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 },
+	{ _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 }, { _PUSHLR, _C32, 0, 5 },
+
+	/* 40 - 5F */
+	{ _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 },
+	{ _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 }, { _LDLRI, _C32, _I32, 5 },
+	{ _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 },
+	{ _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 }, { _POPWR, _C16, 0, 4 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 }, { _DB, 0, 0, 1 },
+	{ _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 },
+	{ _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 }, { _POPLR, _C32, 0, 6 },
+
+	/* 60 - 7F */
+	{ _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 },
+	{ _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 },
+	{ _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 },
+	{ _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 }, { _JR, _CC, _D8, 4 },
+	{ _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 },
+	{ _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 },
+	{ _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 },
+	{ _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 }, { _JRL, _CC, _D16, 4 },
+
+	/* 80 - 9F */
+	{ _80, 0, 0, 0 }, { _80, 0, 0, 0 }, { _80, 0, 0, 0 }, { _80, 0, 0, 0 },
+	{ _80, 0, 0, 0 }, { _80, 0, 0, 0 }, { _80, 0, 0, 0 }, { _80, 0, 0, 0 },
+	{ _88, 0, 0, 0 }, { _88, 0, 0, 0 }, { _88, 0, 0, 0 }, { _88, 0, 0, 0 },
+	{ _88, 0, 0, 0 }, { _88, 0, 0, 0 }, { _88, 0, 0, 0 }, { _88, 0, 0, 0 },
+	{ _90, 0, 0, 0 }, { _90, 0, 0, 0 }, { _90, 0, 0, 0 }, { _90, 0, 0, 0 },
+	{ _90, 0, 0, 0 }, { _90, 0, 0, 0 }, { _90, 0, 0, 0 }, { _90, 0, 0, 0 },
+	{ _98, 0, 0, 0 }, { _98, 0, 0, 0 }, { _98, 0, 0, 0 }, { _98, 0, 0, 0 },
+	{ _98, 0, 0, 0 }, { _98, 0, 0, 0 }, { _98, 0, 0, 0 }, { _98, 0, 0, 0 },
+
+	/* A0 - BF */
+	{ _A0, 0, 0, 0 }, { _A0, 0, 0, 0 }, { _A0, 0, 0, 0 }, { _A0, 0, 0, 0 },
+	{ _A0, 0, 0, 0 }, { _A0, 0, 0, 0 }, { _A0, 0, 0, 0 }, { _A0, 0, 0, 0 },
+	{ _A8, 0, 0, 0 }, { _A8, 0, 0, 0 }, { _A8, 0, 0, 0 }, { _A8, 0, 0, 0 },
+	{ _A8, 0, 0, 0 }, { _A8, 0, 0, 0 }, { _A8, 0, 0, 0 }, { _A8, 0, 0, 0 },
+	{ _B0, 0, 0, 0 }, { _B0, 0, 0, 0 }, { _B0, 0, 0, 0 }, { _B0, 0, 0, 0 },
+	{ _B0, 0, 0, 0 }, { _B0, 0, 0, 0 }, { _B0, 0, 0, 0 }, { _B0, 0, 0, 0 },
+	{ _B8, 0, 0, 0 }, { _B8, 0, 0, 0 }, { _B8, 0, 0, 0 }, { _B8, 0, 0, 0 },
+	{ _B8, 0, 0, 0 }, { _B8, 0, 0, 0 }, { _B8, 0, 0, 0 }, { _B8, 0, 0, 0 },
+
+	/* C0 - DF */
+	{ _C0, 0, 0, 0 }, { _C0, 0, 0, 0 }, { _C0, 0, 0, 0 }, { _C0, 0, 0, 0 },
+	{ _C0, 0, 0, 0 }, { _C0, 0, 0, 0 }, { _DB, 0, 0, 0 }, { oC8, 0, 0, 0 },
+	{ oC8, 0, 0, 0 }, { oC8, 0, 0, 0 }, { oC8, 0, 0, 0 }, { oC8, 0, 0, 0 },
+	{ oC8, 0, 0, 0 }, { oC8, 0, 0, 0 }, { oC8, 0, 0, 0 }, { oC8, 0, 0, 0 },
+	{ _D0, 0, 0, 0 }, { _D0, 0, 0, 0 }, { _D0, 0, 0, 0 }, { _D0, 0, 0, 0 },
+	{ _D0, 0, 0, 0 }, { _D0, 0, 0, 0 }, { _DB, 0, 0, 0 }, { oD8, 0, 0, 0 },
+	{ oD8, 0, 0, 0 }, { oD8, 0, 0, 0 }, { oD8, 0, 0, 0 }, { oD8, 0, 0, 0 },
+	{ oD8, 0, 0, 0 }, { oD8, 0, 0, 0 }, { oD8, 0, 0, 0 }, { oD8, 0, 0, 0 },
+
+	/* E0 - FF */
+	{ _E0, 0, 0, 0 }, { _E0, 0, 0, 0 }, { _E0, 0, 0, 0 }, { _E0, 0, 0, 0 },
+	{ _E0, 0, 0, 0 }, { _E0, 0, 0, 0 }, { _DB, 0, 0, 0 }, { _E8, 0, 0, 0 },
+	{ _E8, 0, 0, 0 }, { _E8, 0, 0, 0 }, { _E8, 0, 0, 0 }, { _E8, 0, 0, 0 },
+	{ _E8, 0, 0, 0 }, { _E8, 0, 0, 0 }, { _E8, 0, 0, 0 }, { _E8, 0, 0, 0 },
+	{ _F0, 0, 0, 0 }, { _F0, 0, 0, 0 }, { _F0, 0, 0, 0 }, { _F0, 0, 0, 0 },
+	{ _F0, 0, 0, 0 }, { _F0, 0, 0, 0 }, { _DB, 0, 0, 0 }, { _LDX, 0, 0, 9 },
+	{ _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 },
+	{ _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 }, { _SWI, _I3, 0, 16 }
+};
+
+
diff --git a/src/emu/cpu/tlcs900/dasm900.c b/src/emu/cpu/tlcs900/dasm900.c
new file mode 100644
index 00000000000..e9202274070
--- /dev/null
+++ b/src/emu/cpu/tlcs900/dasm900.c
@@ -0,0 +1,2246 @@
+/*******************************************************************
+
+Toshiba TLCS-900/H disassembly
+
+*******************************************************************/
+
+#include "cpuintrf.h"
+#include "debugger.h"
+#include "tlcs900.h"
+
+
+enum e_mnemonics
+{
+	_ADC, _ADD, _AND, _ANDCF, _BIT, _BS1B,
+	_BS1F, _CALL, _CALR, _CCF, _CHG, _CP,
+	_CPD, _CPDW, _CPDR, _CPDRW, _CPI, _CPIR,
+	_CPIRW, _CPIW, _CPL, _DAA, _DB, _DEC,
+	_DECF, _DECW, _DIV, _DIVS, _DJNZ, _EI,
+	_EX, _EXTS, _EXTZ, _HALT, _INC, _INCF,
+	_INCW, _JP, _JR, _JRL, _LD, _LDA,
+	_LDC, _LDCF, _LDD, _LDDR, _LDDRW, _LDDW,
+	_LDF, _LDI, _LDIR, _LDIRW, _LDIW, _LDW,
+	_LDX, _LINK, _MAX, _MDEC1, _MDEC2, _MDEC4,
+	_MINC1, _MINC2, _MINC4, _MIRR, _MUL, _MULA,
+	_MULS, _NEG, _NOP, _NORMAL, _OR, _ORCF,
+	_PAA, _POP, _POPW, _PUSH, _PUSHW, _RCF,
+	_RES, _RET, _RETD, _RETI, _RL, _RLC,
+	_RLCW, _RLD, _RLW, _RR, _RRC, _RRCW,
+	_RRD, _RRW, _SBC, _SCC, _SCF, _SET,
+	_SLA, _SLAW, _SLL, _SLLW, _SRA, _SRAW,
+	_SRL, _SRLW, _STCF, _SUB, _SWI, _TSET,
+	_UNLK, _XOR, _XORCF, _ZCF,
+	_80, _88, _90, _98, _A0, _A8, _B0, _B8,
+	_C0, oC8, _D0, oD8, _E0, _E8, _F0
+};
+
+
+static const char *s_mnemonic[] =
+{
+	"adc", "add", "and", "andcf", "bit", "bs1b",
+	"bs1f", "call", "calr", "ccf", "chg", "cp",
+	"cpd", "cpdw", "cpdr", "cpdrw", "cpi", "cpir",
+	"cpirw", "cpiw", "cpl", "daa", "db", "dec",
+	"decf", "decw", "div", "divs", "djnz", "ei",
+	"ex", "exts", "extz", "halt", "inc", "incf",
+	"incw", "jp" ,"jr", "jrl", "ld", "lda",
+	"ldc", "ldcf", "ldd", "lddr", "lddrw", "lddw",
+	"ldf", "ldi", "ldir", "ldirw", "ldiw", "ldw",
+	"ldx", "link", "max", "mdec1", "mdec2", "mdec4",
+	"minc1", "minc2", "minc4", "mirr", "mul", "mula",
+	"muls", "neg", "nop", "normal", "or", "orcf",
+	"paa", "pop", "popw", "push", "pushw", "rcf",
+	"res", "ret", "retd", "reti", "rl", "rlc",
+	"rlcw", "rld", "rlw", "rr", "rrc", "rrcw",
+	"rrd", "rrw", "sbc", "scc", "scf", "set",
+	"sla", "slaw", "sll", "sllw", "sra", "sraw",
+	"srl", "srlw", "stcf", "sub", "swi", "tset",
+	"unlk", "xor", "xorcf", "zcf",
+	"db", "db", "db", "db", "db", "db", "db", "db",
+	"db", "db", "db", "db", "db", "db", "db"
+};
+
+
+enum e_operand
+{
+	_A=1,		/* currect register set register A */
+	_C8,		/* current register set byte */
+	_C16,		/* current register set word */
+	_C32,		/* current register set long word */
+	_MC16,		/* current register set mul/div register word */
+	_CC,		/* condition */
+	_CR8,		/* byte control register */
+	_CR16,		/* word control register */
+	_CR32,		/* long word control register */
+	_D8,		/* byte displacement */
+	_D16,		/* word displacement */
+	_F,			/* F register */
+	_I3,		/* immediate 3 bit (part of last byte) */
+	_I8,		/* immediate byte */
+	_I16,		/* immediate word */
+	_I24,		/* immediate 3 byte address */
+	_I32,		/* immediate long word */
+	_M,			/* memory location (defined by extension) */
+	_M8,		/* (8) */
+	_M16,		/* (i16) */
+	_R,			/* register */
+	_SR,		/* status register */
+};
+
+
+typedef struct 
+{
+	int		mnemonic;
+	int		operand1;
+	int		operand2;
+} tlcs900inst;
+
+
+static const tlcs900inst mnemonic_80[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSH, _M, 0 }, { _DB, 0, 0 }, { _RLD, _A, _M }, { _RRD, _A, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LDI, 0, 0 }, { _LDIR, 0, 0 }, { _LDD, 0, 0 }, { _LDDR, 0, 0 },
+	{ _CPI, 0, 0 }, { _CPIR, 0, 0 }, { _CPD, 0, 0 }, { _CPDR, 0, 0 },
+	{ _DB, 0, 0 }, { _LD, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _ADD, _M, _I8 }, { _ADC, _M, _I8 }, { _SUB, _M, _I8 }, { _SBC, _M, _I8 },
+	{ _AND, _M, _I8 }, { _XOR, _M, _I8 }, { _OR, _M, _I8 }, { _CP, _M, _I8 },
+
+	/* 40 - 5F */
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, 
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLC, _M, 0 }, { _RRC, _M, 0 }, { _RL, _M, 0 }, { _RR, _M, 0 },
+	{ _SLA, _M, 0 }, { _SRA, _M, 0 }, { _SLL, _M, 0 }, { _SRL, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+
+	/* A0 - BF */
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+
+	/* C0 - DF */
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+
+	/* E0 - FF */
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+};
+
+
+static const tlcs900inst mnemonic_88[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSH, _M, 0 }, { _DB, 0, 0 }, { _RLD, _A, _M }, { _RRD, _A, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _LD, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _ADD, _M, _I8 }, { _ADC, _M, _I8 }, { _SUB, _M, _I8 }, { _SBC, _M, _I8 },
+	{ _AND, _M, _I8 }, { _XOR, _M, _I8 }, { _OR, _M, _I8 }, { _CP, _M, _I8 },
+
+	/* 40 - 5F */
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, 
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLC, _M, 0 }, { _RRC, _M, 0 }, { _RL, _M, 0 }, { _RR, _M, 0 },
+	{ _SLA, _M, 0 }, { _SRA, _M, 0 }, { _SLL, _M, 0 }, { _SRL, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+
+	/* A0 - BF */
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+
+	/* C0 - DF */
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+
+	/* E0 - FF */
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+};
+
+
+static const tlcs900inst mnemonic_90[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSHW, _M, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LDIW, 0, 0 }, { _LDIRW, 0, 0 }, { _LDDW, 0, 0 }, { _LDDRW, 0, 0 },
+	{ _CPIW, 0, 0 }, { _CPIRW, 0, 0 }, { _CPDW, 0, 0 }, { _CPDRW, 0, 0 },
+	{ _DB, 0, 0 }, { _LDW, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _ADD, _M, _I16 }, { _ADC, _M, _I16 }, { _SUB, _M, _I16 }, { _SBC, _M, _I16 },
+	{ _AND, _M, _I16 }, { _XOR, _M, _I16 }, { _OR, _M, _I16 }, { _CP, _M, _I16 },
+
+	/* 40 - 5F */
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, 
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+
+	/* 60 - 7F */
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLCW, _M, 0 }, { _RRCW, _M, 0 }, { _RLW, _M, 0 }, { _RRW, _M, 0 },
+	{ _SLAW, _M, 0 }, { _SRAW, _M, 0 }, { _SLLW, _M, 0 }, { _SRLW, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+
+	/* A0 - BF */
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+
+	/* C0 - DF */
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+
+	/* E0 - FF */
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+};
+
+
+static const tlcs900inst mnemonic_98[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSHW, _M, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _LDW, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _ADD, _M, _I16 }, { _ADC, _M, _I16 }, { _SUB, _M, _I16 }, { _SBC, _M, _I16 },
+	{ _AND, _M, _I16 }, { _XOR, _M, _I16 }, { _OR, _M, _I16 }, { _CP, _M, _I16 },
+
+	/* 40 - 5F */
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, 
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+
+	/* 60 - 7F */
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLCW, _M, 0 }, { _RRCW, _M, 0 }, { _RLW, _M, 0 }, { _RRW, _M, 0 },
+	{ _SLAW, _M, 0 }, { _SRAW, _M, 0 }, { _SLLW, _M, 0 }, { _SRLW, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+
+	/* A0 - BF */
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+
+	/* C0 - DF */
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+
+	/* E0 - FF */
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+};
+
+
+static const tlcs900inst mnemonic_a0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M },
+	{ _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M },
+	{ _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M },
+	{ _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 },
+	{ _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 },
+	{ _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M },
+	{ _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M },
+	{ _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 },
+	{ _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 },
+
+	/* A0 - BF */
+	{ _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M },
+	{ _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M },
+	{ _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 },
+	{ _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 },
+	{ _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M },
+	{ _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M },
+	{ _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 },
+	{ _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 },
+
+	/* C0 - DF */
+	{ _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M },
+	{ _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M },
+	{ _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 },
+	{ _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 },
+	{ _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M },
+	{ _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M },
+	{ _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 },
+	{ _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 },
+
+	/* E0 - FF */
+	{ _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M },
+	{ _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M },
+	{ _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 },
+	{ _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 },
+	{ _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M },
+	{ _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M },
+	{ _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 },
+	{ _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 },
+};
+
+
+static const tlcs900inst mnemonic_b0[256] =
+{
+	/* 00 - 1F */
+	{ _LD, _M, _I8 }, { _DB, 0, 0 }, { _LD, _M, _I16 }, { _DB, 0, 0 },
+	{ _POP, _M, 0 }, { _DB, 0, 0 }, { _POPW, _M, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _M16 }, { _DB, 0, 0 }, { _LDW, _M, _M16 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _ANDCF, _A, _M }, { _ORCF, _A, _M }, { _XORCF, _A, _M }, { _LDCF, _A, _M },
+	{ _STCF, _A, _M }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+
+	/* A0 - BF */
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+
+	/* C0 - DF */
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, 
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+
+	/* E0 - FF */
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 },
+	{ _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 },
+	{ _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 },
+	{ _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 }, { _RET, _CC, 0 }
+};
+
+
+static const tlcs900inst mnemonic_b8[256] =
+{
+	/* 00 - 1F */
+	{ _LD, _M, _I8 }, { _DB, 0, 0 }, { _LD, _M, _I16 }, { _DB, 0, 0 },
+	{ _POP, _M, 0 }, { _DB, 0, 0 }, { _POPW, _M, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _M16 }, { _DB, 0, 0 }, { _LDW, _M, _M16 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _ANDCF, _A, _M }, { _ORCF, _A, _M }, { _XORCF, _A, _M }, { _LDCF, _A, _M },
+	{ _STCF, _A, _M }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+
+	/* A0 - BF */
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+
+	/* C0 - DF */
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, 
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+
+	/* E0 - FF */
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }
+};
+
+
+static const tlcs900inst mnemonic_c0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSH, _M, 0 }, { _DB, 0, 0 }, { _RLD, _A, _M }, { _RRD, _A, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _LD, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M }, { _LD, _C8, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 }, { _EX, _M, _C8 },
+	{ _ADD, _M, _I8 }, { _ADC, _M, _I8 }, { _SUB, _M, _I8 }, { _SBC, _M, _I8 },
+	{ _AND, _M, _I8 }, { _XOR, _M, _I8 }, { _OR, _M, _I8 }, { _CP, _M, _I8 },
+
+	/* 40 - 5F */
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, 
+	{ _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M }, { _MUL, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M }, { _MULS, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M }, { _DIV, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+	{ _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M }, { _DIVS, _MC16, _M },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M }, { _INC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M }, { _DEC, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLC, _M, 0 }, { _RRC, _M, 0 }, { _RL, _M, 0 }, { _RR, _M, 0 },
+	{ _SLA, _M, 0 }, { _SRA, _M, 0 }, { _SLL, _M, 0 }, { _SRL, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M }, { _ADD, _C8, _M },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 }, { _ADD, _M, _C8 },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M }, { _ADC, _C8, _M },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+	{ _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 }, { _ADC, _M, _C8 },
+
+	/* A0 - BF */
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M }, { _SUB, _C8, _M },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 }, { _SUB, _M, _C8 },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M }, { _SBC, _C8, _M },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+	{ _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 }, { _SBC, _M, _C8 },
+
+	/* C0 - DF */
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M }, { _AND, _C8, _M },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 }, { _AND, _M, _C8 },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M }, { _XOR, _C8, _M },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+	{ _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 }, { _XOR, _M, _C8 },
+
+	/* E0 - FF */
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M }, { _OR, _C8, _M },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 }, { _OR, _M, _C8 },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M }, { _CP, _C8, _M },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+	{ _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 }, { _CP, _M, _C8 },
+};
+
+
+/* TODO: _MUL_M_I8, _MULS_M_I8, _DIV_M_I8, _DIVS_M_i8 need to be fixed */
+static const tlcs900inst mnemonic_c8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _LD, _R, _I8 },
+	{ _PUSH, _R, 0 }, { _POP, _R, 0 }, { _CPL, _R, 0 }, { _NEG, _R, 0 },
+	{ _MUL, _R, _I8 }, { _MULS, _R, _I8 }, { _DIV, _R, _I8 }, { _DIVS, _R, _I8 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DAA, _R, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DJNZ, _R, _D8 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _ANDCF, _I8, _R }, { _ORCF, _I8, _R }, { _XORCF, _I8, _R }, { _LDCF, _I8, _R },
+	{ _STCF, _I8, _R }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _ANDCF, _A, _R }, { _ORCF, _A, _R }, { _XORCF, _A, _R }, { _LDCF, _A, _R },
+	{ _STCF, _A, _R }, { _DB, 0, 0 }, { _LDC, _CR8, _R }, { _LDC, _R, _CR8 },
+	{ _RES, _I8, _R }, { _SET, _I8, _R }, { _CHG, _I8, _R }, { _BIT, _I8, _R },
+	{ _TSET, _I8, _R }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _MUL, _MC16, _R }, { _MUL, _MC16, _R }, { _MUL, _MC16, _R }, { _MUL, _MC16, _R },
+	{ _MUL, _MC16, _R }, { _MUL, _MC16, _R }, { _MUL, _MC16, _R }, { _MUL, _MC16, _R },
+	{ _MULS, _MC16, _R }, { _MULS, _MC16, _R }, { _MULS, _MC16, _R }, { _MULS, _MC16, _R },
+	{ _MULS, _MC16, _R }, { _MULS, _MC16, _R }, { _MULS, _MC16, _R }, { _MULS, _MC16, _R },
+	{ _DIV, _MC16, _R }, { _DIV, _MC16, _R }, { _DIV, _MC16, _R }, { _DIV, _MC16, _R },
+	{ _DIV, _MC16, _R }, { _DIV, _MC16, _R }, { _DIV, _MC16, _R }, { _DIV, _MC16, _R },
+	{ _DIVS, _MC16, _R }, { _DIVS, _MC16, _R }, { _DIVS, _MC16, _R }, { _DIVS, _MC16, _R },
+	{ _DIVS, _MC16, _R }, { _DIVS, _MC16, _R }, { _DIVS, _MC16, _R }, { _DIVS, _MC16, _R },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+
+	/* 80 - 9F */
+	{ _ADD, _C8, _R }, { _ADD, _C8, _R }, { _ADD, _C8, _R }, { _ADD, _C8, _R },
+	{ _ADD, _C8, _R }, { _ADD, _C8, _R }, { _ADD, _C8, _R }, { _ADD, _C8, _R },
+	{ _LD, _C8, _R }, { _LD, _C8, _R }, { _LD, _C8, _R }, { _LD, _C8, _R },
+	{ _LD, _C8, _R }, { _LD, _C8, _R }, { _LD, _C8, _R }, { _LD, _C8, _R },
+	{ _ADC, _C8, _R }, { _ADC, _C8, _R }, { _ADC, _C8, _R }, { _ADC, _C8, _R },
+	{ _ADC, _C8, _R }, { _ADC, _C8, _R }, { _ADC, _C8, _R }, { _ADC, _C8, _R }, 
+	{ _LD, _R, _C8 }, { _LD, _R, _C8 }, { _LD, _R, _C8 }, { _LD, _R, _C8 },
+	{ _LD, _R, _C8 }, { _LD, _R, _C8 }, { _LD, _R, _C8 }, { _LD, _R, _C8 },
+
+	/* A0 - BF */
+	{ _SUB, _C8, _R }, { _SUB, _C8, _R }, { _SUB, _C8, _R }, { _SUB, _C8, _R },
+	{ _SUB, _C8, _R }, { _SUB, _C8, _R }, { _SUB, _C8, _R }, { _SUB, _C8, _R },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _SBC, _C8, _R }, { _SBC, _C8, _R }, { _SBC, _C8, _R }, { _SBC, _C8, _R },
+	{ _SBC, _C8, _R }, { _SBC, _C8, _R }, { _SBC, _C8, _R }, { _SBC, _C8, _R },
+	{ _EX, _C8, _R }, { _EX, _C8, _R }, { _EX, _C8, _R }, { _EX, _C8, _R },
+	{ _EX, _C8, _R }, { _EX, _C8, _R }, { _EX, _C8, _R }, { _EX, _C8, _R },
+
+	/* C0 - DF */
+	{ _AND, _C8, _R }, { _AND, _C8, _R }, { _AND, _C8, _R }, { _AND, _C8, _R },
+	{ _AND, _C8, _R }, { _AND, _C8, _R }, { _AND, _C8, _R }, { _AND, _C8, _R },
+	{ _ADD, _R, _I8 }, { _ADC, _R, _I8 }, { _SUB, _R, _I8 }, { _SBC, _R, _I8 },
+	{ _AND, _R, _I8 }, { _XOR, _R, _I8 }, { _OR, _R, _I8 }, { _CP, _R, _I8 },
+	{ _XOR, _C8, _R }, { _XOR, _C8, _R }, { _XOR, _C8, _R }, { _XOR, _C8, _R },
+	{ _XOR, _C8, _R }, { _XOR, _C8, _R }, { _XOR, _C8, _R }, { _XOR, _C8, _R },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+
+	/* E0 - FF */
+	{ _OR, _C8, _R }, { _OR, _C8, _R }, { _OR, _C8, _R }, { _OR, _C8, _R },
+	{ _OR, _C8, _R }, { _OR, _C8, _R }, { _OR, _C8, _R }, { _OR, _C8, _R },
+	{ _RLC, _I8, _R }, { _RRC, _I8, _R }, { _RL, _I8, _R }, { _RR, _I8, _R },
+	{ _SLA, _I8, _R }, { _SRA, _I8, _R }, { _SLL, _I8, _R }, { _SRL, _I8, _R },
+	{ _CP, _C8, _R }, { _CP, _C8, _R }, { _CP, _C8, _R }, { _CP, _C8, _R },
+	{ _CP, _C8, _R }, { _CP, _C8, _R }, { _CP, _C8, _R }, { _CP, _C8, _R },
+	{ _RLC, _A, _R }, { _RRC, _A, _R }, { _RL, _A, _R }, { _RR, _A, _R },
+	{ _SLA, _A, _R }, { _SRA, _A, _R }, { _SLL, _A, _R }, { _SRL, _A, _R }
+};
+
+
+static const tlcs900inst mnemonic_d0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _PUSHW, _M, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _LDW, _M16, _M }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M }, { _LD, _C16, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 }, { _EX, _M, _C16 },
+	{ _ADD, _M, _I16 }, { _ADC, _M, _I16 }, { _SUB, _M, _I16 }, { _SBC, _M, _I16 },
+	{ _AND, _M, _I16 }, { _XOR, _M, _I16 }, { _OR, _M, _I16 }, { _CP, _M, _I16 },
+
+	/* 40 - 5F */
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, 
+	{ _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M }, { _MUL, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M }, { _MULS, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M }, { _DIV, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+	{ _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M }, { _DIVS, _C32, _M },
+
+	/* 60 - 7F */
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M }, { _INCW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M }, { _DECW, _I3, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _RLCW, _M, 0 }, { _RRCW, _M, 0 }, { _RLW, _M, 0 }, { _RRW, _M, 0 },
+	{ _SLAW, _M, 0 }, { _SRAW, _M, 0 }, { _SLLW, _M, 0 }, { _SRLW, _M, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M }, { _ADD, _C16, _M },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 }, { _ADD, _M, _C16 },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M }, { _ADC, _C16, _M },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+	{ _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 }, { _ADC, _M, _C16 },
+
+	/* A0 - BF */
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M }, { _SUB, _C16, _M },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 }, { _SUB, _M, _C16 },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M }, { _SBC, _C16, _M },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+	{ _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 }, { _SBC, _M, _C16 },
+
+	/* C0 - DF */
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M }, { _AND, _C16, _M },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 }, { _AND, _M, _C16 },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M }, { _XOR, _C16, _M },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+	{ _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 }, { _XOR, _M, _C16 },
+
+	/* E0 - FF */
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M }, { _OR, _C16, _M },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 }, { _OR, _M, _C16 },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M }, { _CP, _C16, _M },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+	{ _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 }, { _CP, _M, _C16 },
+};
+
+
+static const tlcs900inst mnemonic_d8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _LD, _R, _I16 },
+	{ _PUSH, _R, 0 }, { _POP, _R, 0 }, { _CPL, _R, 0 }, { _NEG, _R, 0 },
+	{ _MUL, _R, _I16 }, { _MULS, _R, _I16 }, { _DIV, _R, _I16 }, { _DIVS, _R, _I16 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _BS1F, _A, _R }, { _BS1B, _A, _R },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _EXTZ, _R, 0 }, { _EXTS, _R, 0 },
+	{ _PAA, _R, 0 }, { _DB, 0, 0 }, { _MIRR, _R, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _MULA, _R, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DJNZ, _R, _D8 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _ANDCF, _I8, _R }, { _ORCF, _I8, _R }, { _XORCF, _I8, _R }, { _LDCF, _I8, _R },
+	{ _STCF, _I8, _R }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _ANDCF, _A, _R }, { _ORCF, _A, _R }, { _XORCF, _A, _R }, { _LDCF, _A, _R },
+	{ _STCF, _A, _R }, { _DB, 0, 0 }, { _LDC, _CR16, _R }, { _LDC, _R, _CR16 },
+	{ _RES, _I8, _R }, { _SET, _I8, _R }, { _CHG, _I8, _R }, { _BIT, _I8, _R },
+	{ _TSET, _I8, _R }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _MINC1, _I16, _R }, { _MINC2, _I16, _R }, { _MINC4, _I16, _R }, { _DB, 0, 0 },
+	{ _MDEC1, _I16, _R }, { _MDEC2, _I16, _R }, { _MDEC4, _I16, _R }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _MUL, _C32, _R }, { _MUL, _C32, _R }, { _MUL, _C32, _R }, { _MUL, _C32, _R },
+	{ _MUL, _C32, _R }, { _MUL, _C32, _R }, { _MUL, _C32, _R }, { _MUL, _C32, _R },
+	{ _MULS, _C32, _R }, { _MULS, _C32, _R }, { _MULS, _C32, _R }, { _MULS, _C32, _R },
+	{ _MULS, _C32, _R }, { _MULS, _C32, _R }, { _MULS, _C32, _R }, { _MULS, _C32, _R },
+	{ _DIV, _C32, _R }, { _DIV, _C32, _R }, { _DIV, _C32, _R }, { _DIV, _C32, _R },
+	{ _DIV, _C32, _R }, { _DIV, _C32, _R }, { _DIV, _C32, _R }, { _DIV, _C32, _R },
+	{ _DIVS, _C32, _R }, { _DIVS, _C32, _R }, { _DIVS, _C32, _R }, { _DIVS, _C32, _R },
+	{ _DIVS, _C32, _R }, { _DIVS, _C32, _R }, { _DIVS, _C32, _R }, { _DIVS, _C32, _R },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+	{ _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R }, { _SCC, _CC, _R },
+
+	/* 80 - 9F */
+	{ _ADD, _C16, _R }, { _ADD, _C16, _R }, { _ADD, _C16, _R }, { _ADD, _C16, _R },
+	{ _ADD, _C16, _R }, { _ADD, _C16, _R }, { _ADD, _C16, _R }, { _ADD, _C16, _R },
+	{ _LD, _C16, _R }, { _LD, _C16, _R }, { _LD, _C16, _R }, { _LD, _C16, _R },
+	{ _LD, _C16, _R }, { _LD, _C16, _R }, { _LD, _C16, _R }, { _LD, _C16, _R },
+	{ _ADC, _C16, _R }, { _ADC, _C16, _R }, { _ADC, _C16, _R }, { _ADC, _C16, _R },
+	{ _ADC, _C16, _R }, { _ADC, _C16, _R }, { _ADC, _C16, _R }, { _ADC, _C16, _R }, 
+	{ _LD, _R, _C16 }, { _LD, _R, _C16 }, { _LD, _R, _C16 }, { _LD, _R, _C16 },
+	{ _LD, _R, _C16 }, { _LD, _R, _C16 }, { _LD, _R, _C16 }, { _LD, _R, _C16 },
+
+	/* A0 - BF */
+	{ _SUB, _C16, _R }, { _SUB, _C16, _R }, { _SUB, _C16, _R }, { _SUB, _C16, _R },
+	{ _SUB, _C16, _R }, { _SUB, _C16, _R }, { _SUB, _C16, _R }, { _SUB, _C16, _R },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _SBC, _C16, _R }, { _SBC, _C16, _R }, { _SBC, _C16, _R }, { _SBC, _C16, _R },
+	{ _SBC, _C16, _R }, { _SBC, _C16, _R }, { _SBC, _C16, _R }, { _SBC, _C16, _R },
+	{ _EX, _C16, _R }, { _EX, _C16, _R }, { _EX, _C16, _R }, { _EX, _C16, _R },
+	{ _EX, _C16, _R }, { _EX, _C16, _R }, { _EX, _C16, _R }, { _EX, _C16, _R },
+
+	/* C0 - DF */
+	{ _AND, _C16, _R }, { _AND, _C16, _R }, { _AND, _C16, _R }, { _AND, _C16, _R },
+	{ _AND, _C16, _R }, { _AND, _C16, _R }, { _AND, _C16, _R }, { _AND, _C16, _R },
+	{ _ADD, _R, _I16 }, { _ADC, _R, _I16 }, { _SUB, _R, _I16 }, { _SBC, _R, _I16 },
+	{ _AND, _R, _I16 }, { _XOR, _R, _I16 }, { _OR, _R, _I16 }, { _CP, _R, _I16 },
+	{ _XOR, _C16, _R }, { _XOR, _C16, _R }, { _XOR, _C16, _R }, { _XOR, _C16, _R },
+	{ _XOR, _C16, _R }, { _XOR, _C16, _R }, { _XOR, _C16, _R }, { _XOR, _C16, _R },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+
+	/* E0 - FF */
+	{ _OR, _C16, _R }, { _OR, _C16, _R }, { _OR, _C16, _R }, { _OR, _C16, _R },
+	{ _OR, _C16, _R }, { _OR, _C16, _R }, { _OR, _C16, _R }, { _OR, _C16, _R },
+	{ _RLC, _I8, _R }, { _RRC, _I8, _R }, { _RL, _I8, _R }, { _RR, _I8, _R },
+	{ _SLA, _I8, _R }, { _SRA, _I8, _R }, { _SLL, _I8, _R }, { _SRL, _I8, _R },
+	{ _CP, _C16, _R }, { _CP, _C16, _R }, { _CP, _C16, _R }, { _CP, _C16, _R },
+	{ _CP, _C16, _R }, { _CP, _C16, _R }, { _CP, _C16, _R }, { _CP, _C16, _R },
+	{ _RLC, _A, _R }, { _RRC, _A, _R }, { _RL, _A, _R }, { _RR, _A, _R },
+	{ _SLA, _A, _R }, { _SRA, _A, _R }, { _SLL, _A, _R }, { _SRL, _A, _R }
+};
+
+
+static const tlcs900inst mnemonic_e0[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M },
+	{ _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M }, { _LD, _C32, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M },
+	{ _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M }, { _ADD, _C32, _M },
+	{ _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 },
+	{ _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 }, { _ADD, _M, _C32 },
+	{ _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M },
+	{ _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M }, { _ADC, _C32, _M },
+	{ _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 },
+	{ _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 }, { _ADC, _M, _C32 },
+
+	/* A0 - BF */
+	{ _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M },
+	{ _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M }, { _SUB, _C32, _M },
+	{ _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 },
+	{ _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 }, { _SUB, _M, _C32 },
+	{ _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M },
+	{ _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M }, { _SBC, _C32, _M },
+	{ _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 },
+	{ _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 }, { _SBC, _M, _C32 },
+
+	/* C0 - DF */
+	{ _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M },
+	{ _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M }, { _AND, _C32, _M },
+	{ _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 },
+	{ _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 }, { _AND, _M, _C32 },
+	{ _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M },
+	{ _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M }, { _XOR, _C32, _M },
+	{ _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 },
+	{ _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 }, { _XOR, _M, _C32 },
+
+	/* E0 - FF */
+	{ _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M },
+	{ _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M }, { _OR, _C32, _M },
+	{ _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 },
+	{ _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 }, { _OR, _M, _C32 },
+	{ _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M },
+	{ _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M }, { _CP, _C32, _M },
+	{ _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 },
+	{ _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 }, { _CP, _M, _C32 },
+};
+
+
+static const tlcs900inst mnemonic_e8[256] =
+{
+	/* 00 - 1F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _LD, _R, _I32 },
+	{ _PUSH, _R, 0 }, { _POP, _R, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LINK, _R, _I16 }, { _UNLK, _R, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _EXTZ, _R, 0 }, { _EXTS, _R, 0 },
+	{ _PAA, _R, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _LDC, _CR32, _R }, { _LDC, _R, _CR32 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R }, { _INC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R }, { _DEC, _I3, _R },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ADD, _C32, _R }, { _ADD, _C32, _R }, { _ADD, _C32, _R }, { _ADD, _C32, _R },
+	{ _ADD, _C32, _R }, { _ADD, _C32, _R }, { _ADD, _C32, _R }, { _ADD, _C32, _R },
+	{ _LD, _C32, _R }, { _LD, _C32, _R }, { _LD, _C32, _R }, { _LD, _C32, _R },
+	{ _LD, _C32, _R }, { _LD, _C32, _R }, { _LD, _C32, _R }, { _LD, _C32, _R },
+	{ _ADC, _C32, _R }, { _ADC, _C32, _R }, { _ADC, _C32, _R }, { _ADC, _C32, _R },
+	{ _ADC, _C32, _R }, { _ADC, _C32, _R }, { _ADC, _C32, _R }, { _ADC, _C32, _R }, 
+	{ _LD, _R, _C32 }, { _LD, _R, _C32 }, { _LD, _R, _C32 }, { _LD, _R, _C32 },
+	{ _LD, _R, _C32 }, { _LD, _R, _C32 }, { _LD, _R, _C32 }, { _LD, _R, _C32 },
+
+	/* A0 - BF */
+	{ _SUB, _C32, _R }, { _SUB, _C32, _R }, { _SUB, _C32, _R }, { _SUB, _C32, _R },
+	{ _SUB, _C32, _R }, { _SUB, _C32, _R }, { _SUB, _C32, _R }, { _SUB, _C32, _R },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 }, { _LD, _R, _I3 },
+	{ _SBC, _C32, _R }, { _SBC, _C32, _R }, { _SBC, _C32, _R }, { _SBC, _C32, _R },
+	{ _SBC, _C32, _R }, { _SBC, _C32, _R }, { _SBC, _C32, _R }, { _SBC, _C32, _R },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* C0 - DF */
+	{ _AND, _C32, _R }, { _AND, _C32, _R }, { _AND, _C32, _R }, { _AND, _C32, _R },
+	{ _AND, _C32, _R }, { _AND, _C32, _R }, { _AND, _C32, _R }, { _AND, _C32, _R },
+	{ _ADD, _R, _I32 }, { _ADC, _R, _I32 }, { _SUB, _R, _I32 }, { _SBC, _R, _I32 },
+	{ _AND, _R, _I32 }, { _XOR, _R, _I32 }, { _OR, _R, _I32 }, { _CP, _R, _I32 },
+	{ _XOR, _C32, _R }, { _XOR, _C32, _R }, { _XOR, _C32, _R }, { _XOR, _C32, _R },
+	{ _XOR, _C32, _R }, { _XOR, _C32, _R }, { _XOR, _C32, _R }, { _XOR, _C32, _R },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+	{ _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 }, { _CP, _R, _I3 },
+
+	/* E0 - FF */
+	{ _OR, _C32, _R }, { _OR, _C32, _R }, { _OR, _C32, _R }, { _OR, _C32, _R },
+	{ _OR, _C32, _R }, { _OR, _C32, _R }, { _OR, _C32, _R }, { _OR, _C32, _R },
+	{ _RLC, _I8, _R }, { _RRC, _I8, _R }, { _RL, _I8, _R }, { _RR, _I8, _R },
+	{ _SLA, _I8, _R }, { _SRA, _I8, _R }, { _SLL, _I8, _R }, { _SRL, _I8, _R },
+	{ _CP, _C32, _R }, { _CP, _C32, _R }, { _CP, _C32, _R }, { _CP, _C32, _R },
+	{ _CP, _C32, _R }, { _CP, _C32, _R }, { _CP, _C32, _R }, { _CP, _C32, _R },
+	{ _RLC, _A, _R }, { _RRC, _A, _R }, { _RL, _A, _R }, { _RR, _A, _R },
+	{ _SLA, _A, _R }, { _SRA, _A, _R }, { _SLL, _A, _R }, { _SRL, _A, _R }
+};
+
+
+static const tlcs900inst mnemonic_f0[256] =
+{
+	/* 00 - 1F */
+	{ _LD, _M, _I8 }, { _DB, 0, 0 }, { _LD, _M, _I16 }, { _DB, 0, 0 },
+	{ _POP, _M, 0 }, { _DB, 0, 0 }, { _POPW, _M, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _M16 }, { _DB, 0, 0 }, { _LDW, _M, _M16 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M }, { _LDA, _C16, _M },
+	{ _ANDCF, _A, _M }, { _ORCF, _A, _M }, { _XORCF, _A, _M }, { _LDCF, _A, _M },
+	{ _STCF, _A, _M }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M }, { _LDA, _C32, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 40 - 5F */
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 }, { _LD, _M, _C8 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 }, { _LD, _M, _C16 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 60 - 7F */
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 }, { _LD, _M, _C32 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+
+	/* 80 - 9F */
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M }, { _ANDCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M }, { _ORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M }, { _XORCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+	{ _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M }, { _LDCF, _I3, _M },
+
+	/* A0 - BF */
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M }, { _STCF, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M }, { _TSET, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M }, { _RES, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+	{ _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M }, { _SET, _I3, _M },
+
+	/* C0 - DF */
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M }, { _CHG, _I3, _M },
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, 
+	{ _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M }, { _BIT, _I3, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+	{ _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M }, { _JP, _CC, _M },
+
+	/* E0 - FF */
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M }, { _CALL, _CC, _M },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }
+};
+
+
+static const tlcs900inst mnemonic[256] =
+{
+	/* 00 - 1F */
+	{ _NOP, 0, 0 }, { _NORMAL, 0, 0 }, { _PUSH, _SR, 0 }, { _POP, _SR, 0 },
+	{ _MAX, 0, 0 }, { _HALT, 0, 0 }, { _EI, _I8, 0 }, { _RETI, 0, 0 },
+	{ _LD, _M8, _I8 }, { _PUSH, _I8, 0 }, { _LD, _M8, _I16 }, { _PUSH, _I16, 0 },
+	{ _INCF, 0, 0 }, { _DECF, 0, 0 }, { _RET, 0, 0 }, { _RETD, _I16, 0 },
+	{ _RCF, 0, 0 }, { _SCF, 0, 0 }, { _CCF, 0, 0 }, { _ZCF, 0, 0 },
+	{ _PUSH, _A, 0 }, { _POP, _A, 0 }, { _EX, _F, _F }, { _LDF, _I8, 0 },
+	{ _PUSH, _F, 0 }, { _POP, _F, 0 }, { _JP, _I16, 0 }, { _JP, _I24, 0 },
+	{ _CALL, _I16, 0 }, { _CALL, _I24, 0 }, { _CALR, _D16, 0 }, { _DB, 0, 0 },
+
+	/* 20 - 3F */
+	{ _LD, _C8, _I8 }, { _LD, _C8, _I8 }, { _LD, _C8, _I8 }, { _LD, _C8, _I8 },
+	{ _LD, _C8, _I8 }, { _LD, _C8, _I8 }, { _LD, _C8, _I8 }, { _LD, _C8, _I8 },
+	{ _PUSH, _C16, 0 }, { _PUSH, _C16, 0 }, { _PUSH, _C16, 0 }, { _PUSH, _C16, 0 },
+	{ _PUSH, _C16, 0 }, { _PUSH, _C16, 0 }, { _PUSH, _C16, 0 }, { _PUSH, _C16, 0 },
+	{ _LD, _C16, _I16 }, { _LD, _C16, _I16 }, { _LD, _C16, _I16 }, { _LD, _C16, _I16 },
+	{ _LD, _C16, _I16 }, { _LD, _C16, _I16 }, { _LD, _C16, _I16 }, { _LD, _C16, _I16 },
+	{ _PUSH, _C32, 0 }, { _PUSH, _C32, 0 }, { _PUSH, _C32, 0 }, { _PUSH, _C32, 0 },
+	{ _PUSH, _C32, 0 }, { _PUSH, _C32, 0 }, { _PUSH, _C32, 0 }, { _PUSH, _C32, 0 },
+
+	/* 40 - 5F */
+	{ _LD, _C32, _I32 }, { _LD, _C32, _I32 }, { _LD, _C32, _I32 }, { _LD, _C32, _I32 },
+	{ _LD, _C32, _I32 }, { _LD, _C32, _I32 }, { _LD, _C32, _I32 }, { _LD, _C32, _I32 },
+	{ _POP, _C16, 0 }, { _POP, _C16, 0 }, { _POP, _C16, 0 }, { _POP, _C16, 0 },
+	{ _POP, _C16, 0 }, { _POP, _C16, 0 }, { _POP, _C16, 0 }, { _POP, _C16, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 }, { _DB, 0, 0 },
+	{ _POP, _C32, 0 }, { _POP, _C32, 0 }, { _POP, _C32, 0 }, { _POP, _C32, 0 },
+	{ _POP, _C32, 0 }, { _POP, _C32, 0 }, { _POP, _C32, 0 }, { _POP, _C32, 0 },
+
+	/* 60 - 7F */
+	{ _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 },
+	{ _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 },
+	{ _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 },
+	{ _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 }, { _JR, _CC, _D8 },
+	{ _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 },
+	{ _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 },
+	{ _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 },
+	{ _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 }, { _JRL, _CC, _D16 },
+
+	/* 80 - 9F */
+	{ _80, 0, 0 }, { _80, 0, 0 }, { _80, 0, 0 }, { _80, 0, 0 },
+	{ _80, 0, 0 }, { _80, 0, 0 }, { _80, 0, 0 }, { _80, 0, 0 },
+	{ _88, 0, 0 }, { _88, 0, 0 }, { _88, 0, 0 }, { _88, 0, 0 },
+	{ _88, 0, 0 }, { _88, 0, 0 }, { _88, 0, 0 }, { _88, 0, 0 },
+	{ _90, 0, 0 }, { _90, 0, 0 }, { _90, 0, 0 }, { _90, 0, 0 },
+	{ _90, 0, 0 }, { _90, 0, 0 }, { _90, 0, 0 }, { _90, 0, 0 },
+	{ _98, 0, 0 }, { _98, 0, 0 }, { _98, 0, 0 }, { _98, 0, 0 },
+	{ _98, 0, 0 }, { _98, 0, 0 }, { _98, 0, 0 }, { _98, 0, 0 },
+
+	/* A0 - BF */
+	{ _A0, 0, 0 }, { _A0, 0, 0 }, { _A0, 0, 0 }, { _A0, 0, 0 },
+	{ _A0, 0, 0 }, { _A0, 0, 0 }, { _A0, 0, 0 }, { _A0, 0, 0 },
+	{ _A8, 0, 0 }, { _A8, 0, 0 }, { _A8, 0, 0 }, { _A8, 0, 0 },
+	{ _A8, 0, 0 }, { _A8, 0, 0 }, { _A8, 0, 0 }, { _A8, 0, 0 },
+	{ _B0, 0, 0 }, { _B0, 0, 0 }, { _B0, 0, 0 }, { _B0, 0, 0 },
+	{ _B0, 0, 0 }, { _B0, 0, 0 }, { _B0, 0, 0 }, { _B0, 0, 0 },
+	{ _B8, 0, 0 }, { _B8, 0, 0 }, { _B8, 0, 0 }, { _B8, 0, 0 },
+	{ _B8, 0, 0 }, { _B8, 0, 0 }, { _B8, 0, 0 }, { _B8, 0, 0 },
+
+	/* C0 - DF */
+	{ _C0, 0, 0 }, { _C0, 0, 0 }, { _C0, 0, 0 }, { _C0, 0, 0 },
+	{ _C0, 0, 0 }, { _C0, 0, 0 }, { _DB, 0, 0 }, { oC8, 0, 0 },
+	{ oC8, 0, 0 }, { oC8, 0, 0 }, { oC8, 0, 0 }, { oC8, 0, 0 },
+	{ oC8, 0, 0 }, { oC8, 0, 0 }, { oC8, 0, 0 }, { oC8, 0, 0 },
+	{ _D0, 0, 0 }, { _D0, 0, 0 }, { _D0, 0, 0 }, { _D0, 0, 0 },
+	{ _D0, 0, 0 }, { _D0, 0, 0 }, { _DB, 0, 0 }, { oD8, 0, 0 },
+	{ oD8, 0, 0 }, { oD8, 0, 0 }, { oD8, 0, 0 }, { oD8, 0, 0 },
+	{ oD8, 0, 0 }, { oD8, 0, 0 }, { oD8, 0, 0 }, { oD8, 0, 0 },
+
+	/* E0 - FF */
+	{ _E0, 0, 0 }, { _E0, 0, 0 }, { _E0, 0, 0 }, { _E0, 0, 0 },
+	{ _E0, 0, 0 }, { _E0, 0, 0 }, { _DB, 0, 0 }, { _E8, 0, 0 },
+	{ _E8, 0, 0 }, { _E8, 0, 0 }, { _E8, 0, 0 }, { _E8, 0, 0 },
+	{ _E8, 0, 0 }, { _E8, 0, 0 }, { _E8, 0, 0 }, { _E8, 0, 0 },
+	{ _F0, 0, 0 }, { _F0, 0, 0 }, { _F0, 0, 0 }, { _F0, 0, 0 },
+	{ _F0, 0, 0 }, { _F0, 0, 0 }, { _DB, 0, 0 }, { _LDX, 0, 0 },
+	{ _SWI, _I3, 0 }, { _SWI, _I3, 0 }, { _SWI, _I3, 0 }, { _SWI, _I3, 0 },
+	{ _SWI, _I3, 0 }, { _SWI, _I3, 0 }, { _SWI, _I3, 0 }, { _SWI, _I3, 0 }
+};
+
+
+
+static const char *s_reg8[8] = { "W", "A", "B", "C", "D", "E", "H", "L" };
+static const char *s_reg16[8] = { "WA", "BC", "DE", "HL", "IX", "IY", "IZ", "SP" };
+static const char *s_reg32[8] = { "XWA", "XBC", "XDE", "XHL", "XIX", "XIY", "XIZ", "XSP" };
+static const char *s_mulreg16[8] = { "??", "WA", "??", "BC", "??", "DE", "??", "HL" };
+static const char *s_allreg8[256] =
+{
+	"RA0" ,"RW0" ,"QA0" ,"QW0" ,"RC0" ,"RB0" ,"QC0" ,"QB0" ,"RE0" ,"RD0" ,"QE0" ,"QD0" ,"RL0" ,"RH0" ,"QL0" ,"QH0" ,
+	"RA1" ,"RW1" ,"QA1" ,"QW1" ,"RC1" ,"RB1" ,"QC1" ,"QB1" ,"RE1" ,"RD1" ,"QE1" ,"QD1" ,"RL1" ,"RH1" ,"QL1" ,"QH1" ,
+	"RA2" ,"RW2" ,"QA2" ,"QW2" ,"RC2" ,"RB2" ,"QC2" ,"QB2" ,"RE2" ,"RD2" ,"QE2" ,"QD2" ,"RL2" ,"RH2" ,"QL2" ,"QH2" ,
+	"RA3" ,"RW3" ,"QA3" ,"QW3" ,"RC3" ,"RB3" ,"QC3" ,"QB3" ,"RE3" ,"RD3" ,"QE3" ,"QD3" ,"RL3" ,"RH3" ,"QL3" ,"QH3" ,
+	"r40B","r41B","r42B","r43B","r44B","r45B","r46B","r47B","r48B","r49B","r4AB","r4BB","r4CB","r4DB","r4EB","r4FB",
+	"r50B","r51B","r52B","r53B","r54B","r55B","r56B","r57B","r58B","r59B","r5AB","r5BB","r5CB","r5DB","r5EB","r5FB",
+	"r60B","r61B","r62B","r63B","r64B","r65B","r66B","r67B","r68B","r69B","r6AB","r6BB","r6CB","r6DB","r6EB","r6FB",
+	"r70B","r71B","r72B","r73B","r74B","r75B","r76B","r77B","r78B","r79B","r7AB","r7BB","r7CB","r7DB","r7EB","r7FB",
+	"r80B","r81B","r82B","r83B","r84B","r85B","r86B","r87B","r88B","r89B","r8AB","r8BB","r8CB","r8DB","r8EB","r8FB",
+	"r90B","r91B","r92B","r93B","r94B","r95B","r96B","r97B","r98B","r99B","r9AB","r9BB","r9CB","r9DB","r9EB","r9FB",
+	"rA0B","rA1B","rA2B","rA3B","rA4B","rA5B","rA6B","rA7B","rA8B","rA9B","rAAB","rABB","rACB","rADB","rAEB","rAFB",
+	"rB0B","rB1B","rB2B","rB3B","rB4B","rB5B","rB6B","rB7B","rB8B","rB9B","rBAB","rBBB","rBCB","rBDB","rBEB","rBFB",
+	"rC0B","rC1B","rC2B","rC3B","rC4B","rC5B","rC6B","rC7B","rC8B","rC9B","rCAB","rCBB","rCCB","rCDB","rCEB","rCFB",
+	"RA-1","RW-1","QA-1","QW-1","RC-1","RB-1","QC-1","QB-1","RE-1","RD-1","QE-1","QD-1","RL-1","RH-1","QL-1","QH-1",
+	"A"   ,"W"   ,"QA"  ,"QW"  ,"C"   ,"B"   ,"QC"  ,"QB"  ,"E"   ,"D"   ,"QE"  ,"QD"  ,"L"   ,"H"   ,"QL"  ,"QH"  ,
+	"IXL" ,"IXH" ,"QIXL","QIXH","IYL" ,"IYH" ,"QIYL","QIYH","IZL" ,"IZH" ,"QIZL","QIZH","SPL" ,"SPH" ,"QSPL","QSPH",
+};
+
+
+static const char *s_allreg16[256] =
+{
+	"RWA0","r01W","QWA0","r03W","RBC0","r05W","QBC0","r07W","RDE0","r09W","QDE0","r0BW","RHL0","r0DW","QHL0","r0FW",
+	"RWA1","r11W","QWA1","r13W","RBC1","r15W","QBC1","r17W","RDE1","r19W","QDE1","r1BW","RHL1","r1DW","QHL1","r1FW",
+	"RWA2","r21W","QWA2","r23W","RBC2","r25W","QBC2","r27W","RDE2","r29W","QDE2","r2BW","RHL2","r2DW","QHL2","r2FW",
+	"RWA3","r31W","QWA3","r33W","RBC3","r35W","QBC3","r37W","RDE3","r39W","QDE3","r3BW","RHL3","r3DW","QHL3","r3FW",
+	"r40W","r41W","r42W","r43W","r44W","r45W","r46W","r47W","r48W","r49W","r4AW","r4BW","r4CW","r4DW","r4EW","r4FW",
+	"r50W","r51W","r52W","r53W","r54W","r55W","r56W","r57W","r58W","r59W","r5AW","r5BW","r5CW","r5DW","r5EW","r5FW",
+	"r60W","r61W","r62W","r63W","r64W","r65W","r66W","r67W","r68W","r69W","r6AW","r6BW","r6CW","r6DW","r6EW","r6FW",
+	"r70W","r71W","r72W","r73W","r74W","r75W","r76W","r77W","r78W","r79W","r7AW","r7BW","r7CW","r7DW","r7EW","r7FW",
+	"r80W","r81W","r82W","r83W","r84W","r85W","r86W","r87W","r88W","r89W","r8AW","r8BW","r8CW","r8DW","r8EW","r8FW",
+	"r90W","r91W","r92W","r93W","r94W","r95W","r96W","r97W","r98W","r99W","r9AW","r9BW","r9CW","r9DW","r9EW","r9FW",
+	"rA0W","rA1W","rA2W","rA3W","rA4W","rA5W","rA6W","rA7W","rA8W","rA9W","rAAW","rABW","rACW","rADW","rAEW","rAFW",
+	"rB0W","rB1W","rB2W","rB3W","rB4W","rB5W","rB6W","rB7W","rB8W","rB9W","rBAW","rBBW","rBCW","rBDW","rBEW","rBFW",
+	"rC0W","rC1W","rC2W","rC3W","rC4W","rC5W","rC6W","rC7W","rC8W","rC9W","rCAW","rCBW","rCCW","rCDW","rCEW","rCFW",
+	"RWA-1","rD1W","QWA-1","rD3W","RBC-1","rD5W","QBC-1","rD7W","RDE-1","rD9W","QDE-1","rDBW","RHL-1","rDDW","QHL-1","rDFW",
+	"WA"  ,"rE1W","QWA" ,"rE3W","BC"  ,"rE5W","QBC" ,"rE7W","DE"  ,"rE9W","QDE" ,"rEBW","HL"  ,"rEDW","QHL" ,"rEFW",
+	"IX"  ,"rF1W","QIX" ,"rF3W","IY"  ,"rF5W","QIY" ,"rF7W","IZ"  ,"rF9W","QIZ" ,"rFBW","SP"  ,"rFDW","QSP" ,"rFFW",
+};
+
+
+static const char *s_allreg32[256] =
+{
+	"XWA0","XWA0","XWA0","r03L","XBC0","XBC0","XBC0","r07L","XDE0","XDE0","XDE0","r0BL","XHL0","XHL0","XHL0","r0FL",
+	"XWA1","XWA1","XWA1","r13L","XBC1","XBC1","XBC1","r17L","XDE1","XDE1","XDE1","r1BL","XHL1","XHL1","XHL1","r1FL",
+	"XWA2","XWA2","XWA2","r23L","XBC2","XBC2","XBC2","r27L","XDE2","XDE2","XDE2","r2BL","XHL2","XHL2","XHL2","r2FL",
+	"XWA3","XWA3","XWA3","r33L","XBC3","XBC3","XBC3","r37L","XDE3","XDE3","XDE3","r3BL","XHL3","XHL3","XHL3","r3FL",
+	"r40L","r41L","r42L","r43L","r44L","r45L","r46L","r47L","r48L","r49L","r4AL","r4BL","r4CL","r4DL","r4EL","r4FL",
+	"r50L","r51L","r52L","r53L","r54L","r55L","r56L","r57L","r58L","r59L","r5AL","r5BL","r5CL","r5DL","r5EL","r5FL",
+	"r60L","r61L","r62L","r63L","r64L","r65L","r66L","r67L","r68L","r69L","r6AL","r6BL","r6CL","r6DL","r6EL","r6FL",
+	"r70L","r71L","r72L","r73L","r74L","r75L","r76L","r77L","r78L","r79L","r7AL","r7BL","r7CL","r7DL","r7EL","r7FL",
+	"r80L","r81L","r82L","r83L","r84L","r85L","r86L","r87L","r88L","r89L","r8AL","r8BL","r8CL","r8DL","r8EL","r8FL",
+	"r90L","r91L","r92L","r93L","r94L","r95L","r96L","r97L","r98L","r99L","r9AL","r9BL","r9CL","r9DL","r9EL","r9FL",
+	"rA0L","rA1L","rA2L","rA3L","rA4L","rA5L","rA6L","rA7L","rA8L","rA9L","rAAL","rABL","rACL","rADL","rAEL","rAFL",
+	"rB0L","rB1L","rB2L","rB3L","rB4L","rB5L","rB6L","rB7L","rB8L","rB9L","rBAL","rBBL","rBCL","rBDL","rBEL","rBFL",
+	"rC0L","rC1L","rC2L","rC3L","rC4L","rC5L","rC6L","rC7L","rC8L","rC9L","rCAL","rCBL","rCCL","rCDL","rCEL","rCFL",
+	"XWA-1","XWA-1","XWA-1","rD3L","XBC-1","XBC-1","XBC-1","rD7L","XDE-1","XDE-1","XDE-1","rDBL","XHL-1","XHL-1","XHL-1","rDFL",
+	"XWA" ,"XWA" ,"XWA" ,"rE3L","XBC" ,"XBC", "XBC" ,"rE7L","XDE" ,"XDE" ,"XDE" ,"rEDL","XHL" ,"XHL" ,"XHL" ,"rEFL",
+	"XIX" ,"XIX" ,"XIX" ,"rF3L","XIY" ,"XIY" ,"XIY" ,"rF7L","XIZ" ,"XIZ" ,"XIZ" ,"rFBL","XSP" ,"XSP" ,"XSP" ,"rFFL",
+};
+
+
+static const char *s_cond[16] =
+{
+	"F","LT","LE","ULE","PE/OV","M/MI","Z","C","T","GE","GT","UGT","PO/NOV","P/PL","NZ","NC"
+};
+
+
+CPU_DISASSEMBLE( tlcs900 )
+{
+	const tlcs900inst *dasm;
+	char *dst = buffer;
+	char buf[32];
+	UINT8	op, op1;
+	UINT32	imm;
+	int		flags = 0;
+	int		pos = 0;
+
+	op = oprom[ pos++ ];
+
+	dasm = &mnemonic[ op ];
+
+	/* Check for extended addressing modes */
+	switch( dasm->mnemonic )
+	{
+	case _80:
+		sprintf( buf, "%s", s_reg32[op & 0x07] );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_80[ op ];
+		break;
+
+	case _88:
+		imm = oprom[ pos++ ];
+		sprintf( buf, "%s+0x%02x", s_reg32[op & 0x07], imm );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_88[ op ];
+		break;
+
+	case _90:
+		sprintf( buf, "%s", s_reg32[op & 0x07] );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_90[ op ];
+		break;
+
+	case _98:
+		imm = oprom[ pos++ ];
+		sprintf( buf, "%s+0x%02x", s_reg32[op & 0x07], imm );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_98[ op ];
+		break;
+
+	case _A0:
+		sprintf( buf, "%s", s_reg32[op & 0x07] );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_a0[ op ];
+		break;
+
+	case _A8:
+		imm = oprom[ pos++ ];
+		sprintf( buf, "%s+0x%02x", s_reg32[op & 0x07], imm );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_a0[ op ];
+		break;
+
+	case _B0:
+		sprintf( buf, "%s", s_reg32[op & 0x07] );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_b0[ op ];
+		break;
+
+	case _B8:
+		imm = oprom[ pos++ ];
+		sprintf( buf, "%s+0x%02x", s_reg32[op & 0x07], imm );
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_b8[ op ];
+		break;
+
+	case _C0:
+		switch( op & 0x07 )
+		{
+		case 0x00:	/* 0xC0 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "0x%02x", imm );
+			break;
+
+		case 0x01:	/* 0xC1 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			sprintf( buf, "0x%04x", imm );
+			break;
+
+		case 0x02:	/* 0xC2 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			imm = imm | ( oprom[ pos++ ] << 16 );
+			sprintf( buf, "0x%06x", imm );
+			break;
+
+		case 0x03:	/* 0xC3 */
+			imm = oprom[ pos++ ];
+			switch( imm & 0x03 )
+			{
+			case 0x00:
+				sprintf( buf, "%s", s_allreg32[imm] );
+				break;
+
+			case 0x01:
+				op = imm;
+				imm = oprom[ pos++ ];
+				imm = imm | ( oprom[ pos++ ] << 8 );
+				sprintf( buf, "%s+0x%04x", s_allreg32[op], imm );
+				break;
+
+			case 0x02:
+				sprintf( buf, "unknown" );
+				break;
+
+			case 0x03:
+				switch( imm )
+				{
+				case 0x03:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg8[op1] );
+					break;
+
+				case 0x07:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg16[op1] );
+					break;
+
+				case 0x13:
+					imm = oprom[ pos++ ];
+					imm = imm | ( oprom[ pos++ ] << 8 );
+					sprintf( buf, "0x%06x", pc + pos + (INT16)imm );
+					break;
+				}
+				break;
+			}
+			break;
+
+		case 0x04:	/* 0xC4 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "-%s", s_allreg32[imm] );
+			break;
+
+		case 0x05:	/* 0xC5 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s+", s_allreg32[imm] );
+			break;
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_c0[ op ];
+		break;
+
+	case oC8:
+		if ( op & 0x08 )
+		{
+			sprintf( buf, "%s", s_reg8[ op & 0x07 ] );
+		}
+		else
+		{
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s", s_allreg8[imm] );
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_c8[ op ];
+		break;
+
+	case _D0:
+		switch( op & 0x07 )
+		{
+		case 0x00:	/* 0xD0 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "0x%02x", imm );
+			break;
+
+		case 0x01:	/* 0xD1 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			sprintf( buf, "0x%04x", imm );
+			break;
+
+		case 0x02:	/* 0xD2 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			imm = imm | ( oprom[ pos++ ] << 16 );
+			sprintf( buf, "0x%06x", imm );
+			break;
+
+		case 0x03:	/* 0xD3 */
+			imm = oprom[ pos++ ];
+			switch( imm & 0x03 )
+			{
+			case 0x00:
+				sprintf( buf, "%s", s_allreg32[imm] );
+				break;
+
+			case 0x01:
+				op = imm;
+				imm = oprom[ pos++ ];
+				imm = imm | ( oprom[ pos++ ] << 8 );
+				sprintf( buf, "%s+0x%04x", s_allreg32[op], imm );
+				break;
+
+			case 0x02:
+				sprintf( buf, "unknown" );
+				break;
+
+			case 0x03:
+				switch( imm )
+				{
+				case 0x03:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg8[op1] );
+					break;
+
+				case 0x07:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg16[op1] );
+					break;
+
+				case 0x13:
+					imm = oprom[ pos++ ];
+					imm = imm | ( oprom[ pos++ ] << 8 );
+					sprintf( buf, "0x%06x", pc + pos + (INT16)imm );
+					break;
+				}
+				break;
+			}
+			break;
+
+		case 0x04:	/* 0xD4 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "-%s", s_allreg32[imm] );
+			break;
+
+		case 0x05:	/* 0xD5 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s+", s_allreg32[imm] );
+			break;
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_d0[ op ];
+		break;
+
+	case oD8:
+		if ( op & 0x08 )
+		{
+			sprintf( buf, "%s", s_reg16[ op & 0x07 ] );
+		}
+		else
+		{
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s", s_allreg16[imm] );
+		}
+
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_d8[ op ];
+		break;
+
+	case _E0:
+		switch( op & 0x07 )
+		{
+		case 0x00:	/* 0xE0 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "0x%02x", imm );
+			break;
+
+		case 0x01:	/* 0xE1 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			sprintf( buf, "0x%04x", imm );
+			break;
+
+		case 0x02:	/* 0xE2 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			imm = imm | ( oprom[ pos++ ] << 16 );
+			sprintf( buf, "0x%06x", imm );
+			break;
+
+		case 0x03:	/* 0xE3 */
+			imm = oprom[ pos++ ];
+			switch( imm & 0x03 )
+			{
+			case 0x00:
+				sprintf( buf, "%s", s_allreg32[imm] );
+				break;
+
+			case 0x01:
+				op = imm;
+				imm = oprom[ pos++ ];
+				imm = imm | ( oprom[ pos++ ] << 8 );
+				sprintf( buf, "%s+0x%04x", s_allreg32[op], imm );
+				break;
+
+			case 0x02:
+				sprintf( buf, "unknown" );
+				break;
+
+			case 0x03:
+				switch( imm )
+				{
+				case 0x03:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg8[op1] );
+					break;
+
+				case 0x07:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg16[op1] );
+					break;
+
+				case 0x13:
+					imm = oprom[ pos++ ];
+					imm = imm | ( oprom[ pos++ ] << 8 );
+					sprintf( buf, "0x%06x", pc + pos + (INT16)imm );
+					break;
+				}
+				break;
+			}
+			break;
+
+		case 0x04:	/* 0xE4 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "-%s", s_allreg32[imm] );
+			break;
+
+		case 0x05:	/* 0xE5 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s+", s_allreg32[imm] );
+			break;
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_e0[ op ];
+		break;
+
+	case _E8:
+		if ( op & 0x08 )
+		{
+			sprintf( buf, "%s", s_reg32[ op & 0x07 ] );
+		}
+		else
+		{
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s", s_allreg32[imm] );
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_e8[ op ];
+		break;
+
+	case _F0:
+		switch( op & 0x07 )
+		{
+		case 0x00:	/* 0xF0 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "0x%02x", imm );
+			break;
+
+		case 0x01:	/* 0xF1 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			sprintf( buf, "0x%04x", imm );
+			break;
+
+		case 0x02:	/* 0xF2 */
+			imm = oprom[ pos++ ];
+			imm = imm | ( oprom[ pos++ ] << 8 );
+			imm = imm | ( oprom[ pos++ ] << 16 );
+			sprintf( buf, "0x%06x", imm );
+			break;
+
+		case 0x03:	/* 0xF3 */
+			imm = oprom[ pos++ ];
+			switch( imm & 0x03 )
+			{
+			case 0x00:
+				sprintf( buf, "%s", s_allreg32[imm] );
+				break;
+
+			case 0x01:
+				op = imm;
+				imm = oprom[ pos++ ];
+				imm = imm | ( oprom[ pos++ ] << 8 );
+				sprintf( buf, "%s+0x%04x", s_allreg32[op], imm );
+				break;
+
+			case 0x02:
+				sprintf( buf, "unknown" );
+				break;
+
+			case 0x03:
+				switch( imm )
+				{
+				case 0x03:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg8[op1] );
+					break;
+
+				case 0x07:
+					op = oprom[ pos++ ];
+					op1 = oprom[ pos++ ];
+					sprintf( buf, "%s+%s", s_allreg32[op], s_allreg16[op1] );
+					break;
+
+				case 0x13:
+					imm = oprom[ pos++ ];
+					imm = imm | ( oprom[ pos++ ] << 8 );
+					sprintf( buf, "0x%06x", pc + pos + (INT16)imm );
+					break;
+				}
+				break;
+			}
+			break;
+
+		case 0x04:	/* 0xF4 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "-%s", s_allreg32[imm] );
+			break;
+
+		case 0x05:	/* 0xF5 */
+			imm = oprom[ pos++ ];
+			sprintf( buf, "%s+", s_allreg32[imm] );
+			break;
+		}
+		op = oprom[ pos++ ];
+		dasm = &mnemonic_f0[ op ];
+		break;
+	}
+
+	dst += sprintf( dst, "%s", s_mnemonic[ dasm->mnemonic ] );
+
+	switch( dasm->mnemonic )
+	{
+	case _CALL:
+	case _CALR:
+		flags = DASMFLAG_STEP_OVER;
+		break;
+	case _RET:
+	case _RETD:
+	case _RETI:
+		flags = DASMFLAG_STEP_OUT;
+		break;
+	}
+
+	switch( dasm->operand1 )
+	{
+	case _A:
+		dst += sprintf( dst, " A" );
+		break;
+
+	case _C8:
+		dst += sprintf( dst, " %s", s_reg8[op & 0x07] );
+		break;
+
+	case _C16:
+		dst += sprintf( dst, " %s", s_reg16[op & 0x07] );
+		break;
+
+	case _C32:
+		dst += sprintf( dst, " %s", s_reg32[op & 0x07] );
+		break;
+
+	case _MC16:
+		dst += sprintf( dst, " %s", s_mulreg16[op & 0x07] );
+		break;
+
+	case _CC:
+		dst += sprintf( dst, " %s", s_cond[op & 0x0F] );
+		break;
+
+	case _CR8:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{
+		case 0x22:
+			dst += sprintf( dst, " DMAM0" );
+			break;
+		case 0x26:
+			dst += sprintf( dst, " DMAM1" );
+			break;
+		case 0x2a:
+			dst += sprintf( dst, " DMAM2" );
+			break;
+		case 0x2e:
+			dst += sprintf( dst, " DMAM3" );
+			break;
+		default:
+			dst += sprintf( dst, " unknown" );
+			break;
+		}
+		break;
+
+	case _CR16:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{
+		case 0x20:
+			dst += sprintf( dst, " DMAC0" );
+			break;
+		case 0x24:
+			dst += sprintf( dst, " DMAC1" );
+			break;
+		case 0x28:
+			dst += sprintf( dst, " DMAC2" );
+			break;
+		case 0x2c:
+			dst += sprintf( dst, " DMAC3" );
+			break;
+		default:
+			dst += sprintf( dst, " unknown" );
+			break;
+		}
+		break;
+
+	case _CR32:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{   
+		case 0x00:
+			dst += sprintf( dst, " DMAS0" );
+			break;
+		case 0x04:
+			dst += sprintf( dst, " DMAS1" );
+			break;
+		case 0x08:
+			dst += sprintf( dst, " DMAS2" );
+			break;
+		case 0x0c:
+			dst += sprintf( dst, " DMAS3" );
+			break;
+		case 0x10:
+			dst += sprintf( dst, " DMAD0" );
+			break;
+		case 0x14:
+			dst += sprintf( dst, " DMAD1" );  
+			break;
+		case 0x18:
+			dst += sprintf( dst, " DMAD2" );
+			break;
+		case 0x1c:
+			dst += sprintf( dst, " DMAD3" );
+			break;
+		default:
+			dst += sprintf( dst, " unknown" );
+			break;
+		}   
+		break;
+
+	case _D8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, " 0x%06x", ( pc + pos + (INT8)imm ) & 0xFFFFFF );
+		break;
+
+	case _D16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, " 0x%06x", ( pc + pos + (INT16)imm ) & 0xFFFFFF );
+		break;
+
+	case _F:
+		dst += sprintf( dst, " F" );
+		break;
+
+	case _I3:
+		dst += sprintf( dst, " %d", op & 0x07 );
+		break;
+
+	case _I8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, " 0x%02x", imm );
+		break;
+
+	case _I16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, " 0x%04x", imm );
+		break;
+
+	case _I24:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		imm = imm | ( oprom[ pos++ ] << 16 );
+		dst += sprintf( dst, " 0x%06x", imm );
+		break;
+
+	case _I32:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		imm = imm | ( oprom[ pos++ ] << 16 );
+		imm = imm | ( oprom[ pos++ ] << 24 );
+		dst += sprintf( dst, "0x%08x", imm );
+		break;
+
+	case _M:
+		switch( dasm->mnemonic )
+		{
+		case _CALL:
+		case _JP:
+		case _LDA:
+			dst += sprintf( dst, " %s", buf );
+			break;
+		default:
+			dst += sprintf( dst, " (%s)", buf );
+			break;
+		}
+		break;
+
+	case _M8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, " (0x%02x)", imm );
+		break;
+
+	case _M16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, " (0x%04x)", imm );
+		break;
+
+	case _R:
+		dst += sprintf( dst, " %s", buf );
+		break;
+
+	case _SR:
+		dst += sprintf( dst, " SR" );
+		break;
+	}
+
+	switch( dasm->operand2 )
+	{
+	case _A:
+		dst += sprintf( dst, ",A" );
+		break;
+
+	case _C8:
+		dst += sprintf( dst, ",%s", s_reg8[op & 0x07] );
+		break;
+
+	case _C16:
+		dst += sprintf( dst, ",%s", s_reg16[op & 0x07] );
+		break;
+
+	case _C32:
+		dst += sprintf( dst, ",%s", s_reg32[op & 0x07] );
+		break;
+
+	case _MC16:
+		dst += sprintf( dst, ",%s", s_mulreg16[op & 0x07] );
+		break;
+
+	case _CC:
+		dst += sprintf( dst, ",%s", s_cond[op & 0x0F] );
+		break;
+
+	case _CR8:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{
+		case 0x22:
+			dst += sprintf( dst, ",DMAM0" );
+			break;
+		case 0x26:
+			dst += sprintf( dst, ",DMAM1" );
+			break;
+		case 0x2a:
+			dst += sprintf( dst, ",DMAM2" );
+			break;
+		case 0x2e:
+			dst += sprintf( dst, ",DMAM3" );
+			break;
+		default:
+			dst += sprintf( dst, ",unknown" );
+			break;
+		}
+		break;
+
+	case _CR16:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{
+		case 0x20:
+			dst += sprintf( dst, ",DMAC0" );
+			break;
+		case 0x24:
+			dst += sprintf( dst, ",DMAC1" );
+			break;
+		case 0x28:
+			dst += sprintf( dst, ",DMAC2" );
+			break;
+		case 0x2c:
+			dst += sprintf( dst, ",DMAC3" );
+			break;
+		default:
+			dst += sprintf( dst, ",unknown" );
+			break;
+		}
+		break;
+
+	case _CR32:
+		imm = oprom[ pos++ ];
+		switch( imm )
+		{
+		case 0x00:
+			dst += sprintf( dst, ",DMAS0" );
+			break;
+		case 0x04:
+			dst += sprintf( dst, ",DMAS1" );
+			break;
+		case 0x08:
+			dst += sprintf( dst, ",DMAS2" );
+			break;
+		case 0x0c:
+			dst += sprintf( dst, ",DMAS3" );
+			break;
+		case 0x10:
+			dst += sprintf( dst, ",DMAD0" );
+			break;
+		case 0x14:
+			dst += sprintf( dst, ",DMAD1" ); 
+			break;
+		case 0x18:
+			dst += sprintf( dst, ",DMAD2" );
+			break;
+		case 0x1c:
+			dst += sprintf( dst, ",DMAD3" );
+			break;
+		default:
+			dst += sprintf( dst, ",unknown" );
+			break;
+		}
+		break;
+
+	case _D8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, ",0x%06x", ( pc + pos + (INT8)imm ) & 0xFFFFFF );
+		break;
+
+	case _D16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, ",0x%06x", ( pc + pos + (INT16)imm ) & 0xFFFFFF );
+		break;
+
+	case _F:
+		dst += sprintf( dst, ",F'" );
+		break;
+
+	case _I3:
+		dst += sprintf( dst, ",%d", op & 0x07 );
+		break;
+
+	case _I8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, ",0x%02x", imm );
+		break;
+
+	case _I16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, ",0x%04x", imm );
+		break;
+
+	case _I24:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		imm = imm | ( oprom[ pos++ ] << 16 );
+		dst += sprintf( dst, ",0x%06x", imm );
+		break;
+
+	case _I32:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		imm = imm | ( oprom[ pos++ ] << 16 );
+		imm = imm | ( oprom[ pos++ ] << 24 );
+		dst += sprintf( dst, ",0x%08x", imm );
+		break;
+
+	case _M:
+		switch( dasm->mnemonic )
+		{
+		case _CALL:
+		case _JP:
+		case _LDA:
+			dst += sprintf( dst, ",%s", buf );
+			break;
+		default:
+			dst += sprintf( dst, ",(%s)", buf );
+			break;
+		}
+		break;
+
+	case _M8:
+		imm = oprom[ pos++ ];
+		dst += sprintf( dst, ",(0x%02x)", imm );
+		break;
+
+	case _M16:
+		imm = oprom[ pos++ ];
+		imm = imm | ( oprom[ pos++ ] << 8 );
+		dst += sprintf( dst, ",(0x%04x)", imm );
+		break;
+
+	case _R:
+		dst += sprintf( dst, ",%s", buf );
+		break;
+
+	case _SR:
+		dst += sprintf( dst, ",SR" );
+		break;
+	}
+
+	return pos | flags | DASMFLAG_SUPPORTED;
+}
+
diff --git a/src/emu/cpu/tlcs900/tlcs900.c b/src/emu/cpu/tlcs900/tlcs900.c
new file mode 100644
index 00000000000..d088a426e7b
--- /dev/null
+++ b/src/emu/cpu/tlcs900/tlcs900.c
@@ -0,0 +1,1209 @@
+/*******************************************************************
+
+Toshiba TLCS-900/H emulation
+
+This code only supports the 900/H mode which is needed for Neogeo
+Pocket emulation. The 900 and 900/M modes are not supported yet.
+
+
+TODO:
+- review cycle counts
+- implement the remaining internal mcu features
+- at support for 900 and 900/M modes
+
+*******************************************************************/
+
+#include "debugger.h"
+#include "tlcs900.h"
+
+typedef struct _tlcs900_state tlcs900_state;
+struct _tlcs900_state
+{
+	const tlcs900_interface *intf;
+
+	devcb_resolved_write8	to1;
+	devcb_resolved_write8	to3;
+
+	/* registers */
+	PAIR	xwa[4];
+	PAIR	xbc[4];
+	PAIR	xde[4];
+	PAIR	xhl[4];
+	PAIR	xix;
+	PAIR	xiy;
+	PAIR	xiz;
+	PAIR	xssp;
+	PAIR	xnsp;
+	PAIR	pc;
+	PAIR	sr;
+	PAIR	f2;	/* f' */
+	/* DMA registers */
+	PAIR	dmas[4];
+	PAIR	dmad[4];
+	PAIR	dmac[4];
+	PAIR	dmam[4];
+
+	/* Internal timers, irqs, etc */
+	UINT8	reg[0x80];
+	UINT32	timer_pre;
+	UINT8	timer[6];
+	UINT8	tff1;
+	UINT8	tff3;
+	int		timer_change[4];
+
+	/* Current state of input levels */
+	int		level[TLCS900_NUM_INPUTS];
+	int		check_irqs;
+	int		ad_cycles_left;
+	int		nmi_state;
+
+	/* used during execution */
+	PAIR	dummy; /* for illegal register references */
+	UINT8	op;
+	PAIR	ea1, ea2;
+	PAIR	imm1, imm2;
+	int	cycles;
+	UINT8	*p1_reg8, *p2_reg8;
+	UINT16	*p1_reg16, *p2_reg16;
+	UINT32	*p1_reg32, *p2_reg32;
+
+	int halted;
+	int icount;
+	int regbank;
+	cpu_irq_callback irqcallback;
+	const device_config *device;
+	const address_space *program;
+};
+
+
+/* Internal register defines */
+#define P1			0x01
+#define P1CR		0x02
+#define P2			0x06
+#define P2FC		0x09
+#define P5			0x0d
+#define P5CR		0x10
+#define P5FC		0x11
+#define P6			0x12
+#define P7			0x13
+#define P6FC		0x15
+#define P7CR		0x16
+#define P7FC		0x17
+#define P8			0x18
+#define P9			0x19
+#define P8CR		0x1a
+#define P8FC		0x1b
+#define PA			0x1e
+#define PB			0x1f
+#define TRUN		0x20
+#define TREG0		0x22
+#define TREG1		0x23
+#define T01MOD		0x24
+#define TFFCR		0x25
+#define TREG2		0x26
+#define TREG3		0x27
+#define T23MOD		0x28
+#define TRDC		0x29
+#define PACR		0x2c
+#define PAFC		0x2d
+#define PBCR		0x2e
+#define PBFC		0x2f
+#define TREG4L		0x30
+#define TREG4H		0x31
+#define TREG5L		0x32
+#define TREG5H		0x33
+#define CAP1L		0x34
+#define CAP1H		0x35
+#define CAP2L		0x36
+#define CAP2H		0x37
+#define T4MOD		0x38
+#define T4FFCR		0x39
+#define T45CR		0x3a
+#define MSAR0		0x3c
+#define MAMR0		0x3d
+#define MSAR1		0x3e
+#define MAMR1		0x3f
+#define TREG6L		0x40
+#define TREG6H		0x41
+#define TREG7L		0x42
+#define TREG7H		0x43
+#define CAP3L		0x44
+#define CAP3H		0x45
+#define CAP4L		0x46
+#define CAP4H		0x47
+#define T5MOD		0x48
+#define T5FFCR		0x49
+#define PG0REG		0x4c
+#define PG1REG		0x4d
+#define PG01CR		0x4e
+#define SC0BUF		0x50
+#define SC0CR		0x51
+#define SC0MOD		0x52
+#define BR0CR		0x53
+#define SC1BUF		0x54
+#define SC1CR		0x55
+#define SC1MOD		0x56
+#define BR1CR		0x57
+#define ODE			0x58
+#define DREFCR		0x5a
+#define DMEMCR		0x5b
+#define MSAR2		0x5c
+#define MAMR2		0x5d
+#define MSAR3		0x5e
+#define MAMR3		0x5f
+#define ADREG0L		0x60
+#define ADREG0H		0x61
+#define ADREG1L		0x62
+#define ADREG1H		0x63
+#define ADREG2L		0x64
+#define ADREG2H		0x65
+#define ADREG3L		0x66
+#define ADREG3H		0x67
+#define B0CS		0x68
+#define B1CS		0x69
+#define B2CS		0x6a
+#define B3CS		0x6b
+#define BEXCS		0x6c
+#define ADMOD		0x6d
+#define WDMOD		0x6e
+#define WDCR		0x6f
+#define INTE0AD		0x70
+#define INTE45		0x71
+#define INTE67		0x72
+#define INTET10		0x73
+#define INTET32		0x74
+#define INTET54		0x75
+#define INTET76		0x76
+#define INTES0		0x77
+#define INTES1		0x78
+#define INTETC10	0x79
+#define INTETC32	0x7a
+#define IIMC		0x7b
+#define DMA0V		0x7c
+#define DMA1V		0x7d
+#define DMA2V		0x7e
+#define DMA3V		0x7f
+
+
+/* Flag defines */
+#define FLAG_CF		0x01
+#define FLAG_NF		0x02
+#define FLAG_VF		0x04
+#define FLAG_HF		0x10
+#define FLAG_ZF		0x40
+#define FLAG_SF		0x80
+
+
+#define RDMEM(addr)			memory_read_byte_8le( cpustate->program, addr )
+#define WRMEM(addr,data)	memory_write_byte_8le( cpustate->program, addr, data )
+#define RDOP()				RDMEM( cpustate->pc.d ); cpustate->pc.d++
+#define RDMEMW(addr)			( RDMEM(addr) | ( RDMEM(addr+1) << 8 ) )
+#define RDMEML(addr)			( RDMEMW(addr) | ( RDMEMW(addr+2) << 16 ) )
+#define WRMEMW(addr,data)		{ UINT16 dw = data; WRMEM(addr,dw & 0xff); WRMEM(addr+1,(dw >> 8 )); }
+#define WRMEML(addr,data)		{ UINT32 dl = data; WRMEMW(addr,dl); WRMEMW(addr+2,(dl >> 16)); }
+
+
+INLINE tlcs900_state *get_safe_token( const device_config *device )
+{
+	assert( device != NULL );
+	assert( device->token != NULL );
+	assert( device->type == CPU );
+	assert( cpu_get_type(device) == CPU_TLCS900H );
+
+	return (tlcs900_state *) device->token;
+}
+
+
+static CPU_INIT( tlcs900 )
+{
+	tlcs900_state *cpustate = get_safe_token(device);
+
+	cpustate->intf = (const tlcs900_interface *)device->static_config;
+	cpustate->irqcallback = irqcallback;
+	cpustate->device = device;
+	cpustate->program = memory_find_address_space( device, ADDRESS_SPACE_PROGRAM );
+
+	devcb_resolve_write8( &cpustate->to1, &cpustate->intf->to1, device );
+	devcb_resolve_write8( &cpustate->to3, &cpustate->intf->to3, device );
+
+	state_save_register_device_item_array( device, 0, cpustate->xwa );
+	state_save_register_device_item_array( device, 0, cpustate->xbc );
+	state_save_register_device_item_array( device, 0, cpustate->xde );
+	state_save_register_device_item_array( device, 0, cpustate->xhl );
+	state_save_register_device_item( device, 0, cpustate->xix );
+	state_save_register_device_item( device, 0, cpustate->xiy );
+	state_save_register_device_item( device, 0, cpustate->xiz );
+	state_save_register_device_item( device, 0, cpustate->xssp );
+	state_save_register_device_item( device, 0, cpustate->xnsp );
+	state_save_register_device_item( device, 0, cpustate->pc );
+	state_save_register_device_item( device, 0, cpustate->sr );
+	state_save_register_device_item( device, 0, cpustate->f2 );
+	state_save_register_device_item_array( device, 0, cpustate->dmas );
+	state_save_register_device_item_array( device, 0, cpustate->dmad );
+	state_save_register_device_item_array( device, 0, cpustate->dmac );
+	state_save_register_device_item_array( device, 0, cpustate->dmam );
+	state_save_register_device_item_array( device, 0, cpustate->reg );
+	state_save_register_device_item( device, 0, cpustate->timer_pre );
+	state_save_register_device_item_array( device, 0, cpustate->timer );
+	state_save_register_device_item( device, 0, cpustate->tff1 );
+	state_save_register_device_item( device, 0, cpustate->tff3 );
+	state_save_register_device_item_array( device, 0, cpustate->timer_change );
+	state_save_register_device_item_array( device, 0, cpustate->level );
+	state_save_register_device_item( device, 0, cpustate->check_irqs );
+	state_save_register_device_item( device, 0, cpustate->ad_cycles_left );
+	state_save_register_device_item( device, 0, cpustate->nmi_state );
+}
+
+
+static CPU_RESET( tlcs900 )
+{
+	tlcs900_state *cpustate = get_safe_token(device);
+	int i;
+
+	cpustate->pc.b.l = RDMEM( 0xFFFF00 );
+	cpustate->pc.b.h = RDMEM( 0xFFFF01 );
+	cpustate->pc.b.h2 = RDMEM( 0xFFFF02 );
+	cpustate->pc.b.h3 = 0;
+	/* system mode, iff set to 111, max mode, register bank 0 */
+	cpustate->sr.d = 0xF800;
+	cpustate->regbank = 0;
+	cpustate->xssp.d = 0x0100;
+	cpustate->halted = 0;
+	cpustate->check_irqs = 0;
+	cpustate->ad_cycles_left = 0;
+	cpustate->nmi_state = CLEAR_LINE;
+	cpustate->timer_pre = 0;
+	cpustate->timer_change[0] = 0;
+	cpustate->timer_change[1] = 0;
+	cpustate->timer_change[2] = 0;
+	cpustate->timer_change[3] = 0;
+
+	cpustate->reg[P1] = 0x00;
+	cpustate->reg[P1CR] = 0x00;
+	cpustate->reg[P2] = 0xff;
+	cpustate->reg[P2FC] = 0x00;
+	cpustate->reg[P5] = 0x3d;
+	cpustate->reg[P5CR] = 0x00;
+	cpustate->reg[P5FC] = 0x00;
+	cpustate->reg[P6] = 0x3b;
+	cpustate->reg[P6FC] = 0x00;
+	cpustate->reg[P7] = 0xff;
+	cpustate->reg[P7CR] = 0x00;
+	cpustate->reg[P7FC] = 0x00;
+	cpustate->reg[P8] = 0x3f;
+	cpustate->reg[P8CR] = 0x00;
+	cpustate->reg[P8FC] = 0x00;
+	cpustate->reg[PA] = 0x0f;
+	cpustate->reg[PACR] = 0x00;
+	cpustate->reg[PAFC] = 0x00;
+	cpustate->reg[PB] = 0xff;
+	cpustate->reg[PBCR] = 0x00;
+	cpustate->reg[PBFC] = 0x00;
+	cpustate->reg[MSAR0] = 0xff;
+	cpustate->reg[MSAR1] = 0xff;
+	cpustate->reg[MSAR2] = 0xff;
+	cpustate->reg[MSAR3] = 0xff;
+	cpustate->reg[MAMR0] = 0xff;
+	cpustate->reg[MAMR1] = 0xff;
+	cpustate->reg[MAMR2] = 0xff;
+	cpustate->reg[MAMR3] = 0xff;
+	cpustate->reg[DREFCR] = 0x00;
+	cpustate->reg[DMEMCR] = 0x80;
+	cpustate->reg[T01MOD] = 0x00;
+	cpustate->reg[T23MOD] = 0x00;
+	cpustate->reg[TFFCR] = 0x00;
+	cpustate->reg[TRUN] = 0x00;
+	cpustate->reg[TRDC] = 0x00;
+	cpustate->reg[T4MOD] = 0x20;
+	cpustate->reg[T4FFCR] = 0x00;
+	cpustate->reg[T5MOD] = 0x20;
+	cpustate->reg[T5FFCR] = 0x00;
+	cpustate->reg[T45CR] = 0x00;
+	cpustate->reg[PG01CR] = 0x00;
+	cpustate->reg[PG0REG] = 0x00;
+	cpustate->reg[PG1REG] = 0x00;
+	cpustate->reg[SC0MOD] = 0x00;
+	cpustate->reg[SC0CR] = 0x00;
+	cpustate->reg[BR0CR] = 0x00;
+	cpustate->reg[SC1MOD] = 0x00;
+	cpustate->reg[SC1CR] = 0x00;
+	cpustate->reg[BR1CR] = 0x00;
+	cpustate->reg[P8FC] = 0x00;
+	cpustate->reg[ODE] = 0x00;
+	cpustate->reg[ADMOD] = 0x00;
+	cpustate->reg[ADREG0L] = 0x3f;
+	cpustate->reg[ADREG1L] = 0x3f;
+	cpustate->reg[ADREG2L] = 0x3f;
+	cpustate->reg[ADREG3L] = 0x3f;
+	cpustate->reg[WDMOD] = 0x80;
+
+	for ( i = 0; i < TLCS900_NUM_INPUTS; i++ )
+	{
+		cpustate->level[i] = CLEAR_LINE;
+	}
+}
+
+
+static CPU_EXIT( tlcs900 )
+{
+}
+
+
+#include "900tbl.c"
+
+
+INLINE void tlcs900_process_hdma( tlcs900_state *cpustate, int channel, int vector )
+{
+	if ( vector == ( cpustate->reg[0x7c + channel] & 0x1f ) )
+	{
+		switch( cpustate->dmam[channel].b.l & 0x1f )
+		{
+		case 0x00:
+			WRMEM( cpustate->dmad[channel].d, RDMEM( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d += 1;
+			cpustate->cycles += 8;
+			break;
+		case 0x01:
+			WRMEMW( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d += 2;
+			cpustate->cycles += 8;
+			break;
+		case 0x02:
+			WRMEML( cpustate->dmad[channel].d, RDMEML( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d += 4;
+			cpustate->cycles += 12;
+			break;
+		case 0x04:
+			WRMEM( cpustate->dmad[channel].d, RDMEM( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d -= 1;
+			cpustate->cycles += 8;
+			break;
+		case 0x05:
+			WRMEMW( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d -= 2;
+			cpustate->cycles += 8;
+			break;
+		case 0x06:
+			WRMEML( cpustate->dmad[channel].d, RDMEML( cpustate->dmas[channel].d ) );
+			cpustate->dmad[channel].d -= 4;
+			cpustate->cycles += 12;
+			break;
+		case 0x08:
+			WRMEM( cpustate->dmad[channel].d, RDMEM( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d += 1;
+			cpustate->cycles += 8;
+			break;
+		case 0x09:
+			WRMEMW( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d += 2;
+			cpustate->cycles += 8;
+			break;
+		case 0x0a:
+			WRMEML( cpustate->dmad[channel].d, RDMEML( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d += 4;
+			cpustate->cycles += 12;
+			break;
+		case 0x0c:
+			WRMEM( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d -= 1;
+			cpustate->cycles += 8;
+			break;
+		case 0x0d:
+			WRMEMW( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d -= 2;
+			cpustate->cycles += 8;
+			break;
+		case 0x0e:
+			WRMEML( cpustate->dmad[channel].d, RDMEML( cpustate->dmas[channel].d ) );
+			cpustate->dmas[channel].d -= 4;
+			cpustate->cycles += 12;
+			break;
+		case 0x10:
+			WRMEM( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->cycles += 8;
+			break;
+		case 0x11:
+			WRMEMW( cpustate->dmad[channel].d, RDMEMW( cpustate->dmas[channel].d ) );
+			cpustate->cycles += 8;
+			break;
+		case 0x12:
+			WRMEML( cpustate->dmad[channel].d, RDMEML( cpustate->dmas[channel].d ) );
+			cpustate->cycles += 12;
+			break;
+		case 0x14:
+			cpustate->dmas[channel].d += 1;
+			cpustate->cycles += 5;
+			break;
+		}
+
+		cpustate->dmac[channel].w.l -= 1;
+
+		if ( cpustate->dmac[channel].w.l == 0 )
+		{
+			cpustate->reg[0x7c + channel] = 0;
+			switch( channel )
+			{
+			case 0:
+				cpustate->reg[INTETC10] |= 0x08;
+				break;
+			case 1:
+				cpustate->reg[INTETC10] |= 0x80;
+				break;
+			case 2:
+				cpustate->reg[INTETC32] |= 0x08;
+				break;
+			case 3:
+				cpustate->reg[INTETC32] |= 0x80;
+				break;
+			}
+		}
+	}
+}
+
+
+INLINE void tlcs900_check_irqs( tlcs900_state *cpustate )
+{
+#define NUM_MASKABLE_IRQS	22
+	static const struct {
+		UINT8 reg;
+		UINT8 iff;
+		UINT8 vector;
+	} irq_vector_map[NUM_MASKABLE_IRQS] =
+	{
+		{ INTETC32, 0x80, 0x80 },	/* INTTC3 */
+		{ INTETC32, 0x08, 0x7c },	/* INTTC2 */
+		{ INTETC10, 0x80, 0x78 },	/* INTTC1 */
+		{ INTETC10, 0x08, 0x74 },	/* INTTC0 */
+		{ INTE0AD, 0x80, 0x70 },	/* INTAD */
+		{ INTES1, 0x80, 0x6c },		/* INTTX1 */
+		{ INTES1, 0x08, 0x68 },		/* INTRX1 */
+		{ INTES0, 0x80, 0x64 },		/* INTTX0 */
+		{ INTES0, 0x08, 0x60 },		/* INTRX0 */
+		{ INTET76, 0x80, 0x5c },	/* INTTR7 */
+		{ INTET76, 0x08, 0x58 },	/* INTTR6 */
+		{ INTET54, 0x80, 0x54 },	/* INTTR5 */
+		{ INTET54, 0x08, 0x50 },	/* INTTR4 */
+		{ INTET32, 0x80, 0x4c },	/* INTT3 */
+		{ INTET32, 0x08, 0x48 },	/* INTT2 */
+		{ INTET10, 0x80, 0x44 },	/* INTT1 */
+		{ INTET10, 0x08, 0x40 },	/* INTT0 */
+									/* 0x3c - reserved */
+		{ INTE67, 0x80, 0x38 },		/* INT7 */
+		{ INTE67, 0x08, 0x34 },		/* INT6 */
+		{ INTE45, 0x80, 0x30 },		/* INT5 */
+		{ INTE45, 0x08, 0x2c },		/* INT4 */
+		{ INTE0AD, 0x08, 0x28 }		/* INT0 */
+	};
+	int irq_vectors[9] = { -1, -1, -1, -1, -1, -1, -1, -1, -1 };
+	int irq = -1;
+	int i;
+
+	/* Check for NMI */
+	if ( cpustate->nmi_state == ASSERT_LINE )
+	{
+		cpustate->xssp.d -= 4;
+		WRMEML( cpustate->xssp.d, cpustate->pc.d );
+		cpustate->xssp.d -= 2;
+		WRMEMW( cpustate->xssp.d, cpustate->sr.w.l );
+		cpustate->pc.d = RDMEML( 0xffff00 + 0x20 );
+		cpustate->cycles += 18;
+
+		cpustate->halted = 0;
+
+		cpustate->nmi_state = CLEAR_LINE;
+
+		return;
+	}
+
+	/* Check regular irqs */
+	for( i = 0; i < NUM_MASKABLE_IRQS; i++ )
+	{
+		if ( cpustate->reg[irq_vector_map[i].reg] & irq_vector_map[i].iff )
+		{
+			switch( irq_vector_map[i].iff )
+			{
+			case 0x80:
+				irq_vectors[ ( cpustate->reg[ irq_vector_map[i].reg ] >> 4 ) & 0x07 ] = i;
+				break;
+			case 0x08:
+				irq_vectors[ cpustate->reg[ irq_vector_map[i].reg ] & 0x07 ] = i;
+				break;
+			}
+		}
+	}
+
+	/* Check highest allowed priority irq */
+	for ( i = MAX( 1, ( ( cpustate->sr.b.h & 0x70 ) >> 4 ) ); i < 7; i++ )
+	{
+		if ( irq_vectors[i] >= 0 )
+		{
+			irq = irq_vectors[i];
+		}
+	}
+
+	/* Take irq */
+	if ( irq >= 0 )
+	{
+		UINT8 vector = irq_vector_map[irq].vector;
+
+		cpustate->xssp.d -= 4;
+		WRMEML( cpustate->xssp.d, cpustate->pc.d );
+		cpustate->xssp.d -= 2;
+		WRMEMW( cpustate->xssp.d, cpustate->sr.w.l );
+		cpustate->pc.d = RDMEML( 0xffff00 + vector );
+		cpustate->cycles += 18;
+
+		cpustate->halted = 0;
+
+		/* Clear taken IRQ */
+		cpustate->reg[ irq_vector_map[irq].reg ] &= ~ irq_vector_map[irq].iff;
+
+		/* Check if any HDMA actions should be performed */
+		if ( vector >= 0x28 && vector != 0x3C && vector < 0x74 )
+		{
+			tlcs900_process_hdma( cpustate, 0, vector >> 2 );
+			tlcs900_process_hdma( cpustate, 1, vector >> 2 );
+			tlcs900_process_hdma( cpustate, 2, vector >> 2 );
+			tlcs900_process_hdma( cpustate, 3, vector >> 2 );
+		}
+	}
+}
+
+
+INLINE void tlcs900_handle_ad( tlcs900_state *cpustate )
+{
+	if ( cpustate->ad_cycles_left > 0 )
+	{
+		cpustate->ad_cycles_left -= cpustate->cycles;
+		if ( cpustate->ad_cycles_left <= 0 )
+		{
+			/* Store A/D converted value */
+			switch( cpustate->reg[ADMOD] & 0x03 )
+			{
+			case 0x00:	/* AN0 */
+				cpustate->reg[ADREG0L] |= 0xc0;
+				cpustate->reg[ADREG0H] = 0xff;
+				break;
+			case 0x01:	/* AN1 */
+			case 0x02:	/* AN2 */
+			case 0x03:	/* AN3 */
+				break;
+			}
+
+			/* Clear BUSY flag, set END flag */
+			cpustate->reg[ADMOD] &= ~ 0x40;
+			cpustate->reg[ADMOD] |= 0x80;
+
+			cpustate->reg[INTE0AD] |= 0x80;
+			cpustate->check_irqs = 1;
+		}
+	}
+}
+
+
+enum ff_change
+{
+	FF_CLEAR,
+	FF_SET,
+	FF_INVERT
+};
+
+
+INLINE void tlcs900_change_tff( tlcs900_state *cpustate, int which, int change )
+{
+	switch( which )
+	{
+	case 1:
+		switch( change )
+		{
+		case FF_CLEAR:
+			cpustate->tff1 = 0;
+			break;
+		case FF_SET:
+			cpustate->tff1 = 1;
+			break;
+		case FF_INVERT:
+			cpustate->tff1 ^= 1;
+			break;
+		}
+		if ( cpustate->to1.write != NULL )
+			devcb_call_write8( &cpustate->to1, 0, cpustate->tff1 );
+		break;
+
+	case 3:
+		switch( change )
+		{
+		case FF_CLEAR:
+			cpustate->tff3 = 0;
+			break;
+		case FF_SET:
+			cpustate->tff3 = 1;
+			break;
+		case FF_INVERT:
+			cpustate->tff3 ^= 1;
+			break;
+		}
+		if ( cpustate->to3.write != NULL )
+			devcb_call_write8( &cpustate->to3, 0, cpustate->tff3 );
+		break;
+	}
+}
+
+
+INLINE void tlcs900_handle_timers( tlcs900_state *cpustate )
+{
+	UINT32	old_pre = cpustate->timer_pre;
+
+	/* Is the pre-scaler active */
+	if ( cpustate->reg[TRUN] & 0x80 )
+		cpustate->timer_pre += cpustate->cycles;
+
+	/* Timer 0 */
+	if ( cpustate->reg[TRUN] & 0x01 )
+	{
+		switch( cpustate->reg[T01MOD] & 0x03 )
+		{
+		case 0x00:	/* TIO */
+			break;
+		case 0x01:	/* T1 */
+			cpustate->timer_change[0] += ( cpustate->timer_pre >> 7 ) - ( old_pre >> 7 );
+			break;
+		case 0x02:	/* T4 */
+			cpustate->timer_change[0] += ( cpustate->timer_pre >> 9 ) - ( old_pre >> 9 );
+			break;
+		case 0x03:	/* T16 */
+			cpustate->timer_change[0] += ( cpustate->timer_pre >> 11 ) - ( old_pre >> 11 );
+			break;
+		}
+
+		for( ; cpustate->timer_change[0] > 0; cpustate->timer_change[0]-- )
+		{
+			cpustate->timer[0] += 1;
+			if ( cpustate->timer[0] == cpustate->reg[TREG0] )
+			{
+				if ( ( cpustate->reg[T01MOD] & 0x0c ) == 0x00 )
+				{
+					cpustate->timer_change[1] += 1;
+				}
+
+				/* In 16bit timer mode the timer should not be reset */
+				if ( ( cpustate->reg[T01MOD] & 0xc0 ) != 0x40 )
+				{
+					cpustate->timer[0] = 0;
+					cpustate->reg[INTET10] |= 0x08;
+				}
+			}
+		}
+	}
+
+	/* Timer 1 */
+	if ( cpustate->reg[TRUN] & 0x02 )
+	{
+		switch( ( cpustate->reg[T01MOD] >> 2 ) & 0x03 )
+		{
+		case 0x00:	/* TO0TRG */
+			break;
+		case 0x01:	/* T1 */
+			cpustate->timer_change[1] += ( cpustate->timer_pre >> 7 ) - ( old_pre >> 7 );
+			break;
+		case 0x02:	/* T16 */
+			cpustate->timer_change[1] += ( cpustate->timer_pre >> 11 ) - ( old_pre >> 11 );
+			break;
+		case 0x03:	/* T256 */
+			cpustate->timer_change[1] += ( cpustate->timer_pre >> 15 ) - ( old_pre >> 15 );
+			break;
+		}
+
+		for( ; cpustate->timer_change[1] > 0; cpustate->timer_change[1]-- )
+		{
+			cpustate->timer[1] += 1;
+			if ( cpustate->timer[1] == cpustate->reg[TREG1] )
+			{
+				cpustate->timer[1] = 0;
+				cpustate->reg[INTET10] |= 0x80;
+
+				if ( cpustate->reg[TFFCR] & 0x02 )
+				{
+					tlcs900_change_tff( cpustate, 1, FF_INVERT );
+				}
+
+				/* In 16bit timer mode also reset timer 0 */
+				if ( ( cpustate->reg[T01MOD] & 0xc0 ) == 0x40 )
+				{
+					cpustate->timer[0] = 0;
+				}
+			}
+		}
+	}
+
+	/* Timer 2 */
+	if ( cpustate->reg[TRUN] & 0x04 )
+	{
+		switch( cpustate->reg[T23MOD] & 0x03 )
+		{
+		case 0x00:	/* invalid */
+		case 0x01:	/* T1 */
+			cpustate->timer_change[2] += ( cpustate->timer_pre >> 7 ) - ( old_pre >> 7 );
+			break;
+		case 0x02:	/* T4 */
+			cpustate->timer_change[2] += ( cpustate->timer_pre >> 9 ) - ( old_pre >> 9 );
+			break;
+		case 0x03:	/* T16 */
+			cpustate->timer_change[2] += ( cpustate->timer_pre >> 11 ) - ( old_pre >> 11 );
+			break;
+		}
+
+		for( ; cpustate->timer_change[2] > 0; cpustate->timer_change[2]-- )
+		{
+			cpustate->timer[2] += 1;
+			if ( cpustate->timer[2] == cpustate->reg[TREG2] )
+			{
+				if ( ( cpustate->reg[T23MOD] & 0x0c ) == 0x00 )
+				{
+					cpustate->timer_change[3] += 1;
+				}
+
+				/* In 16bit timer mode the timer should not be reset */
+				if ( ( cpustate->reg[T23MOD] & 0xc0 ) != 0x40 )
+				{
+					cpustate->timer[2] = 0;
+					cpustate->reg[INTET32] |= 0x08;
+				}
+			}
+		}
+	}
+
+	/* Timer 3 */
+	if ( cpustate->reg[TRUN] & 0x08 )
+	{
+		switch( ( cpustate->reg[T23MOD] >> 2 ) & 0x03 )
+		{
+		case 0x00:	/* TO2TRG */
+			break;
+		case 0x01:	/* T1 */
+			cpustate->timer_change[3] += ( cpustate->timer_pre >> 7 ) - ( old_pre >> 7 );
+			break;
+		case 0x02:	/* T16 */
+			cpustate->timer_change[3] += ( cpustate->timer_pre >> 11 ) - ( old_pre >> 11 );
+			break;
+		case 0x03:	/* T256 */
+			cpustate->timer_change[3] += ( cpustate->timer_pre >> 15 ) - ( old_pre >> 15 );
+			break;
+		}
+
+		for( ; cpustate->timer_change[3] > 0; cpustate->timer_change[3]-- )
+		{
+			cpustate->timer[3] += 1;
+			if ( cpustate->timer[3] == cpustate->reg[TREG3] )
+			{
+				cpustate->timer[3] = 0;
+				cpustate->reg[INTET32] |= 0x80;
+
+				if ( cpustate->reg[TFFCR] & 0x20 )
+				{
+					tlcs900_change_tff( cpustate, 3, FF_INVERT );
+				}
+
+				/* In 16bit timer mode also reset timer 2 */
+				if ( ( cpustate->reg[T23MOD] & 0xc0 ) == 0x40 )
+				{
+					cpustate->timer[2] = 0;
+				}
+			}
+		}
+	}
+
+	cpustate->timer_pre &= 0xffffff;
+}
+
+
+static CPU_EXECUTE( tlcs900 )
+{
+	tlcs900_state *cpustate = get_safe_token(device);
+
+	cpustate->icount = cycles;
+
+	do
+	{
+		const tlcs900inst *inst;
+
+		cpustate->cycles = 0;
+
+		if ( cpustate->check_irqs )
+		{
+			tlcs900_check_irqs( cpustate );
+			cpustate->check_irqs = 0;
+		}
+
+		debugger_instruction_hook( device, cpustate->pc.d );
+
+		if ( cpustate->halted )
+		{
+			cpustate->cycles += 8;
+		}
+		else
+		{
+			cpustate->op = RDOP();
+			inst = &mnemonic[cpustate->op];
+			prepare_operands( cpustate, inst );
+
+			/* Execute the instruction */
+			inst->opfunc( cpustate );
+			cpustate->cycles += inst->cycles;
+		}
+
+		tlcs900_handle_ad( cpustate );
+
+		tlcs900_handle_timers( cpustate );
+
+		cpustate->icount -= cpustate->cycles;
+	} while ( cpustate->icount > 0 );
+
+	return cycles - cpustate->icount;
+}
+
+
+static void tlcs900_input_level_change( tlcs900_state *cpustate, int input, int level )
+{
+	switch( input )
+	{
+	case INPUT_LINE_NMI:
+	case TLCS900_NMI:
+		if ( cpustate->level[TLCS900_NMI] == CLEAR_LINE && level == ASSERT_LINE )
+		{
+			cpustate->nmi_state = level;
+		}
+		cpustate->level[TLCS900_NMI] = level;
+		break;
+
+	case TLCS900_INTWD:
+		break;
+
+	case TLCS900_INT0:
+		/* Is INT0 functionality enabled? */
+		if ( cpustate->reg[IIMC] & 0x04 )
+		{
+			if ( cpustate->reg[IIMC] & 0x02 )
+			{
+				/* Rising edge detect */
+				if ( cpustate->level[TLCS900_INT0] == CLEAR_LINE && level == ASSERT_LINE )
+				{
+					/* Leave HALT state */
+					cpustate->halted = 0;
+					cpustate->reg[INTE0AD] |= 0x08;
+				}
+			}
+			else
+			{
+				/* Level detect */
+				if ( level == ASSERT_LINE )
+					cpustate->reg[INTE0AD] |= 0x08;
+				else
+					cpustate->reg[INTE0AD] &= ~ 0x08;
+			}
+		}
+		cpustate->level[TLCS900_INT0] = level;
+		break;
+
+	case TLCS900_INT4:
+		if ( ! ( cpustate->reg[PBCR] & 0x01 ) )
+		{
+			if ( cpustate->level[TLCS900_INT4] == CLEAR_LINE && level == ASSERT_LINE )
+			{
+				cpustate->reg[INTE45] |= 0x08;
+			}
+		}
+		cpustate->level[TLCS900_INT4] = level;
+		break;
+
+	case TLCS900_INT5:
+		if ( ! ( cpustate->reg[PBCR] & 0x02 ) )
+		{
+			if ( cpustate->level[TLCS900_INT5] == CLEAR_LINE && level == ASSERT_LINE )
+			{
+				cpustate->reg[INTE45] |= 0x80;
+			}
+		}
+		cpustate->level[TLCS900_INT5] = level;
+		break;
+
+	case TLCS900_TIO:	/* External timer input for timer 0 */
+		if ( ( cpustate->reg[TRUN] & 0x01 ) && ( cpustate->reg[T01MOD] & 0x03 ) == 0x00 )
+		{
+			if ( cpustate->level[TLCS900_TIO] == CLEAR_LINE && level == ASSERT_LINE )
+			{
+				cpustate->timer_change[0] += 1;
+			}
+		}
+		cpustate->level[TLCS900_TIO] = level;
+		break;
+	}
+	cpustate->check_irqs = 1;
+}
+
+
+static READ8_HANDLER( tlcs900_internal_r )
+{
+	tlcs900_state *cpustate = get_safe_token( space->cpu );
+
+	return cpustate->reg[ offset ];
+}
+
+
+static WRITE8_HANDLER( tlcs900_internal_w )
+{
+	tlcs900_state *cpustate = get_safe_token( space->cpu );
+
+	switch ( offset )
+	{
+	case TRUN:
+		if ( ! ( data & 0x01 ) )
+		{
+			cpustate->timer[0] = 0;
+			cpustate->timer_change[0] = 0;
+		}
+		if ( ! ( data & 0x02 ) )
+		{
+			cpustate->timer[1] = 0;
+			cpustate->timer_change[1] = 0;
+		}
+		if ( ! ( data & 0x04 ) )
+		{
+			cpustate->timer[2] = 0;
+			cpustate->timer_change[2] = 0;
+		}
+		if ( ! ( data & 0x08 ) )
+		{
+			cpustate->timer[3] = 0;
+			cpustate->timer_change[3] = 0;
+		}
+		if ( ! ( data & 0x10 ) )
+			cpustate->timer[4] = 0;
+		if ( ! ( data & 0x20 ) )
+			cpustate->timer[5] = 0;
+		break;
+
+	case TFFCR:
+		switch( data & 0x0c )
+		{
+		case 0x00:
+			tlcs900_change_tff( cpustate, 1, FF_INVERT );
+			break;
+		case 0x04:
+			tlcs900_change_tff( cpustate, 1, FF_SET );
+			break;
+		case 0x08:
+			tlcs900_change_tff( cpustate, 1, FF_CLEAR );
+			break;
+		}
+		switch( data & 0xc0 )
+		{
+		case 0x00:
+			tlcs900_change_tff( cpustate, 3, FF_INVERT );
+			break;
+		case 0x40:
+			tlcs900_change_tff( cpustate, 3, FF_SET );
+			break;
+		case 0x80:
+			tlcs900_change_tff( cpustate, 3, FF_CLEAR );
+			break;
+		}
+		break;
+	case MSAR0:
+	case MAMR0:
+	case MSAR1:
+	case MAMR1:
+		break;
+
+	case ADMOD:
+		/* Preserve read-only bits */
+		data = ( cpustate->reg[ADMOD] & 0xc0 ) | ( data & 0x3f );
+
+		/* Check for A/D request start */
+		if ( data & 0x04 )
+		{
+			data &= ~0x04;
+			data |= 0x40;
+			cpustate->ad_cycles_left = ( data & 0x08 ) ? 640 : 320;
+		}
+		break;
+
+	case WDMOD:
+	case WDCR:
+		break;
+
+	case INTE0AD:
+	case INTE45:
+	case INTE67:
+	case INTET10:
+	case INTET32:
+	case INTET54:
+	case INTET76:
+	case INTES0:
+	case INTES1:
+	case INTETC10:
+	case INTETC32:
+		if ( data & 0x80 )
+			data = ( data & 0x7f ) | ( cpustate->reg[offset] & 0x80 );
+		if ( data & 0x08 )
+			data = ( data & 0xf7 ) | ( cpustate->reg[offset] & 0x08 );
+		break;
+
+	case IIMC:
+		break;
+
+	default:
+		break;
+	}
+
+	cpustate->check_irqs = 1;
+	cpustate->reg[ offset ] = data;
+}
+
+
+static ADDRESS_MAP_START( tlcs900_mem, ADDRESS_SPACE_PROGRAM, 8 )
+	AM_RANGE( 0x000000, 0x00007f ) AM_READWRITE( tlcs900_internal_r, tlcs900_internal_w )
+ADDRESS_MAP_END
+
+
+static CPU_SET_INFO( tlcs900 )
+{
+	tlcs900_state *cpustate = get_safe_token( device );
+
+	switch ( state )
+	{
+	case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_NMI:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INTWD:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT0:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT4:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT5:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_TIO:
+		tlcs900_input_level_change( cpustate, state - CPUINFO_INT_INPUT_STATE, info->i ); break;
+	}
+}
+
+
+CPU_GET_INFO( tlcs900h )
+{
+	tlcs900_state *cpustate = ( device != NULL && device->token != NULL ) ? get_safe_token(device) : NULL;
+
+	switch( state )
+	{
+	case CPUINFO_INT_CONTEXT_SIZE:					info->i = sizeof(tlcs900_state); break;
+	case CPUINFO_INT_ENDIANNESS:					info->i = ENDIANNESS_LITTLE; break;
+	case CPUINFO_INT_CLOCK_MULTIPLIER:				info->i = 1; break;
+	case CPUINFO_INT_CLOCK_DIVIDER:					info->i = 1; break;
+	case CPUINFO_INT_MIN_INSTRUCTION_BYTES:			info->i = 1; break;
+	case CPUINFO_INT_MAX_INSTRUCTION_BYTES:			info->i = 7; break;	/* FIXME */
+	case CPUINFO_INT_MIN_CYCLES:					info->i = 1; break; /* FIXME */
+	case CPUINFO_INT_MAX_CYCLES:					info->i = 1; break; /* FIXME */
+	case CPUINFO_INT_INPUT_LINES:					info->i = 1; break;
+
+	case CPUINFO_INT_DATABUS_WIDTH_PROGRAM:			info->i = 8; break;
+	case CPUINFO_INT_ADDRBUS_WIDTH_PROGRAM:			info->i = 24; break;
+	case CPUINFO_INT_ADDRBUS_SHIFT_PROGRAM:			info->i = 0; break;
+
+	case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI:
+	case CPUINFO_INT_INPUT_STATE + TLCS900_NMI:		info->i = cpustate->level[TLCS900_NMI]; break;
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INTWD:	info->i = cpustate->level[TLCS900_INTWD]; break;
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT0:	info->i = cpustate->level[TLCS900_INT0]; break;
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT4:	info->i = cpustate->level[TLCS900_INT4]; break;
+	case CPUINFO_INT_INPUT_STATE + TLCS900_INT5:	info->i = cpustate->level[TLCS900_INT5]; break;
+	case CPUINFO_INT_INPUT_STATE + TLCS900_TIO:		info->i = cpustate->level[TLCS900_TIO]; break;
+
+	case CPUINFO_INT_PC:							info->i = cpustate->pc.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_PC:			info->i = cpustate->pc.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_SR:			info->i = cpustate->sr.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XWA0:		info->i = cpustate->xwa[0].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XBC0:		info->i = cpustate->xbc[0].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XDE0:		info->i = cpustate->xde[0].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XHL0:		info->i = cpustate->xhl[0].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XWA1:		info->i = cpustate->xwa[1].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XBC1:		info->i = cpustate->xbc[1].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XDE1:		info->i = cpustate->xde[1].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XHL1:		info->i = cpustate->xhl[1].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XWA2:		info->i = cpustate->xwa[2].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XBC2:		info->i = cpustate->xbc[2].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XDE2:		info->i = cpustate->xde[2].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XHL2:		info->i = cpustate->xhl[2].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XWA3:		info->i = cpustate->xwa[3].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XBC3:		info->i = cpustate->xbc[3].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XDE3:		info->i = cpustate->xde[3].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XHL3:		info->i = cpustate->xhl[3].d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XIX:		info->i = cpustate->xix.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XIY:		info->i = cpustate->xiy.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XIZ:		info->i = cpustate->xiz.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XNSP:		info->i = cpustate->xnsp.d; break;
+	case CPUINFO_INT_REGISTER + TLCS900_XSSP:		info->i = cpustate->xssp.d; break;
+
+	case CPUINFO_FCT_SET_INFO:						info->setinfo = CPU_SET_INFO_NAME(tlcs900); break;
+	case CPUINFO_FCT_INIT:							info->init = CPU_INIT_NAME(tlcs900); break;
+	case CPUINFO_FCT_RESET:							info->reset = CPU_RESET_NAME(tlcs900); break;
+	case CPUINFO_FCT_EXIT:							info->exit = CPU_EXIT_NAME(tlcs900); break;
+	case CPUINFO_FCT_EXECUTE:						info->execute = CPU_EXECUTE_NAME(tlcs900); break;
+	case CPUINFO_FCT_DISASSEMBLE:					info->disassemble = CPU_DISASSEMBLE_NAME(tlcs900); break;
+	case CPUINFO_PTR_INSTRUCTION_COUNTER:			info->icount = &cpustate->icount; break;
+	case CPUINFO_PTR_INTERNAL_MEMORY_MAP:			info->internal_map8 = ADDRESS_MAP_NAME(tlcs900_mem); break;
+
+	case CPUINFO_STR_REGISTER + TLCS900_PC:			sprintf( info->s, "PC:%08x", cpustate->pc.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_SR:			sprintf( info->s, "SR:%c%d%c%d%c%c%c%c%c%c%c%c",
+														cpustate->sr.w.l & 0x8000 ? 'S' : 'U',
+														( cpustate->sr.w.l & 0x7000 ) >> 12,
+														cpustate->sr.w.l & 0x0800 ? 'M' : 'N',
+														( cpustate->sr.w.l & 0x0700 ) >> 8,
+														cpustate->sr.w.l & 0x0080 ? 'S' : '.',
+														cpustate->sr.w.l & 0x0040 ? 'Z' : '.',
+														cpustate->sr.w.l & 0x0020 ? '1' : '.',
+														cpustate->sr.w.l & 0x0010 ? 'H' : '.',
+														cpustate->sr.w.l & 0x0008 ? '1' : '.',
+														cpustate->sr.w.l & 0x0004 ? 'V' : '.',
+														cpustate->sr.w.l & 0x0002 ? 'N' : '.',
+														cpustate->sr.w.l & 0x0001 ? 'C' : '.' );
+													break;
+	case CPUINFO_STR_REGISTER + TLCS900_XWA0:		sprintf( info->s, "XWA0:%08x", cpustate->xwa[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XBC0:		sprintf( info->s, "XBC0:%08x", cpustate->xbc[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XDE0:		sprintf( info->s, "XDE0:%08x", cpustate->xde[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XHL0:		sprintf( info->s, "XHL0:%08x", cpustate->xhl[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XWA1:		sprintf( info->s, "XWA1:%08x", cpustate->xwa[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XBC1:		sprintf( info->s, "XBC1:%08x", cpustate->xbc[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XDE1:		sprintf( info->s, "XDE1:%08x", cpustate->xde[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XHL1:		sprintf( info->s, "XHL1:%08x", cpustate->xhl[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XWA2:		sprintf( info->s, "XWA2:%08x", cpustate->xwa[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XBC2:		sprintf( info->s, "XBC2:%08x", cpustate->xbc[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XDE2:		sprintf( info->s, "XDE2:%08x", cpustate->xde[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XHL2:		sprintf( info->s, "XHL2:%08x", cpustate->xhl[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XWA3:		sprintf( info->s, "XWA3:%08x", cpustate->xwa[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XBC3:		sprintf( info->s, "XBC3:%08x", cpustate->xbc[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XDE3:		sprintf( info->s, "XDE3:%08x", cpustate->xde[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XHL3:		sprintf( info->s, "XHL3:%08x", cpustate->xhl[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XIX:		sprintf( info->s, "XIX:%08x", cpustate->xix.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XIY:		sprintf( info->s, "XIY:%08x", cpustate->xiy.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XIZ:		sprintf( info->s, "XIZ:%08x", cpustate->xiz.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XNSP:		sprintf( info->s, "XNSP:%08x", cpustate->xnsp.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_XSSP:		sprintf( info->s, "XSSP:%08x", cpustate->xssp.d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAS0:		sprintf( info->s, "DMAS0:%08x", cpustate->dmas[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAD0:		sprintf( info->s, "DMAD0:%08x", cpustate->dmad[0].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAC0:		sprintf( info->s, "DMAC0:%04x", cpustate->dmac[0].w.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAM0:		sprintf( info->s, "DMAM0:%02x", cpustate->dmam[0].b.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAS1:		sprintf( info->s, "DMAS0:%08x", cpustate->dmas[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAD1:		sprintf( info->s, "DMAD0:%08x", cpustate->dmad[1].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAC1:		sprintf( info->s, "DMAC0:%04x", cpustate->dmac[1].w.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAM1:		sprintf( info->s, "DMAM0:%02x", cpustate->dmam[1].b.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAS2:		sprintf( info->s, "DMAS0:%08x", cpustate->dmas[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAD2:		sprintf( info->s, "DMAD0:%08x", cpustate->dmad[2].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAC2:		sprintf( info->s, "DMAC0:%04x", cpustate->dmac[2].w.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAM2:		sprintf( info->s, "DMAM0:%02x", cpustate->dmam[2].b.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAS3:		sprintf( info->s, "DMAS0:%08x", cpustate->dmas[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAD3:		sprintf( info->s, "DMAD0:%08x", cpustate->dmad[3].d ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAC3:		sprintf( info->s, "DMAC0:%04x", cpustate->dmac[3].w.l ); break;
+	case CPUINFO_STR_REGISTER + TLCS900_DMAM3:		sprintf( info->s, "DMAM0:%02x", cpustate->dmam[3].b.l ); break;
+
+	case CPUINFO_STR_NAME:							strcpy( info->s, "TLCS-900/H" ); break;
+	case CPUINFO_STR_CORE_FAMILY:					strcpy( info->s, "Toshiba TLCS-900" ); break;
+	case CPUINFO_STR_CORE_VERSION:					strcpy( info->s, "0.1" ); break;
+	case CPUINFO_STR_CORE_FILE:						strcpy( info->s, __FILE__ ); break;
+	case CPUINFO_STR_CORE_CREDITS:					strcpy( info->s, "Copyright Wilbert Pol" ); break;
+	}
+}
+
diff --git a/src/emu/cpu/tlcs900/tlcs900.h b/src/emu/cpu/tlcs900/tlcs900.h
new file mode 100644
index 00000000000..e83aa2b3745
--- /dev/null
+++ b/src/emu/cpu/tlcs900/tlcs900.h
@@ -0,0 +1,49 @@
+#ifndef __TLCS900_H__
+#define __TLCS900_H__
+
+#include "cpuintrf.h"
+#include "devcb.h"
+
+
+enum tlcs900_inputs
+{
+	TLCS900_NMI=0,
+	TLCS900_INTWD,
+	TLCS900_INT0,
+	TLCS900_INTAD,
+	TLCS900_INT4,
+	TLCS900_INT5,
+	TLCS900_TIO,
+	TLCS900_NUM_INPUTS
+};
+
+
+enum
+{
+	TLCS900_PC=1, TLCS900_SR,
+	TLCS900_XWA0, TLCS900_XBC0, TLCS900_XDE0, TLCS900_XHL0,
+	TLCS900_XWA1, TLCS900_XBC1, TLCS900_XDE1, TLCS900_XHL1,
+	TLCS900_XWA2, TLCS900_XBC2, TLCS900_XDE2, TLCS900_XHL2,
+	TLCS900_XWA3, TLCS900_XBC3, TLCS900_XDE3, TLCS900_XHL3,
+	TLCS900_XIX, TLCS900_XIY, TLCS900_XIZ, TLCS900_XNSP, TLCS900_XSSP,
+	TLCS900_DMAS0, TLCS900_DMAS1, TLCS900_DMAS2, TLCS900_DMAS3,
+	TLCS900_DMAD0, TLCS900_DMAD1, TLCS900_DMAD2, TLCS900_DMAD3,
+	TLCS900_DMAC0, TLCS900_DMAC1, TLCS900_DMAC2, TLCS900_DMAC3,
+	TLCS900_DMAM0, TLCS900_DMAM1, TLCS900_DMAM2, TLCS900_DMAM3
+};
+
+
+typedef struct _tlcs900_interface tlcs900_interface;
+struct _tlcs900_interface
+{
+	devcb_write8	to1;
+	devcb_write8	to3;
+};
+
+
+extern CPU_GET_INFO( tlcs900h );
+#define CPU_TLCS900H CPU_GET_INFO_NAME( tlcs900h )
+
+extern CPU_DISASSEMBLE( tlcs900 );
+
+#endif
diff --git a/src/mame/mame.mak b/src/mame/mame.mak
index d2b74080824..cce3aad1a27 100644
--- a/src/mame/mame.mak
+++ b/src/mame/mame.mak
@@ -94,6 +94,7 @@ CPUS += ALPHA8201
 CPUS += CDP1802
 CPUS += COP400
 CPUS += TLCS90
+CPUS += TLCS900
 CPUS += MB88XX
 CPUS += MB86233
 CPUS += SSP1601