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https://github.com/holub/mame
synced 2025-07-04 09:28:51 +03:00
sh4: fix FMOV* opcodes,
half of FPU was not correct, but who cares ?)
This commit is contained in:
MetalliC
parent
07ef2097d3
commit
4f85c189fa
@ -2556,21 +2556,7 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
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* OPCODE DISPATCHERS
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*****************************************************************************/
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// TODO: current SZ=1(64bit) FMOVs correct for SH4 in LE mode only
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/* FMOV.S @Rm+,FRn PR=0 SZ=0 1111nnnnmmmm1001 */
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/* FMOV @Rm+,DRn PR=0 SZ=1 1111nnn0mmmm1001 */
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@ -2580,35 +2566,36 @@ inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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n = n & 14;
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m_ea = m_r[m];
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m_r[m] += 8;
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (n & 1) {
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n = n & 14;
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n &= 14;
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[m];
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m_xf[n] = RL(m_ea );
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m_r[m] += 4;
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m_xf[n+1] = RL(m_ea+4 );
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m_xf[n^1] = RL(m_ea+4 );
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m_r[m] += 4;
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} else {
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[m];
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m_fr[n] = RL(m_ea );
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m_r[m] += 4;
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m_fr[n+1] = RL(m_ea+4 );
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m_fr[n^1] = RL(m_ea+4 );
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m_r[m] += 4;
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}
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} else { /* SZ = 0 */
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m_ea = m_r[m];
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_fr[n] = RL(m_ea );
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m_r[m] += 4;
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}
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}
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}
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/* FMOV.S FRm,@Rn PR=0 SZ=0 1111nnnnmmmm1010 */
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/* FMOV DRm,@Rn PR=0 SZ=1 1111nnnnmmm01010 */
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@ -2618,29 +2605,31 @@ inline void sh34_base_device::FMOVFRMR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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m= m & 14;
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m_ea = m_r[n];
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WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
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WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (m & 1) {
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m= m & 14;
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m &= 14;
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_ea = m_r[n];
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WL(m_ea,m_xf[m] );
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WL(m_ea+4,m_xf[m+1] );
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WL(m_ea+4,m_xf[m^1] );
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} else {
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_ea = m_r[n];
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WL(m_ea,m_fr[m] );
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WL(m_ea+4,m_fr[m+1] );
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WL(m_ea+4,m_fr[m^1] );
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}
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} else { /* SZ = 0 */
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m_ea = m_r[n];
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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WL(m_ea,m_fr[m] );
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}
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}
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}
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/* FMOV.S FRm,@-Rn PR=0 SZ=0 1111nnnnmmmm1011 */
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/* FMOV DRm,@-Rn PR=0 SZ=1 1111nnnnmmm01011 */
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@ -2650,33 +2639,34 @@ inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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m= m & 14;
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m_r[n] -= 8;
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m_ea = m_r[n];
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WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
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WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (m & 1) {
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m= m & 14;
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m &= 14;
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_r[n] -= 8;
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m_ea = m_r[n];
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WL(m_ea,m_xf[m] );
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WL(m_ea+4,m_xf[m+1] );
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WL(m_ea+4,m_xf[m^1] );
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} else {
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_r[n] -= 8;
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m_ea = m_r[n];
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WL(m_ea,m_fr[m] );
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WL(m_ea+4,m_fr[m+1] );
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WL(m_ea+4,m_fr[m^1] );
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}
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} else { /* SZ = 0 */
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m_r[n] -= 4;
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m_ea = m_r[n];
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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WL(m_ea,m_fr[m] );
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}
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}
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}
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/* FMOV.S FRm,@(R0,Rn) PR=0 SZ=0 1111nnnnmmmm0111 */
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/* FMOV DRm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm00111 */
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@ -2686,29 +2676,31 @@ inline void sh34_base_device::FMOVFRS0(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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m= m & 14;
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m_ea = m_r[0] + m_r[n];
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WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] );
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WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] );
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (m & 1) {
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m= m & 14;
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m &= 14;
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_ea = m_r[0] + m_r[n];
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WL(m_ea,m_xf[m] );
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WL(m_ea+4,m_xf[m+1] );
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WL(m_ea+4,m_xf[m^1] );
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} else {
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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m_ea = m_r[0] + m_r[n];
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WL(m_ea,m_fr[m] );
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WL(m_ea+4,m_fr[m+1] );
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WL(m_ea+4,m_fr[m^1] );
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}
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} else { /* SZ = 0 */
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m_ea = m_r[0] + m_r[n];
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#ifdef LSB_FIRST
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m ^= m_fpu_pr;
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#endif
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WL(m_ea,m_fr[m] );
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}
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}
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}
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/* FMOV.S @(R0,Rm),FRn PR=0 SZ=0 1111nnnnmmmm0110 */
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/* FMOV @(R0,Rm),DRn PR=0 SZ=1 1111nnn0mmmm0110 */
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@ -2718,29 +2710,31 @@ inline void sh34_base_device::FMOVS0FR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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n= n & 14;
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m_ea = m_r[0] + m_r[m];
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (n & 1) {
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n= n & 14;
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n &= 14;
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[0] + m_r[m];
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m_xf[n] = RL(m_ea );
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m_xf[n+1] = RL(m_ea+4 );
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m_xf[n^1] = RL(m_ea+4 );
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} else {
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[0] + m_r[m];
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m_fr[n] = RL(m_ea );
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m_fr[n+1] = RL(m_ea+4 );
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m_fr[n^1] = RL(m_ea+4 );
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}
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} else { /* SZ = 0 */
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m_ea = m_r[0] + m_r[m];
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_fr[n] = RL(m_ea );
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}
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}
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}
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/* FMOV.S @Rm,FRn PR=0 SZ=0 1111nnnnmmmm1000 */
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/* FMOV @Rm,DRn PR=0 SZ=1 1111nnn0mmmm1000 */
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@ -2751,37 +2745,31 @@ inline void sh34_base_device::FMOVMRFR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if (m_fpu_pr) { /* PR = 1 */
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if (n & 1) {
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n= n & 14;
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m_ea = m_r[m];
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
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m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
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} else {
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n= n & 14;
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m_ea = m_r[m];
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m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea );
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m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 );
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}
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} else { /* PR = 0 */
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if (m_fpu_sz) { /* SZ = 1 */
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if (n & 1) {
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n= n & 14;
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n &= 14;
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[m];
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m_xf[n] = RL(m_ea );
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m_xf[n+1] = RL(m_ea+4 );
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m_xf[n^1] = RL(m_ea+4 );
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} else {
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n= n & 14;
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_ea = m_r[m];
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m_fr[n] = RL(m_ea );
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m_fr[n+1] = RL(m_ea+4 );
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m_fr[n^1] = RL(m_ea+4 );
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}
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} else { /* SZ = 0 */
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m_ea = m_r[m];
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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#endif
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m_fr[n] = RL(m_ea );
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}
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}
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}
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/* FMOV FRm,FRn PR=0 SZ=0 FRm -> FRn 1111nnnnmmmm1100 */
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/* FMOV DRm,DRn PR=0 SZ=1 DRm -> DRn 1111nnn0mmm01100 */
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@ -2792,9 +2780,14 @@ inline void sh34_base_device::FMOVFR(const uint16_t opcode)
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{
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uint32_t m = Rm; uint32_t n = Rn;
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if ((m_fpu_sz == 0) && (m_fpu_pr == 0)) /* SZ = 0 */
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if (m_fpu_sz == 0) { /* SZ = 0 */
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#ifdef LSB_FIRST
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n ^= m_fpu_pr;
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m ^= m_fpu_pr;
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#endif
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m_fr[n] = m_fr[m];
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else { /* SZ = 1 or PR = 1 */
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}
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else { /* SZ = 1 */
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if (m & 1) {
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if (n & 1) {
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m_xf[n & 14] = m_xf[m & 14];
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@ -2818,25 +2811,41 @@ inline void sh34_base_device::FMOVFR(const uint16_t opcode)
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/* FLDI1 FRn 1111nnnn10011101 */
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inline void sh34_base_device::FLDI1(const uint16_t opcode)
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{
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#ifdef LSB_FIRST
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m_fr[Rn ^ m_fpu_pr] = 0x3F800000;
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#else
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m_fr[Rn] = 0x3F800000;
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#endif
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}
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/* FLDI0 FRn 1111nnnn10001101 */
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inline void sh34_base_device::FLDI0(const uint16_t opcode)
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{
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#ifdef LSB_FIRST
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m_fr[Rn ^ m_fpu_pr] = 0;
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#else
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m_fr[Rn] = 0;
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#endif
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}
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/* FLDS FRm,FPUL 1111mmmm00011101 */
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inline void sh34_base_device:: FLDS(const uint16_t opcode)
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{
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#ifdef LSB_FIRST
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m_fpul = m_fr[Rn ^ m_fpu_pr];
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#else
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m_fpul = m_fr[Rn];
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#endif
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}
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/* FSTS FPUL,FRn 1111nnnn00001101 */
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inline void sh34_base_device:: FSTS(const uint16_t opcode)
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{
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#ifdef LSB_FIRST
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m_fr[Rn ^ m_fpu_pr] = m_fpul;
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#else
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m_fr[Rn] = m_fpul;
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#endif
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}
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/* FRCHG 1111101111111101 */
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