mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
tms1000: split execute_run into execute_one (nw)
This commit is contained in:
hap
parent
be9fea28e4
commit
50ee57f1b3
@ -64,3 +64,21 @@ u32 tms1000c_cpu_device::decode_micro(u8 sel)
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return decode;
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}
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// execute
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void tms1000c_cpu_device::execute_run()
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{
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while (m_icount > 0)
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{
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if (m_halt_pin)
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{
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// not running (output pins remain unchanged)
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m_icount = 0;
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return;
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}
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m_icount--;
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execute_one();
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}
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}
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@ -23,6 +23,7 @@ protected:
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// overrides
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virtual void device_add_mconfig(machine_config &config) override;
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virtual u32 decode_micro(u8 sel) override;
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virtual void execute_run() override;
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virtual void op_br() override { op_br3(); } // 3-level stack
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virtual void op_call() override { op_call3(); } // "
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@ -144,7 +144,7 @@ void tms1k_base_device::device_start()
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m_r = 0;
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m_o = 0;
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m_o_index = 0;
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m_halt = false;
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m_halt_pin = false;
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m_cki_bus = 0;
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m_c4 = 0;
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m_p = 0;
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@ -184,7 +184,7 @@ void tms1k_base_device::device_start()
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save_item(NAME(m_r));
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save_item(NAME(m_o));
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save_item(NAME(m_o_index));
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save_item(NAME(m_halt));
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save_item(NAME(m_halt_pin));
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save_item(NAME(m_cki_bus));
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save_item(NAME(m_c4));
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save_item(NAME(m_p));
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@ -314,7 +314,7 @@ void tms1k_base_device::execute_set_input(int line, int state)
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return;
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// HALT pin (CMOS only)
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m_halt = bool(state);
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m_halt_pin = bool(state);
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}
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void tms1k_base_device::write_o_output(u8 index)
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@ -604,145 +604,142 @@ void tms1k_base_device::op_sbl()
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//-------------------------------------------------
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// execute_run
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// execute
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//-------------------------------------------------
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void tms1k_base_device::execute_one()
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{
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switch (m_subcycle)
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{
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case 0:
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// fetch: rom address 1/2
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// execute: br/call 2/2
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if (m_fixed & F_BR) op_br();
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if (m_fixed & F_CALL) op_call();
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if (m_fixed & F_RETN) op_retn();
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// execute: k input valid, read ram, clear alu inputs
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dynamic_output();
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set_cki_bus();
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m_ram_in = m_data->read_byte(m_ram_address) & 0xf;
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m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf;
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m_p = 0;
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m_n = 0;
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m_carry_in = 0;
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break;
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case 1:
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// fetch: rom address 2/2
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m_rom_address = (m_ca << (m_pc_bits+4)) | (m_pa << m_pc_bits) | m_pc;
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// execute: update alu inputs
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// N inputs
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if (m_micro & M_15TN) m_n |= 0xf;
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if (m_micro & M_ATN) m_n |= m_a;
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if (m_micro & M_NATN) m_n |= (~m_a & 0xf);
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if (m_micro & M_CKN) m_n |= m_cki_bus;
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if (m_micro & M_MTN) m_n |= m_ram_in;
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// P inputs
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if (m_micro & M_CKP) m_p |= m_cki_bus;
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if (m_micro & M_MTP) m_p |= m_ram_in;
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if (m_micro & M_YTP) m_p |= m_y;
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if (m_micro & M_DMTP) m_p |= m_dam_in;
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if (m_micro & M_NDMTP) m_p |= (~m_dam_in & 0xf);
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// carry input
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if (m_micro & M_CIN) m_carry_in |= 1;
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if (m_micro & M_SSS) m_carry_in |= m_eac;
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break;
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case 2:
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{
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// fetch: nothing
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// execute: perform alu logic
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// note: officially, only 1 alu operation is allowed per opcode
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m_adder_out = m_p + m_n + m_carry_in;
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int carry_out = m_adder_out >> 4 & 1;
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int status = 1;
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m_ram_out = -1;
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if (m_micro & M_C8) status &= carry_out;
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if (m_micro & M_NE) status &= (m_n != m_p); // COMP
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if (m_micro & M_CKM) m_ram_out = m_cki_bus;
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// special status circuit
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if (m_micro & M_SSE)
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{
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m_eac = m_carry_out;
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if (m_add)
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m_eac |= carry_out;
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}
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m_carry_out = carry_out;
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if (m_micro & M_STO || (m_micro & M_CME && m_eac == m_add))
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m_ram_out = m_a;
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// handle the other fixed opcodes here
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if (m_fixed & F_SBIT) op_sbit();
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if (m_fixed & F_RBIT) op_rbit();
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if (m_fixed & F_SETR) op_setr();
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if (m_fixed & F_RSTR) op_rstr();
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if (m_fixed & F_TDO) op_tdo();
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if (m_fixed & F_CLO) op_clo();
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if (m_fixed & F_LDX) op_ldx();
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if (m_fixed & F_COMX) op_comx();
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if (m_fixed & F_COMX8) op_comx8();
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if (m_fixed & F_LDP) op_ldp();
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if (m_fixed & F_COMC) op_comc();
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if (m_fixed & F_TPC) op_tpc();
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if (m_fixed & F_OFF) op_off();
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if (m_fixed & F_SEAC) op_seac();
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if (m_fixed & F_REAC) op_reac();
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if (m_fixed & F_SAL) op_sal();
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if (m_fixed & F_SBL) op_sbl();
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if (m_fixed & F_XDA) op_xda();
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// after fixed opcode handling: store status, write ram
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m_status = status;
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if (m_ram_out != -1)
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m_data->write_byte(m_ram_address, m_ram_out);
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break;
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}
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case 3:
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// fetch: update pc, ram address 1/2
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// execute: register store 1/2
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break;
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case 4:
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// execute: register store 2/2
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if (m_micro & M_AUTA) m_a = m_adder_out & 0xf;
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if (m_micro & M_AUTY) m_y = m_adder_out & 0xf;
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if (m_micro & M_STSL) m_status_latch = m_status;
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// fetch: update pc, ram address 2/2
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read_opcode();
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m_ram_address = m_x << 4 | m_y;
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break;
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case 5:
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// fetch: instruction decode (handled above, before next_pc)
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// execute: br/call 1/2
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break;
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}
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m_subcycle = (m_subcycle + 1) % 6;
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}
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void tms1k_base_device::execute_run()
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{
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while (m_icount > 0)
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{
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m_icount--;
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if (m_halt)
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{
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// not running (output pins remain unchanged)
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m_icount = 0;
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return;
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}
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switch (m_subcycle)
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{
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case 0:
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// fetch: rom address 1/2
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// execute: br/call 2/2
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if (m_fixed & F_BR) op_br();
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if (m_fixed & F_CALL) op_call();
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if (m_fixed & F_RETN) op_retn();
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// execute: k input valid, read ram, clear alu inputs
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dynamic_output();
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set_cki_bus();
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m_ram_in = m_data->read_byte(m_ram_address) & 0xf;
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m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf;
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m_p = 0;
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m_n = 0;
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m_carry_in = 0;
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break;
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case 1:
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// fetch: rom address 2/2
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m_rom_address = (m_ca << (m_pc_bits+4)) | (m_pa << m_pc_bits) | m_pc;
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// execute: update alu inputs
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// N inputs
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if (m_micro & M_15TN) m_n |= 0xf;
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if (m_micro & M_ATN) m_n |= m_a;
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if (m_micro & M_NATN) m_n |= (~m_a & 0xf);
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if (m_micro & M_CKN) m_n |= m_cki_bus;
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if (m_micro & M_MTN) m_n |= m_ram_in;
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// P inputs
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if (m_micro & M_CKP) m_p |= m_cki_bus;
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if (m_micro & M_MTP) m_p |= m_ram_in;
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if (m_micro & M_YTP) m_p |= m_y;
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if (m_micro & M_DMTP) m_p |= m_dam_in;
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if (m_micro & M_NDMTP) m_p |= (~m_dam_in & 0xf);
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// carry input
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if (m_micro & M_CIN) m_carry_in |= 1;
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if (m_micro & M_SSS) m_carry_in |= m_eac;
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break;
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case 2:
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{
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// fetch: nothing
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// execute: perform alu logic
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// note: officially, only 1 alu operation is allowed per opcode
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m_adder_out = m_p + m_n + m_carry_in;
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int carry_out = m_adder_out >> 4 & 1;
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int status = 1;
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m_ram_out = -1;
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if (m_micro & M_C8) status &= carry_out;
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if (m_micro & M_NE) status &= (m_n != m_p); // COMP
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if (m_micro & M_CKM) m_ram_out = m_cki_bus;
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// special status circuit
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if (m_micro & M_SSE)
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{
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m_eac = m_carry_out;
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if (m_add)
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m_eac |= carry_out;
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}
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m_carry_out = carry_out;
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if (m_micro & M_STO || (m_micro & M_CME && m_eac == m_add))
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m_ram_out = m_a;
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// handle the other fixed opcodes here
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if (m_fixed & F_SBIT) op_sbit();
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if (m_fixed & F_RBIT) op_rbit();
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if (m_fixed & F_SETR) op_setr();
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if (m_fixed & F_RSTR) op_rstr();
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if (m_fixed & F_TDO) op_tdo();
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if (m_fixed & F_CLO) op_clo();
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if (m_fixed & F_LDX) op_ldx();
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if (m_fixed & F_COMX) op_comx();
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if (m_fixed & F_COMX8) op_comx8();
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if (m_fixed & F_LDP) op_ldp();
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if (m_fixed & F_COMC) op_comc();
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if (m_fixed & F_TPC) op_tpc();
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if (m_fixed & F_OFF) op_off();
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if (m_fixed & F_SEAC) op_seac();
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if (m_fixed & F_REAC) op_reac();
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if (m_fixed & F_SAL) op_sal();
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if (m_fixed & F_SBL) op_sbl();
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if (m_fixed & F_XDA) op_xda();
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// after fixed opcode handling: store status, write ram
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m_status = status;
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if (m_ram_out != -1)
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m_data->write_byte(m_ram_address, m_ram_out);
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break;
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}
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case 3:
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// fetch: update pc, ram address 1/2
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// execute: register store 1/2
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break;
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case 4:
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// execute: register store 2/2
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if (m_micro & M_AUTA) m_a = m_adder_out & 0xf;
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if (m_micro & M_AUTY) m_y = m_adder_out & 0xf;
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if (m_micro & M_STSL) m_status_latch = m_status;
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// fetch: update pc, ram address 2/2
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read_opcode();
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m_ram_address = m_x << 4 | m_y;
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break;
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case 5:
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// fetch: instruction decode (handled above, before next_pc)
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// execute: br/call 1/2
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break;
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}
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m_subcycle = (m_subcycle + 1) % 6;
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execute_one();
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}
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}
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@ -106,10 +106,11 @@ protected:
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// device_execute_interface overrides
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virtual u32 execute_min_cycles() const override { return 1; }
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virtual u32 execute_max_cycles() const override { return 6; }
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virtual u32 execute_max_cycles() const override { return 1; }
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virtual u32 execute_input_lines() const override { return 1; }
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virtual void execute_set_input(int line, int state) override;
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virtual void execute_run() override;
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virtual void execute_one();
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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@ -151,28 +152,28 @@ protected:
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// standard/fixed instructions - these are documented more in their specific handlers
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enum
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{
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F_BR = (1<<0),
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F_CALL = (1<<1),
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F_CLO = (1<<2),
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F_COMC = (1<<3),
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F_COMX = (1<<4),
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F_BR = (1<<0),
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F_CALL = (1<<1),
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F_CLO = (1<<2),
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F_COMC = (1<<3),
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F_COMX = (1<<4),
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F_COMX8 = (1<<5),
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F_LDP = (1<<6),
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F_LDX = (1<<7),
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F_RBIT = (1<<8),
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F_RETN = (1<<9),
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F_RSTR = (1<<10),
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F_SBIT = (1<<11),
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F_SETR = (1<<12),
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F_TDO = (1<<13),
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F_TPC = (1<<14),
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F_LDP = (1<<6),
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F_LDX = (1<<7),
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F_RBIT = (1<<8),
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F_RETN = (1<<9),
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F_RSTR = (1<<10),
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F_SBIT = (1<<11),
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F_SETR = (1<<12),
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F_TDO = (1<<13),
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F_TPC = (1<<14),
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F_OFF = (1<<15),
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F_REAC = (1<<16),
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F_SAL = (1<<17),
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F_SBL = (1<<18),
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F_SEAC = (1<<19),
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F_XDA = (1<<20)
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F_OFF = (1<<15),
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F_REAC = (1<<16),
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F_SAL = (1<<17),
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F_SBL = (1<<18),
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F_SEAC = (1<<19),
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F_XDA = (1<<20)
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};
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void next_pc();
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@ -256,7 +257,7 @@ protected:
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int m_subcycle;
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int m_icount;
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u8 m_o_index;
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bool m_halt; // halt pin state
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bool m_halt_pin;
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u8 m_o_pins; // how many O pins
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u8 m_r_pins; // how many R pins
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