mirror of
https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
v25: Improve peripheral emulation
- Add preliminary DMA controller (capable of doing burst memory transfers) - Make timer 1 cause two different interrupts - Add kludge for one timer edge case * tvdear: Map some more ROM; add P0 readback
This commit is contained in:
AJR
parent
2e1f992c45
commit
510ebf5b38
@ -69,6 +69,8 @@ v25_common_device::v25_common_device(const machine_config &mconfig, device_type
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, m_p0_out(*this)
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, m_p1_out(*this)
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, m_p2_out(*this)
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, m_dma_read(*this, 0xffff)
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, m_dma_write(*this)
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, m_prefetch_size(prefetch_size)
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, m_prefetch_cycles(prefetch_cycles)
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, m_chip_type(chip_type)
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@ -215,7 +217,6 @@ void v25_common_device::device_reset()
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m_intm = 0;
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m_halted = 0;
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m_TM0 = m_MD0 = m_TM1 = m_MD1 = 0;
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m_TMC0 = m_TMC1 = 0;
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for (int i = 0; i < 2; i++)
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@ -226,6 +227,10 @@ void v25_common_device::device_reset()
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m_sce[i] = 0;
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}
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m_dmam[0] = m_dmam[1] = 0;
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m_dma_channel = -1;
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m_last_dma_channel = 0;
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m_RAMEN = 1;
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m_TB = 20;
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m_PCK = 8;
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@ -483,6 +488,111 @@ void v25_common_device::external_int()
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}
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}
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void v25_common_device::dma_process()
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{
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uint16_t sar = m_internal_ram[m_dma_channel * 4];
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uint16_t dar = m_internal_ram[m_dma_channel * 4 + 1];
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uint16_t sarh_darh = m_internal_ram[m_dma_channel * 4 + 2];
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uint8_t dmamode = BIT(m_dmam[m_dma_channel], 5, 3);
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bool w = BIT(m_dmam[m_dma_channel], 4);
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uint32_t saddr = (BIT(dmamode, 0) ? 0 : (uint32_t(sarh_darh) & 0xff00) << 4) + sar;
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uint32_t daddr = (BIT(dmamode, 1) ? 0 : (uint32_t(sarh_darh) & 0x00ff) << 12) + dar;
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switch (dmamode & 3)
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{
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case 0:
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// Memory to memory transfer
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if (w)
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{
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uint16_t data = v25_read_word(saddr);
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v25_write_word(daddr, data);
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}
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else
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{
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uint8_t data = v25_read_byte(saddr);
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v25_write_byte(daddr, data);
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}
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m_icount -= (w && m_program->addr_width() == 8) ? 8 : 4;
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break;
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case 1:
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// I/O to memory transfer
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if (w && m_program->addr_width() == 16)
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{
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uint16_t data = m_dma_read[m_dma_channel](daddr);
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v25_write_word(daddr, data);
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}
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else
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{
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uint8_t data = m_dma_read[m_dma_channel](daddr);
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v25_write_byte(daddr, data);
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if (w)
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{
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logerror("Warning: V25 16-bit I/O to memory transfer\n");
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data = m_dma_read[m_dma_channel](daddr + 1);
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v25_write_byte(daddr + 1, data);
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m_icount -= 2;
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}
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}
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m_icount -= 2;
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break;
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case 2:
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// Memory to I/O transfer
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if (w && m_program->addr_width() == 16)
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{
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uint16_t data = v25_read_word(saddr);
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m_dma_write[m_dma_channel](saddr, data);
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}
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else
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{
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uint8_t data = v25_read_byte(saddr);
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m_dma_write[m_dma_channel](saddr, data);
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if (w)
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{
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logerror("Warning: V25 16-bit memory to I/O transfer\n");
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data = v25_read_byte(saddr + 1);
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m_dma_write[m_dma_channel](saddr + 1, data);
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m_icount -= 2;
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}
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}
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m_icount -= 2;
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break;
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default:
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logerror("Reserved DMA transfer mode\n");
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m_icount--;
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break;
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}
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// Update source and destination based on address control
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uint8_t dmac = m_dmac[m_dma_channel];
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if (BIT(dmac, 0, 2) == 1)
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m_internal_ram[m_dma_channel * 4] = sar + (w ? 2 : 1);
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else if (BIT(dmac, 0, 2) == 2)
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m_internal_ram[m_dma_channel * 4] = sar - (w ? 2 : 1);
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if (BIT(dmac, 4, 2) == 1)
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m_internal_ram[m_dma_channel * 4 + 1] = dar + (w ? 2 : 1);
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else if (BIT(dmac, 4, 2) == 2)
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m_internal_ram[m_dma_channel * 4 + 1] = dar - (w ? 2 : 1);
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// Update TC
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uint16_t tc = --m_internal_ram[m_dma_channel * 4 + 3];
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if (tc == 0)
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{
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m_dmam[m_dma_channel] &= 0xf0; // disable channel
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m_pending_irq |= m_dma_channel ? INTD1 : INTD0; // request interrupt
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}
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if (dmamode == 0 || dmamode > 4 || tc == 0)
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{
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// Single step/single transfer modes (or end of burst)
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m_last_dma_channel = m_dma_channel;
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m_dma_channel = -1;
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}
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}
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/****************************************************************************/
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/* OPCODES */
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/****************************************************************************/
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@ -570,6 +680,9 @@ void v25_common_device::device_start()
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m_EO = 0;
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m_E16 = 0;
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m_TM0 = m_MD0 = m_TM1 = m_MD1 = 0;
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m_dmac[0] = m_dmac[1] = 0;
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for (i = 0; i < 4; i++)
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m_timers[i] = timer_alloc(FUNC(v25_common_device::v25_timer_callback), this);
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@ -630,6 +743,10 @@ void v25_common_device::device_start()
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save_item(NAME(m_scc));
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save_item(NAME(m_brg));
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save_item(NAME(m_sce));
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save_item(NAME(m_dmac));
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save_item(NAME(m_dmam));
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save_item(NAME(m_dma_channel));
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save_item(NAME(m_last_dma_channel));
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save_item(NAME(m_RAMEN));
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save_item(NAME(m_TB));
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save_item(NAME(m_PCK));
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@ -790,6 +907,12 @@ void v25_common_device::execute_run()
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}
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while(m_icount>0) {
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if (m_dma_channel != -1)
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{
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dma_process();
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continue;
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}
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/* Dispatch IRQ */
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m_prev_ip = m_ip;
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if (m_no_interrupt==0 && (m_pending_irq & m_unmasked_irq))
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@ -808,5 +931,13 @@ void v25_common_device::execute_run()
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prev_ICount = m_icount;
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(this->*s_nec_instruction[fetchop()])();
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do_prefetch(prev_ICount);
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if ((m_dmam[0] & 0x0c) == 0x0c || (m_dmam[1] & 0x0c) == 0x0c)
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{
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if ((m_dmam[1 - m_last_dma_channel] & 0x0c) == 0x0c)
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m_dma_channel = 1 - m_last_dma_channel;
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else
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m_dma_channel = m_last_dma_channel;
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}
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}
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}
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@ -39,6 +39,12 @@ public:
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auto p1_out_cb() { return m_p1_out.bind(); }
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auto p2_out_cb() { return m_p2_out.bind(); }
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auto dma0_read_cb() { return m_dma_read[0].bind(); }
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auto dma1_read_cb() { return m_dma_read[1].bind(); }
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auto dma0_write_cb() { return m_dma_write[0].bind(); }
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auto dma1_write_cb() { return m_dma_write[1].bind(); }
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TIMER_CALLBACK_MEMBER(v25_timer_callback);
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protected:
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@ -113,19 +119,25 @@ private:
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uint8_t m_no_interrupt;
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uint8_t m_halted;
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/* timer related */
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// timer related
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uint16_t m_TM0, m_MD0, m_TM1, m_MD1;
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uint8_t m_TMC0, m_TMC1;
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emu_timer *m_timers[4];
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/* serial interface related */
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// serial interface related
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uint8_t m_scm[2];
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uint8_t m_scc[2];
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uint8_t m_brg[2];
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uint8_t m_sce[2];
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/* system control */
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uint8_t m_RAMEN, m_TB, m_PCK; /* PRC register */
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// DMA related
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uint8_t m_dmac[2];
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uint8_t m_dmam[2];
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int8_t m_dma_channel;
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int8_t m_last_dma_channel;
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// system control
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uint8_t m_RAMEN, m_TB, m_PCK; // PRC register
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uint8_t m_RFM;
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uint16_t m_WTC;
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uint32_t m_IDB;
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@ -146,6 +158,9 @@ private:
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devcb_write8 m_p1_out;
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devcb_write8 m_p2_out;
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devcb_read16::array<2> m_dma_read;
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devcb_write16::array<2> m_dma_write;
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uint8_t m_prefetch_size;
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uint8_t m_prefetch_cycles;
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int8_t m_prefetch_count;
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@ -177,6 +192,7 @@ private:
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void nec_bankswitch(unsigned bank_num);
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void nec_trap();
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void external_int();
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void dma_process();
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void ida_sfr_map(address_map &map) ATTR_COLD;
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uint8_t read_irqcontrol(int /*INTSOURCES*/ source, uint8_t priority);
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@ -257,6 +273,18 @@ private:
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void tmic1_w(uint8_t d);
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uint8_t tmic2_r();
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void tmic2_w(uint8_t d);
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uint8_t dmac0_r();
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void dmac0_w(uint8_t d);
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uint8_t dmam0_r();
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void dmam0_w(uint8_t d);
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uint8_t dmac1_r();
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void dmac1_w(uint8_t d);
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uint8_t dmam1_r();
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void dmam1_w(uint8_t d);
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uint8_t dic0_r();
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void dic0_w(uint8_t d);
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uint8_t dic1_r();
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void dic1_w(uint8_t d);
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uint8_t rfm_r();
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void rfm_w(uint8_t d);
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uint16_t wtc_r();
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@ -57,6 +57,12 @@ void v25_common_device::ida_sfr_map(address_map &map)
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map(0x19c, 0x19c).rw(FUNC(v25_common_device::tmic0_r), FUNC(v25_common_device::tmic0_w));
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map(0x19d, 0x19d).rw(FUNC(v25_common_device::tmic1_r), FUNC(v25_common_device::tmic1_w));
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map(0x19e, 0x19e).rw(FUNC(v25_common_device::tmic2_r), FUNC(v25_common_device::tmic2_w));
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map(0x1a0, 0x1a0).rw(FUNC(v25_common_device::dmac0_r), FUNC(v25_common_device::dmac0_w));
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map(0x1a1, 0x1a1).rw(FUNC(v25_common_device::dmam0_r), FUNC(v25_common_device::dmam0_w));
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map(0x1a2, 0x1a2).rw(FUNC(v25_common_device::dmac1_r), FUNC(v25_common_device::dmac1_w));
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map(0x1a3, 0x1a3).rw(FUNC(v25_common_device::dmam1_r), FUNC(v25_common_device::dmam1_w));
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map(0x1ac, 0x1ac).rw(FUNC(v25_common_device::dic0_r), FUNC(v25_common_device::dic0_w));
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map(0x1ad, 0x1ad).rw(FUNC(v25_common_device::dic1_r), FUNC(v25_common_device::dic1_w));
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map(0x1e1, 0x1e1).rw(FUNC(v25_common_device::rfm_r), FUNC(v25_common_device::rfm_w));
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map(0x1e8, 0x1e9).rw(FUNC(v25_common_device::wtc_r), FUNC(v25_common_device::wtc_w));
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map(0x1ea, 0x1ea).rw(FUNC(v25_common_device::flag_r), FUNC(v25_common_device::flag_w));
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@ -469,7 +475,13 @@ uint16_t v25_common_device::md1_r()
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void v25_common_device::md1_w(uint16_t d)
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{
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m_MD1 = d;
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if (m_MD1 == 0 && d != 0)
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{
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m_MD1 = d;
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tmc1_w(m_TMC1); // HACK: start timer if necessary
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}
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else
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m_MD1 = d;
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}
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void v25_common_device::tmc0_w(uint8_t d)
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@ -477,7 +489,7 @@ void v25_common_device::tmc0_w(uint8_t d)
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m_TMC0 = d;
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if (BIT(d, 0)) // oneshot mode
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{
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if (BIT(d, 7))
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if (BIT(d, 7) && m_TM0 != 0)
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{
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unsigned tmp = m_PCK * m_TM0 * (BIT(d, 6) ? 128 : 12);
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attotime time = clocks_to_attotime(tmp);
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@ -486,7 +498,7 @@ void v25_common_device::tmc0_w(uint8_t d)
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else
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m_timers[0]->adjust(attotime::never);
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if (BIT(d, 5))
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if (BIT(d, 5) && m_MD0 != 0)
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{
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unsigned tmp = m_PCK * m_MD0 * (BIT(d, 4) ? 128 : 12);
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attotime time = clocks_to_attotime(tmp);
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@ -497,7 +509,7 @@ void v25_common_device::tmc0_w(uint8_t d)
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}
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else // interval mode
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{
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if (BIT(d, 7))
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if (BIT(d, 7) && m_MD0 != 0)
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{
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unsigned tmp = m_PCK * m_MD0 * (BIT(d, 6) ? 128 : 6);
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attotime time = clocks_to_attotime(tmp);
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@ -516,11 +528,11 @@ void v25_common_device::tmc0_w(uint8_t d)
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void v25_common_device::tmc1_w(uint8_t d)
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{
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m_TMC1 = d & 0xC0;
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if (BIT(d, 7))
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if (BIT(d, 7) && m_MD1 != 0)
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{
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unsigned tmp = m_PCK * m_MD1 * (BIT(d, 6) ? 128 : 6);
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attotime time = clocks_to_attotime(tmp);
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m_timers[2]->adjust(time, INTTU2, time);
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m_timers[2]->adjust(time, INTTU1 | INTTU2, time);
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m_TM1 = m_MD1;
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}
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else
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@ -569,6 +581,115 @@ void v25_common_device::tmic2_w(uint8_t d)
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write_irqcontrol(INTTU2, d);
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}
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uint8_t v25_common_device::dmac0_r()
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{
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return m_dmac[0];
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}
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void v25_common_device::dmac0_w(uint8_t d)
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{
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logerror("%06x: DMAC0 set to %02x\n", PC(), d);
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logerror(" SAR0 %s after each transfer\n", (d & 0x03) == 0x01 ? "incremented" : (d & 0x03) == 0x02 ? "decremented" : "unmodified");
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logerror(" DAR0 %s after each transfer\n", (d & 0x30) == 0x10 ? "incremented" : (d & 0x30) == 0x20 ? "decremented" : "unmodified");
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m_dmac[0] = d & 0x33;
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}
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uint8_t v25_common_device::dmam0_r()
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{
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return m_dmam[0];
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}
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void v25_common_device::dmam0_w(uint8_t d)
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{
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logerror("%06x: DMAM0 set to %02x\n", PC(), d);
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if ((d & 0x60) == 0)
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logerror(" %s mode, memory to memory, %s\n", BIT(d, 7) ? "Single step" : "Burst", BIT(d, 4) ? "words" : "bytes");
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else if ((d & 0x60) != 0x60)
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logerror(" %s mode, %s to %s, %s\n", BIT(d, 7) ? "Single transfer" : "Demand release",
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BIT(d, 5) ? "I/O" : "memory",
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BIT(d, 6) ? "I/O" : "memory",
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BIT(d, 4) ? "words" : "bytes");
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if (BIT(d, 2))
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{
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uint16_t sar = m_internal_ram[0];
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uint16_t dar = m_internal_ram[1];
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uint16_t sarh_darh = m_internal_ram[2];
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uint16_t tc = m_internal_ram[3];
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logerror(" DMA enabled%s (%04x:%04x -> %04x:%04x, %u %s)\n", BIT(d, 3) ? " and triggered" : "",
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sarh_darh & 0xff00, sar,
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(sarh_darh & 0x00ff) << 8, dar,
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tc, BIT(d, 4) ? "words" : "bytes");
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}
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else
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logerror(" DMA not enabled\n");
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m_dmam[0] = d & 0xfc;
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}
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uint8_t v25_common_device::dmac1_r()
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{
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return m_dmac[1];
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}
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void v25_common_device::dmac1_w(uint8_t d)
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{
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logerror("%06x: DMAC1 set to %02x\n", PC(), d);
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logerror(" SAR1 %s after each transfer\n", (d & 0x03) == 0x01 ? "incremented" : (d & 0x03) == 0x02 ? "decremented" : "unmodified");
|
||||
logerror(" DAR1 %s after each transfer\n", (d & 0x30) == 0x10 ? "incremented" : (d & 0x30) == 0x20 ? "decremented" : "unmodified");
|
||||
m_dmac[1] = d & 0x33;
|
||||
}
|
||||
|
||||
uint8_t v25_common_device::dmam1_r()
|
||||
{
|
||||
return m_dmam[1];
|
||||
}
|
||||
|
||||
void v25_common_device::dmam1_w(uint8_t d)
|
||||
{
|
||||
logerror("%06x: DMAM1 set to %02x\n", PC(), d);
|
||||
if ((d & 0x60) == 0)
|
||||
logerror(" %s mode, memory to memory, %s\n", BIT(d, 7) ? "Single step" : "Burst", BIT(d, 4) ? "words" : "bytes");
|
||||
else if ((d & 0x60) != 0x60)
|
||||
logerror(" %s mode, %s to %s, %s\n", BIT(d, 7) ? "Single transfer" : "Demand release",
|
||||
BIT(d, 5) ? "I/O" : "memory",
|
||||
BIT(d, 6) ? "I/O" : "memory",
|
||||
BIT(d, 4) ? "words" : "bytes");
|
||||
if (BIT(d, 2))
|
||||
{
|
||||
uint16_t sar = m_internal_ram[4];
|
||||
uint16_t dar = m_internal_ram[5];
|
||||
uint16_t sarh_darh = m_internal_ram[6];
|
||||
uint16_t tc = m_internal_ram[7];
|
||||
logerror(" DMA enabled%s (%04x:%04x -> %04x:%04x, %u %s)\n", BIT(d, 3) ? " and triggered" : "",
|
||||
sarh_darh & 0xff00, sar,
|
||||
(sarh_darh & 0x00ff) << 8, dar,
|
||||
tc, BIT(d, 4) ? "words" : "bytes");
|
||||
}
|
||||
else
|
||||
logerror(" DMA not enabled\n");
|
||||
m_dmam[1] = d & 0xfc;
|
||||
}
|
||||
|
||||
uint8_t v25_common_device::dic0_r()
|
||||
{
|
||||
return read_irqcontrol(INTD0, m_priority_intd);
|
||||
}
|
||||
|
||||
void v25_common_device::dic0_w(uint8_t d)
|
||||
{
|
||||
write_irqcontrol(INTD0, d);
|
||||
m_priority_intd = d & 0x7;
|
||||
}
|
||||
|
||||
uint8_t v25_common_device::dic1_r()
|
||||
{
|
||||
return read_irqcontrol(INTD1, 7);
|
||||
}
|
||||
|
||||
void v25_common_device::dic1_w(uint8_t d)
|
||||
{
|
||||
write_irqcontrol(INTD1, d);
|
||||
}
|
||||
|
||||
uint8_t v25_common_device::rfm_r()
|
||||
{
|
||||
return m_RFM;
|
||||
|
||||
@ -25,6 +25,7 @@ protected:
|
||||
virtual void machine_start() override ATTR_COLD;
|
||||
|
||||
private:
|
||||
u8 p0_r();
|
||||
void p0_w(u8 data);
|
||||
u8 pt_r();
|
||||
|
||||
@ -42,6 +43,11 @@ void tvdear_state::machine_start()
|
||||
save_item(NAME(m_p0));
|
||||
}
|
||||
|
||||
u8 tvdear_state::p0_r()
|
||||
{
|
||||
return m_p0;
|
||||
}
|
||||
|
||||
void tvdear_state::p0_w(u8 data)
|
||||
{
|
||||
m_p0 = data;
|
||||
@ -59,7 +65,7 @@ void tvdear_state::mem_map(address_map &map)
|
||||
{
|
||||
map(0x00000, 0x07fff).ram();
|
||||
map(0x10000, 0x17fff).ram();
|
||||
map(0x80000, 0xfffff).rom().region("maincpu", 0x080000);
|
||||
map(0x40000, 0xfffff).rom().region("maincpu", 0x040000);
|
||||
}
|
||||
|
||||
void tvdear_state::io_map(address_map &map)
|
||||
@ -174,6 +180,7 @@ void tvdear_state::tvdear(machine_config &config)
|
||||
V25(config, m_maincpu, 16000000); // NEC D70320DGJ-8; XTAL marked 16AKSS5HT
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &tvdear_state::mem_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &tvdear_state::io_map);
|
||||
m_maincpu->p0_in_cb().set(FUNC(tvdear_state::p0_r));
|
||||
m_maincpu->p0_out_cb().set(FUNC(tvdear_state::p0_w));
|
||||
m_maincpu->pt_in_cb().set(FUNC(tvdear_state::pt_r));
|
||||
|
||||
@ -189,4 +196,5 @@ ROM_END
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
CONS( 1995, tvdear, 0, 0, tvdear, tvdear, tvdear_state, empty_init, "Takara", "TV Dear Multi Word Processor", MACHINE_IS_SKELETON | MACHINE_NODEVICE_PRINTER ) // テレビディア マルチワープロ
|
||||
// テレビディア マルチワープロ
|
||||
CONS( 1995, tvdear, 0, 0, tvdear, tvdear, tvdear_state, empty_init, "Takara", "TV Dear Multi Word Processor", MACHINE_IS_SKELETON | MACHINE_NODEVICE_PRINTER )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user