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capcom/cps2.cpp: Support for CPS2 debug DIP switches (#11540)

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* initial working version

* fixed incorrect mapping in memory by using a custom read handler; cleaned up unnecessary port conditions; better comments

* moved read handler directly into the map segment; renamed hardware type device tag

* corrected accidentally moved line break

* switched from native array usage to optional_ioport_array
This commit is contained in:
Damian Rogers 2023-09-11 19:28:19 +09:00 committed by GitHub
parent caab779986
commit 512d319420
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 101 additions and 9 deletions
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110
src/mame/capcom/cps2.cpp
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@ -668,6 +668,7 @@ public:
, m_output(*this, "output") , m_output(*this, "output")
, m_io_in0(*this, "IN0") , m_io_in0(*this, "IN0")
, m_io_in1(*this, "IN1") , m_io_in1(*this, "IN1")
, m_dsw(*this, "DSW%c", 'A')
, m_cps2_dial_type(0) , m_cps2_dial_type(0)
, m_ecofghtr_dial_direction0(0) , m_ecofghtr_dial_direction0(0)
, m_ecofghtr_dial_direction1(0) , m_ecofghtr_dial_direction1(0)
@ -695,7 +696,6 @@ private:
void gigaman2_gfx_reorder(); void gigaman2_gfx_reorder();
void cps2_eeprom_port_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0); void cps2_eeprom_port_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t cps2_qsound_volume_r(); uint16_t cps2_qsound_volume_r();
uint16_t kludge_r();
uint16_t joy_or_paddle_r(); uint16_t joy_or_paddle_r();
uint16_t joy_or_paddle_ecofghtr_r(); uint16_t joy_or_paddle_ecofghtr_r();
TIMER_DEVICE_CALLBACK_MEMBER(cps2_interrupt); TIMER_DEVICE_CALLBACK_MEMBER(cps2_interrupt);
@ -741,6 +741,7 @@ private:
optional_ioport m_io_in0; optional_ioport m_io_in0;
optional_ioport m_io_in1; optional_ioport m_io_in1;
optional_ioport_array<3> m_dsw;
std::unique_ptr<uint16_t[]> m_cps2_buffered_obj; std::unique_ptr<uint16_t[]> m_cps2_buffered_obj;
std::unique_ptr<uint16_t[]> m_gigaman2_dummyqsound_ram; std::unique_ptr<uint16_t[]> m_gigaman2_dummyqsound_ram;
@ -1314,11 +1315,6 @@ uint16_t cps2_state::cps2_qsound_volume_r()
* *
*************************************/ *************************************/
uint16_t cps2_state::kludge_r()
{
return 0xffff;
}
uint16_t cps2_state::joy_or_paddle_r() uint16_t cps2_state::joy_or_paddle_r()
{ {
if (m_readpaddle != 0) if (m_readpaddle != 0)
@ -1393,7 +1389,6 @@ uint16_t cps2_state::joy_or_paddle_ecofghtr_r()
} }
} }
/************************************* /*************************************
* *
* Memory map * Memory map
@ -1417,7 +1412,13 @@ void cps2_state::cps2_map(address_map &map)
map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present. map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present.
map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM
map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup) map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup)
map(0x8040b0, 0x8040b3).r(FUNC(cps2_state::kludge_r)); // Unknown (xmcotaj hangs if this is 0) map(0x8040b0, 0x8040b2).lr8( // DIP switches (only present on development hardware)
NAME([this] (offs_t offset) {
return this->ioport("HW_TYPE")->read() == 0
? (unsigned) 0xff
: m_dsw[offset]->read();
})
);
map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap
map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom
map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom
@ -1456,7 +1457,13 @@ void cps2_state::dead_cps2_map(address_map &map)
map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present. map(0x804030, 0x804031).r(FUNC(cps2_state::cps2_qsound_volume_r)); // Master volume. Also when bit 14=0 addon memory is present, when bit 15=0 network adapter present.
map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM map(0x804040, 0x804041).w(FUNC(cps2_state::cps2_eeprom_port_w)); // EEPROM
map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup) map(0x8040a0, 0x8040a1).nopw(); // Unknown (reset once on startup)
map(0x8040b0, 0x8040b3).r(FUNC(cps2_state::kludge_r)); // Unknown (xmcotaj hangs if this is 0) map(0x8040b0, 0x8040b2).lr8( // DIP switches (only present on development hardware)
NAME([this] (offs_t offset) {
return this->ioport("HW_TYPE")->read() == 0
? (unsigned) 0xff
: m_dsw[offset]->read();
})
);
map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap map(0x8040e0, 0x8040e1).w(FUNC(cps2_state::cps2_objram_bank_w)); // bit 0 = Object ram bank swap
map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom map(0x804100, 0x80413f).w(FUNC(cps2_state::cps1_cps_a_w)).share("cps_a_regs"); // CPS-A custom
map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom map(0x804140, 0x80417f).rw(FUNC(cps2_state::cps1_cps_b_r), FUNC(cps2_state::cps1_cps_b_w)); // CPS-B custom
@ -1543,6 +1550,91 @@ static INPUT_PORTS_START( cps2_4p4b )
PORT_START( "DIGITALVOL" ) PORT_START( "DIGITALVOL" )
PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_VOLUME_DOWN ) PORT_BIT( 0x0001, IP_ACTIVE_HIGH, IPT_VOLUME_DOWN )
PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_VOLUME_UP ) PORT_BIT( 0x0002, IP_ACTIVE_HIGH, IPT_VOLUME_UP )
// Machine configuration for dev hardware with DIPs
PORT_START("HW_TYPE")
PORT_CONFNAME(0x01,0x00,"Hardware")
PORT_CONFSETTING(0x00, "Production")
PORT_CONFSETTING(0x01, "Development (Enable Debug DIPs)")
PORT_START("DSWA")
PORT_DIPNAME( 0x01, 0x01, "1-1" ) PORT_DIPLOCATION("SW1:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPNAME( 0x02, 0x02, "1-2" ) PORT_DIPLOCATION("SW1:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPNAME( 0x04, 0x04, "1-3" ) PORT_DIPLOCATION("SW1:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPNAME( 0x08, 0x08, "1-4" ) PORT_DIPLOCATION("SW1:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPNAME( 0x10, 0x10, "1-5" ) PORT_DIPLOCATION("SW1:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPNAME( 0x20, 0x20, "1-6" ) PORT_DIPLOCATION("SW1:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPNAME( 0x40, 0x40, "1-7" ) PORT_DIPLOCATION("SW1:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPNAME( 0x80, 0x80, "1-8" ) PORT_DIPLOCATION("SW1:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_START("DSWB")
PORT_DIPNAME( 0x01, 0x01, "2-1" ) PORT_DIPLOCATION("SW2:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPNAME( 0x02, 0x02, "2-2" ) PORT_DIPLOCATION("SW2:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPNAME( 0x04, 0x04, "2-3" ) PORT_DIPLOCATION("SW2:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPNAME( 0x08, 0x08, "2-4" ) PORT_DIPLOCATION("SW2:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPNAME( 0x10, 0x10, "2-5" ) PORT_DIPLOCATION("SW2:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPNAME( 0x20, 0x20, "2-6" ) PORT_DIPLOCATION("SW2:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPNAME( 0x40, 0x40, "2-7" ) PORT_DIPLOCATION("SW2:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPNAME( 0x80, 0x80, "2-8" ) PORT_DIPLOCATION("SW2:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_START("DSWC")
PORT_DIPNAME( 0x01, 0x01, "3-1" ) PORT_DIPLOCATION("SW3:1") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
PORT_DIPNAME( 0x02, 0x02, "3-2" ) PORT_DIPLOCATION("SW3:2") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
PORT_DIPNAME( 0x04, 0x04, "3-3" ) PORT_DIPLOCATION("SW3:3") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
PORT_DIPNAME( 0x08, 0x08, "3-4" ) PORT_DIPLOCATION("SW3:4") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
PORT_DIPNAME( 0x10, 0x10, "3-5" ) PORT_DIPLOCATION("SW3:5") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPNAME( 0x20, 0x20, "3-6" ) PORT_DIPLOCATION("SW3:6") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
PORT_DIPNAME( 0x40, 0x40, "3-7" ) PORT_DIPLOCATION("SW3:7") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPNAME( 0x80, 0x80, "3-8" ) PORT_DIPLOCATION("SW3:8") PORT_CONDITION("HW_TYPE", 0x01, EQUALS, 0x01)
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
INPUT_PORTS_END INPUT_PORTS_END
// 4 players and 3 buttons // 4 players and 3 buttons