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hd6301: fix SLP during pending interrupt

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This commit is contained in:
hap 2024-01-23 16:56:47 +01:00
parent 8f5d6f67be
commit 513257a969
6 changed files with 117 additions and 169 deletions
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12
src/devices/cpu/m6800/6800ops.hxx
View File

@ -222,7 +222,10 @@ OP_HANDLER( slp )
{
/* wait for next IRQ (same as waiting of wai) */
m_wai_state |= M6800_SLP;
eat_cycles();
check_irq_lines();
if (m_wai_state & M6800_SLP)
eat_cycles();
}
/* $1b ABA inherent ***** */
@ -428,6 +431,7 @@ OP_HANDLER( rti )
PULLBYTE(A);
PULLWORD(pX);
PULLWORD(pPC);
check_irq_lines();
}
@ -455,13 +459,16 @@ OP_HANDLER( wai )
* hardware stack, then waits for an interrupt.
*/
m_wai_state |= M6800_WAI;
PUSHWORD(pPC);
PUSHWORD(pX);
PUSHBYTE(A);
PUSHBYTE(B);
PUSHBYTE(CC);
check_irq_lines();
if (m_wai_state & M6800_WAI) eat_cycles();
if (m_wai_state & M6800_WAI)
eat_cycles();
}
/* $3f SWI absolute indirect ----- */
@ -472,6 +479,7 @@ OP_HANDLER( swi )
PUSHBYTE(A);
PUSHBYTE(B);
PUSHBYTE(CC);
SEI;
PCD = RM16(0xfffa);
}

31
src/devices/cpu/m6800/m6800.cpp
View File

@ -67,10 +67,6 @@ TODO:
#include "m6800.h"
#include "6800dasm.h"
#define VERBOSE 0
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
#define pPPC m_ppc
#define pPC m_pc
@ -255,7 +251,7 @@ const uint8_t m6800_cpu_device::flags8d[256]= /* decrement */
/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
/* hang in an infinite loop if we hit one */
#define XX 5 // invalid opcode unknown cc
#define XX 4 // invalid opcode unknown cc
const uint8_t m6800_cpu_device::cycles_6800[256] =
{
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
@ -453,16 +449,14 @@ void m6800_cpu_device::WM16(uint32_t Addr, PAIR *p )
}
/* IRQ enter */
void m6800_cpu_device::enter_interrupt(const char *message,uint16_t irq_vector)
void m6800_cpu_device::enter_interrupt(uint16_t irq_vector)
{
int cycles_to_eat = 0;
LOG((message));
if (m_wai_state & (M6800_WAI | M6800_SLP))
if (m_wai_state & M6800_WAI)
{
if (m_wai_state & M6800_WAI)
cycles_to_eat = 4;
m_wai_state &= ~(M6800_WAI | M6800_SLP);
cycles_to_eat = 4;
m_wai_state &= ~M6800_WAI;
}
else
{
@ -485,29 +479,25 @@ void m6800_cpu_device::check_irq_lines()
{
if (m_nmi_pending)
{
if (m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
m_wai_state &= ~M6800_SLP;
m_nmi_pending = false;
enter_interrupt("take NMI\n", 0xfffc);
enter_interrupt(0xfffc);
}
else
{
if (m_irq_state[M6800_IRQ_LINE] != CLEAR_LINE)
{
/* standard IRQ */
if (m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
m_wai_state &= ~M6800_SLP;
if (!(CC & 0x10))
{
standard_irq_callback(M6800_IRQ_LINE, m_pc.w.l);
enter_interrupt("take IRQ1\n", 0xfff8);
enter_interrupt(0xfff8);
}
}
else
if (!(CC & 0x10))
m6800_check_irq2();
check_irq2();
}
}
@ -608,7 +598,6 @@ void m6800_cpu_device::execute_set_input(int irqline, int state)
break;
default:
LOG(("set_irq_line %d,%d\n", irqline, state));
m_irq_state[irqline] = state;
break;
}

4
src/devices/cpu/m6800/m6800.h
View File

@ -100,8 +100,8 @@ protected:
uint32_t RM16(uint32_t Addr );
void WM16(uint32_t Addr, PAIR *p );
void enter_interrupt(const char *message,uint16_t irq_vector);
virtual void m6800_check_irq2() { }
void enter_interrupt(uint16_t irq_vector);
virtual void check_irq2() { }
void check_irq_lines();
virtual void increment_counter(int amount);
virtual void eat_cycles();

219
src/devices/cpu/m6800/m6801.cpp
View File

@ -98,14 +98,6 @@ enum
M6801_TX_STATE_READY
};
/* take interrupt */
#define TAKE_ISI enter_interrupt("take ISI\n",0xfff8)
#define TAKE_ICI enter_interrupt("take ICI\n",0xfff6)
#define TAKE_OCI enter_interrupt("take OCI\n",0xfff4)
#define TAKE_TOI enter_interrupt("take TOI\n",0xfff2)
#define TAKE_SCI enter_interrupt("take SCI\n",0xfff0)
#define TAKE_CMI enter_interrupt("take CMI\n",0xffec)
/* mnemonics for the Timer Control and Status Register bits */
#define TCSR_OLVL 0x01
#define TCSR_IEDG 0x02
@ -138,7 +130,7 @@ enum
/* Note: don't use 0 cycles here for invalid opcodes so that we don't */
/* hang in an infinite loop if we hit one */
#define XX 5 // invalid opcode unknown cc
#define XX 4 // invalid opcode unknown cc
const uint8_t m6801_cpu_device::cycles_6803[256] =
{
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
@ -551,115 +543,119 @@ hd6303y_cpu_device::hd6303y_cpu_device(const machine_config &mconfig, const char
{
}
void m6801_cpu_device::m6800_check_irq2()
bool m6801_cpu_device::check_irq2_ici()
{
if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
{
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
TAKE_ICI;
}
else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF))
{
TAKE_OCI;
}
else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
{
TAKE_TOI;
}
else if (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
return (m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF);
}
bool m6801_cpu_device::check_irq2_oci()
{
return (m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF);
}
bool m6801_cpu_device::check_irq2_toi()
{
return (m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF);
}
bool m6801_cpu_device::check_irq2_sci()
{
return (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) == (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) ||
((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)))
((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)));
}
void m6801_cpu_device::take_irq2(uint16_t irq_vector)
{
m_wai_state &= ~M6800_SLP;
if (!(m_cc & 0x10))
enter_interrupt(irq_vector);
}
void m6801_cpu_device::check_irq2()
{
if (check_irq2_ici())
{
TAKE_SCI;
if (!(m_cc & 0x10))
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
take_irq2(0xfff6);
}
else if (check_irq2_oci())
{
take_irq2(0xfff4);
}
else if (check_irq2_toi())
{
take_irq2(0xfff2);
}
else if (check_irq2_sci())
{
take_irq2(0xfff0);
}
}
void m6801u4_cpu_device::m6800_check_irq2()
void m6801u4_cpu_device::check_irq2()
{
if (((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF)) ||
(m_tcr[1] & m_tsr & TSR_ICF2))
if (check_irq2_ici() || (m_tcr[1] & m_tsr & TSR_ICF2))
{
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
TAKE_ICI;
if (!(m_cc & 0x10))
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
take_irq2(0xfff6);
}
else if (((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF)) ||
(m_tcr[1] & m_tsr & (TSR_OCF2 | TSR_OCF3)))
else if (check_irq2_oci() || (m_tcr[1] & m_tsr & (TSR_OCF2 | TSR_OCF3)))
{
TAKE_OCI;
take_irq2(0xfff4);
}
else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
else if (check_irq2_toi())
{
TAKE_TOI;
take_irq2(0xfff2);
}
else if (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) == (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) ||
((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)))
else if (check_irq2_sci())
{
TAKE_SCI;
take_irq2(0xfff0);
}
}
void hd6301x_cpu_device::m6800_check_irq2()
void hd6301x_cpu_device::check_irq2()
{
if ((m_tcsr & (TCSR_EICI|TCSR_ICF)) == (TCSR_EICI|TCSR_ICF))
if (check_irq2_ici())
{
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
TAKE_ICI;
if (!(m_cc & 0x10))
standard_irq_callback(M6801_TIN_LINE, m_pc.w.l);
take_irq2(0xfff6);
}
else if ((m_tcsr & (TCSR_EOCI|TCSR_OCF)) == (TCSR_EOCI|TCSR_OCF) ||
(m_tcsr2 & (TCSR2_EOCI2|TCSR2_OCF2)) == (TCSR2_EOCI2|TCSR2_OCF2))
else if (check_irq2_oci() || (m_tcsr2 & (TCSR2_EOCI2|TCSR2_OCF2)) == (TCSR2_EOCI2|TCSR2_OCF2))
{
TAKE_OCI;
take_irq2(0xfff4);
}
else if ((m_tcsr & (TCSR_ETOI|TCSR_TOF)) == (TCSR_ETOI|TCSR_TOF))
else if (check_irq2_toi())
{
TAKE_TOI;
take_irq2(0xfff2);
}
else if ((m_tcsr3 & 0xc0) == 0xc0)
{
TAKE_CMI;
take_irq2(0xffec);
}
else if (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) == (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) ||
((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)))
else if (check_irq2_sci())
{
TAKE_SCI;
take_irq2(0xfff0);
}
}
void hd6301y_cpu_device::m6800_check_irq2()
void hd6301y_cpu_device::check_irq2()
{
if ((m_p6csr & 0xc0) == 0xc0)
{
standard_irq_callback(M6801_IS3_LINE, m_pc.w.l);
TAKE_ISI;
if (!(m_cc & 0x10))
standard_irq_callback(M6801_IS3_LINE, m_pc.w.l);
take_irq2(0xfff8);
}
else
hd6301x_cpu_device::m6800_check_irq2();
hd6301x_cpu_device::check_irq2();
}
void m6801_cpu_device::modified_tcsr()
{
m_irq2 = (m_tcsr & (m_tcsr << 3)) & (TCSR_ICF | TCSR_OCF | TCSR_TOF);
}
void m6801u4_cpu_device::modified_tcsr()
{
m6801_cpu_device::modified_tcsr();
if (m_tcr[1] & m_tsr & TSR_ICF2)
m_irq2 |= TCSR_ICF;
if (m_tcr[1] & m_tsr & (TSR_OCF2 | TSR_OCF3))
m_irq2 |= TCSR_OCF;
}
void hd6301x_cpu_device::modified_tcsr()
{
m6801_cpu_device::modified_tcsr();
if ((m_tcsr2 & TCSR2_EOCI2) && (m_tcsr2 & TCSR2_OCF2))
m_irq2 |= TCSR_OCF;
}
void m6801_cpu_device::set_timer_event()
{
@ -715,7 +711,6 @@ void m6801_cpu_device::check_timer_event()
OCH++; // next IRQ point
m_tcsr |= TCSR_OCF;
m_pending_tcsr |= TCSR_OCF;
modified_tcsr();
// if output on P21 is enabled, let's do it
if (m_port_ddr[1] & 2)
@ -736,16 +731,9 @@ void m6801_cpu_device::check_timer_event()
#endif
m_tcsr |= TCSR_TOF;
m_pending_tcsr |= TCSR_TOF;
modified_tcsr();
}
if (m_irq2 & (TCSR_OCF | TCSR_TOF))
{
if (m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
if (!(m_cc & 0x10))
m6800_check_irq2();
}
check_irq2();
// set next event
set_timer_event();
@ -759,7 +747,6 @@ void m6801u4_cpu_device::check_timer_event()
OCH++; // next IRQ point
m_tcsr |= TCSR_OCF;
m_pending_tcsr |= TCSR_OCF;
modified_tcsr();
// TODO: output to P21
}
@ -768,7 +755,6 @@ void m6801u4_cpu_device::check_timer_event()
OC2H++; // next IRQ point
m_tsr |= TSR_OCF2;
m_pending_tsr |= TSR_OCF2;
modified_tcsr();
// TODO: output to P11
}
@ -777,7 +763,6 @@ void m6801u4_cpu_device::check_timer_event()
OC3H++; // next IRQ point
m_tsr |= TSR_OCF3;
m_pending_tsr |= TSR_OCF3;
modified_tcsr();
// TODO: output to P12
}
@ -791,16 +776,9 @@ void m6801u4_cpu_device::check_timer_event()
#endif
m_tcsr |= TCSR_TOF;
m_pending_tcsr |= TCSR_TOF;
modified_tcsr();
}
if (m_irq2 & (TCSR_OCF | TCSR_TOF))
{
if (m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
if (!(m_cc & 0x10))
m6800_check_irq2();
}
check_irq2();
// set next event
set_timer_event();
@ -814,7 +792,6 @@ void hd6301x_cpu_device::check_timer_event()
OCH++; // next IRQ point
m_tcsr |= TCSR_OCF;
m_pending_tcsr |= TCSR_OCF;
modified_tcsr();
// if output on P21 is enabled, let's do it
if (m_tcsr2 & TCSR2_OE1)
@ -830,7 +807,6 @@ void hd6301x_cpu_device::check_timer_event()
OC2H++; // next IRQ point
m_tcsr2 |= TCSR2_OCF2;
m_pending_tcsr2 |= TCSR2_OCF2;
modified_tcsr();
// if output on P25 is enabled, let's do it
if (m_tcsr2 & TCSR2_OE2)
@ -853,16 +829,9 @@ void hd6301x_cpu_device::check_timer_event()
#endif
m_tcsr |= TCSR_TOF;
m_pending_tcsr |= TCSR_TOF;
modified_tcsr();
}
if ((m_irq2 & (TCSR_OCF | TCSR_TOF)) || (m_tcsr3 & 0xc0) == 0xc0)
{
if (m_wai_state & M6800_SLP)
m_wai_state &= ~M6800_SLP;
if (!(m_cc & 0x10))
m6800_check_irq2();
}
check_irq2();
// set next event
set_timer_event();
@ -1269,9 +1238,6 @@ void m6801_cpu_device::execute_set_input(int irqline, int state)
m_tcsr |= TCSR_ICF;
m_pending_tcsr |= TCSR_ICF;
m_input_capture = CT;
modified_tcsr();
if ((m_tcsr & TCSR_EICI) && (m_wai_state & M6800_SLP))
m_wai_state &= ~M6800_SLP;
}
break;
@ -1315,7 +1281,6 @@ void m6801_cpu_device::device_start()
m_p3csr = 0;
m_tcsr = 0;
m_pending_tcsr = 0;
m_irq2 = 0;
m_ram_ctrl = 0;
m_counter.d = 0;
m_output_compare[0].d = 0;
@ -1351,7 +1316,6 @@ void m6801_cpu_device::device_start()
save_item(NAME(m_p3csr));
save_item(NAME(m_tcsr));
save_item(NAME(m_pending_tcsr));
save_item(NAME(m_irq2));
save_item(NAME(m_ram_ctrl));
save_item(NAME(m_counter.d));
@ -1454,7 +1418,6 @@ void m6801_cpu_device::device_reset()
/* TODO: on reset port 2 should be read to determine the operating mode (bits 0-2) */
m_tcsr = 0x00;
m_pending_tcsr = 0x00;
m_irq2 = 0;
CTD = 0x0000;
OCD = 0xffff;
TOD = 0xffff;
@ -2048,7 +2011,7 @@ void hd6301y_cpu_device::p6_csr_w(uint8_t data)
m_p6csr = (m_p6csr & 0x80) | (data & 0x7f);
if (!(m_cc & 0x10) && data & 0x40)
m6800_check_irq2();
check_irq2();
}
@ -2083,9 +2046,7 @@ void m6801_cpu_device::tcsr_w(uint8_t data)
m_tcsr = data | (m_tcsr & 0xe0);
m_pending_tcsr &= m_tcsr;
modified_tcsr();
if (!(m_cc & 0x10))
m6800_check_irq2();
check_irq2();
}
uint8_t m6801_cpu_device::ch_r()
@ -2093,7 +2054,6 @@ uint8_t m6801_cpu_device::ch_r()
if (!(m_pending_tcsr & TCSR_TOF) && !machine().side_effects_disabled())
{
m_tcsr &= ~TCSR_TOF;
modified_tcsr();
}
return m_counter.b.h;
}
@ -2139,7 +2099,6 @@ void m6801_cpu_device::ocrh_w(uint8_t data)
if (!(m_pending_tcsr & TCSR_OCF))
{
m_tcsr &= ~TCSR_OCF;
modified_tcsr();
}
if (m_output_compare[0].b.h != data)
@ -2156,7 +2115,6 @@ void m6801_cpu_device::ocrl_w(uint8_t data)
if (!(m_pending_tcsr & TCSR_OCF))
{
m_tcsr &= ~TCSR_OCF;
modified_tcsr();
}
if (m_output_compare[0].b.l != data)
@ -2171,7 +2129,6 @@ uint8_t m6801_cpu_device::icrh_r()
if (!(m_pending_tcsr & TCSR_ICF) && !machine().side_effects_disabled())
{
m_tcsr &= ~TCSR_ICF;
modified_tcsr();
}
return (m_input_capture >> 0) & 0xff;
}
@ -2192,9 +2149,7 @@ void m6801u4_cpu_device::tcr2_w(uint8_t data)
LOGTIMER("Timer Control Register 2: %02x\n", data);
m_tcr[1] = data & 0xfc;
modified_tcsr();
if (!(m_cc & 0x10))
m6800_check_irq2();
check_irq2();
}
uint8_t m6801u4_cpu_device::tsr_r()
@ -2231,7 +2186,6 @@ void m6801u4_cpu_device::ocr2h_w(uint8_t data)
if (!(m_pending_tsr & (TSR_OCF2 * N)))
{
m_tsr &= ~(TSR_OCF2 * N);
modified_tcsr();
}
if (m_output_compare[N].b.h != data)
@ -2249,7 +2203,6 @@ void m6801u4_cpu_device::ocr2l_w(uint8_t data)
if (!(m_pending_tsr & (TSR_OCF2 * N)))
{
m_tsr &= ~(TSR_OCF2 * N);
modified_tcsr();
}
if (m_output_compare[N].b.l != data)
@ -2277,9 +2230,7 @@ void hd6301x_cpu_device::tcsr2_w(uint8_t data)
data &= TCSR2_OE1 | TCSR2_OE2 | TCSR2_OLVL2 | TCSR2_EOCI2;
m_tcsr2 = data | (m_tcsr2 & TCSR2_OCF2);
m_pending_tcsr2 &= m_tcsr2;
modified_tcsr();
if (!(m_cc & 0x10))
m6800_check_irq2();
check_irq2();
}
uint8_t hd6301x_cpu_device::ocr2h_r()
@ -2299,7 +2250,6 @@ void hd6301x_cpu_device::ocr2h_w(uint8_t data)
if (!(m_pending_tcsr2 & TCSR2_OCF2))
{
m_tcsr2 &= ~TCSR2_OCF2;
modified_tcsr();
}
if (m_output_compare[1].b.h != data)
@ -2316,7 +2266,6 @@ void hd6301x_cpu_device::ocr2l_w(uint8_t data)
if (!(m_pending_tcsr2 & TCSR2_OCF2))
{
m_tcsr2 &= ~TCSR2_OCF2;
modified_tcsr();
}
if (m_output_compare[1].b.l != data)
@ -2576,5 +2525,5 @@ std::unique_ptr<util::disasm_interface> hd6301_cpu_device::create_disassembler()
void hd6301_cpu_device::take_trap()
{
enter_interrupt("take TRAP\n",0xffee);
enter_interrupt(0xffee);
}

18
src/devices/cpu/m6800/m6801.h
View File

@ -150,7 +150,6 @@ protected:
uint8_t m_p3csr; // Port 3 Control/Status Register
uint8_t m_tcsr; // Timer Control and Status Register
uint8_t m_pending_tcsr; // pending IRQ flag for clear IRQflag process
uint8_t m_irq2; // IRQ2 flags
uint8_t m_ram_ctrl;
PAIR m_counter; // free running counter
PAIR m_output_compare[3]; // output compare (MC6801U4 and HD6301X have more than one)
@ -175,12 +174,17 @@ protected:
static const op_func m6803_insn[256];
static const op_func hd63701_insn[256];
virtual void m6800_check_irq2() override;
bool check_irq2_ici();
bool check_irq2_oci();
bool check_irq2_toi();
bool check_irq2_sci();
virtual void check_irq2() override;
void take_irq2(uint16_t irq_vector);
virtual void increment_counter(int amount) override;
virtual void eat_cycles() override;
virtual void cleanup_counters() override;
virtual void modified_tcsr();
virtual void set_timer_event();
virtual void modified_counters();
virtual void check_timer_event();
@ -208,8 +212,7 @@ private:
void m6801u4_io(address_map &map);
void m6801u4_mem(address_map &map);
virtual void m6800_check_irq2() override;
virtual void modified_tcsr() override;
virtual void check_irq2() override;
virtual void set_timer_event() override;
virtual void modified_counters() override;
virtual void check_timer_event() override;
@ -383,8 +386,7 @@ protected:
uint8_t tcsr3_r();
void tcsr3_w(uint8_t data);
virtual void m6800_check_irq2() override;
virtual void modified_tcsr() override;
virtual void check_irq2() override;
virtual void set_timer_event() override;
virtual void modified_counters() override;
virtual void increment_counter(int amount) override;
@ -473,7 +475,7 @@ protected:
virtual uint8_t rcr_r() override;
virtual void rcr_w(uint8_t data) override;
virtual void m6800_check_irq2() override;
virtual void check_irq2() override;
void clear_pending_isf();
uint8_t m_p6csr;

2
src/mame/novag/svip.cpp
View File

@ -13,7 +13,7 @@ chess engine is similar to other HD6301/3Y ones by David Kittinger. The 'sequels
of this portable design (Ruby, Sapphire, ..) are on H8.
Hardware notes:
- Hitachi HD63A03YF (mode 2) @ 9.83MHz
- Hitachi HD6301YF (mode 2) @ 9.83MHz
- 32KB ROM(TC57256AD-12), 2KB RAM(TC5517CFL-20)
- LCD with 4 digits and custom segments, no LCD chip
- RJ-12 port, 24 buttons, piezo