mirror of
https://github.com/holub/mame
synced 2025-04-16 21:44:32 +03:00
Merge pull request #298 from JoakimLarsson/hkv10_2
Added driver for Heurikon HK68K/V10 VME board
This commit is contained in:
R. Belmont
commit
518897bfca
@ -2364,6 +2364,30 @@ if (MACHINES["Z80DART"]~=null) then
|
||||
}
|
||||
end
|
||||
|
||||
---------------------------------------------------
|
||||
--
|
||||
--@src/devices/machine/z80sio.h,MACHINES["Z80SIO"] = true
|
||||
---------------------------------------------------
|
||||
|
||||
if (MACHINES["Z80SIO"]~=null) then
|
||||
files {
|
||||
MAME_DIR .. "src/devices/machine/z80sio.c",
|
||||
MAME_DIR .. "src/devices/machine/z80sio.h",
|
||||
}
|
||||
end
|
||||
|
||||
---------------------------------------------------
|
||||
--
|
||||
--@src/devices/machine/z80scc.h,MACHINES["Z80SCC"] = true
|
||||
---------------------------------------------------
|
||||
|
||||
if (MACHINES["Z80SCC"]~=null) then
|
||||
files {
|
||||
MAME_DIR .. "src/devices/machine/z80scc.c",
|
||||
MAME_DIR .. "src/devices/machine/z80scc.h",
|
||||
}
|
||||
end
|
||||
|
||||
---------------------------------------------------
|
||||
--
|
||||
--@src/devices/machine/z80dma.h,MACHINES["Z80DMA"] = true
|
||||
|
||||
@ -546,6 +546,8 @@ MACHINES["X76F100"] = true
|
||||
MACHINES["YM2148"] = true
|
||||
MACHINES["Z80CTC"] = true
|
||||
MACHINES["Z80DART"] = true
|
||||
MACHINES["Z80SIO"] = true
|
||||
MACHINES["Z80SCC"] = true
|
||||
MACHINES["Z80DMA"] = true
|
||||
MACHINES["Z80PIO"] = true
|
||||
MACHINES["Z80STI"] = true
|
||||
@ -736,6 +738,7 @@ function linkProjects_mame_mess(_target, _subtarget)
|
||||
"heathkit",
|
||||
"hec2hrp",
|
||||
"hegener",
|
||||
"heurikon",
|
||||
"hitachi",
|
||||
"homebrew",
|
||||
"homelab",
|
||||
@ -1635,6 +1638,11 @@ files {
|
||||
MAME_DIR .. "src/mess/drivers/interact.c",
|
||||
}
|
||||
|
||||
createMESSProjects(_target, _subtarget, "heurikon")
|
||||
files {
|
||||
MAME_DIR .. "src/mess/drivers/hk68v10.c",
|
||||
}
|
||||
|
||||
createMESSProjects(_target, _subtarget, "intel")
|
||||
files {
|
||||
MAME_DIR .. "src/mess/drivers/basic52.c",
|
||||
|
||||
1850
src/devices/machine/z80scc.c
Normal file
1850
src/devices/machine/z80scc.c
Normal file
File diff suppressed because it is too large
Load Diff
738
src/devices/machine/z80scc.h
Normal file
738
src/devices/machine/z80scc.h
Normal file
@ -0,0 +1,738 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Joakim Larsson Edstrom
|
||||
/***************************************************************************
|
||||
|
||||
Z80-SCC Serial Communications Controller emulation
|
||||
|
||||
****************************************************************************
|
||||
_____ _____ _____ _____
|
||||
AD1 1|* \_/ |40 AD0 D1 1|* \_/ |40 D0
|
||||
AD3 2| |39 AD2 D3 2| |39 D2
|
||||
AD5 3| |38 AD4 D5 3| |38 D4
|
||||
AD7 4| |37 AD6 D7 4| |37 D6
|
||||
_INT 5| |36 _DS _INT 5| |36 _RD
|
||||
IEO 6| |35 _AS IEO 6| |35 _WR
|
||||
IEI 7| |34 R/_W IEI 7| |34 B/_A
|
||||
_INTACK 8| |33 _CS0 _INTACK 8| |33 _CE
|
||||
VCC 9| |32 CS1 VCC 9| |32 C/_D
|
||||
_W//REQA 10| |31 GND _W//REQA 10| |31 GND
|
||||
_SYNCA 11| Z8030 |30 _W/_REQ _SYNCA 11| Z8530 |30 _W/_REQB
|
||||
_RTxCA 12| Z80C30 |29 _SYNCB _RTxCA 12| Z85C30 |29 _SYNCB
|
||||
RxDA 13| Z80230 |28 _RTxCB RxDA 13| Z85230 |28 _RTxCB
|
||||
_TRxCA 14| |27 RxDB _TRxCA 14| |27 RxDB
|
||||
TxDA 15| |26 _TRxCB TxDA 15| |26 _TRxCB
|
||||
_DTR//REQA 16| |25 TxDB _DTR//REQA 16| |25 TxDB
|
||||
_RTSA 17| |24 _DTR/_REQB _RTSA 17| |24 _DTR/_REQB
|
||||
_CTSA 18| |23 _RTSB _CTSA 18| |23 _RTSB
|
||||
_DCDA 19| |22 _CTSB _DCDA 19| |22 _CTSB
|
||||
PCLK 20|_____________|21 _DCDB PCLK 20|_____________|21 _DCDB
|
||||
ZBUS Universal Bus
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __Z80SCC_H__
|
||||
#define __Z80SCC_H__
|
||||
|
||||
#include "emu.h"
|
||||
#include "z80sio.h"
|
||||
#include "cpu/z80/z80daisy.h"
|
||||
|
||||
//**************************************************************************
|
||||
// DEVICE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MCFG_Z80SCC_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, Z80SCC, _clock) \
|
||||
MCFG_Z80SCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_SCC8530_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, SCC8530N, _clock) \
|
||||
MCFG_Z80SCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_Z80SCC_OFFSETS(_rxa, _txa, _rxb, _txb) \
|
||||
z80scc_device::configure_channels(*device, _rxa, _txa, _rxb, _txb);
|
||||
|
||||
// Port A callbacks
|
||||
#define MCFG_Z80SCC_OUT_TXDA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txda_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_DTRA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_dtra_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RTSA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rtsa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_WRDYA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_wrdya_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_SYNCA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_synca_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
// Port B callbacks
|
||||
#define MCFG_Z80SCC_OUT_TXDB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_DTRB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_dtrb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RTSB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rtsb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_WRDYB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_wrdyb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_SYNCB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_syncb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_INT_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_int_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RXDRQA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rxdrqa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_TXDRQA_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdrqa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_RXDRQB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_rxdrqb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SCC_OUT_TXDRQB_CB(_devcb) \
|
||||
devcb = &z80scc_device::set_out_txdrqb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> z80scc_channel
|
||||
|
||||
class z80scc_device;
|
||||
|
||||
class z80scc_channel : public z80sio_channel
|
||||
{
|
||||
friend class z80scc_device;
|
||||
|
||||
public:
|
||||
z80scc_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
// device_serial_interface overrides
|
||||
virtual void tra_callback();
|
||||
virtual void tra_complete();
|
||||
virtual void rcv_callback();
|
||||
virtual void rcv_complete();
|
||||
|
||||
// read register handlers
|
||||
UINT8 do_sccreg_rr0();
|
||||
UINT8 do_sccreg_rr1();
|
||||
UINT8 do_sccreg_rr2();
|
||||
UINT8 do_sccreg_rr3();
|
||||
UINT8 do_sccreg_rr4();
|
||||
UINT8 do_sccreg_rr5();
|
||||
UINT8 do_sccreg_rr6();
|
||||
UINT8 do_sccreg_rr7();
|
||||
UINT8 do_sccreg_rr8();
|
||||
UINT8 do_sccreg_rr9();
|
||||
UINT8 do_sccreg_rr10();
|
||||
UINT8 do_sccreg_rr11();
|
||||
UINT8 do_sccreg_rr12();
|
||||
UINT8 do_sccreg_rr13();
|
||||
UINT8 do_sccreg_rr14();
|
||||
UINT8 do_sccreg_rr15();
|
||||
|
||||
// write register handlers
|
||||
void do_sccreg_wr0(UINT8 data);
|
||||
void do_sccreg_wr1(UINT8 data);
|
||||
void do_sccreg_wr2(UINT8 data);
|
||||
void do_sccreg_wr3(UINT8 data);
|
||||
void do_sccreg_wr4(UINT8 data);
|
||||
void do_sccreg_wr5(UINT8 data);
|
||||
void do_sccreg_wr6(UINT8 data);
|
||||
void do_sccreg_wr7(UINT8 data);
|
||||
void do_sccreg_wr8(UINT8 data);
|
||||
void do_sccreg_wr9(UINT8 data);
|
||||
void do_sccreg_wr10(UINT8 data);
|
||||
void do_sccreg_wr11(UINT8 data);
|
||||
void do_sccreg_wr12(UINT8 data);
|
||||
void do_sccreg_wr13(UINT8 data);
|
||||
void do_sccreg_wr14(UINT8 data);
|
||||
void do_sccreg_wr15(UINT8 data);
|
||||
|
||||
UINT8 control_read();
|
||||
void control_write(UINT8 data);
|
||||
|
||||
UINT8 data_read();
|
||||
void data_write(UINT8 data);
|
||||
|
||||
void receive_data(UINT8 data);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( write_rx );
|
||||
DECLARE_WRITE_LINE_MEMBER( cts_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dcd_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( ri_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rxc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( txc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( sync_w );
|
||||
|
||||
int m_rxc;
|
||||
int m_txc;
|
||||
|
||||
// Register state
|
||||
// read registers enum
|
||||
#if 0 //defined by z80sio.h
|
||||
UINT8 m_rr0; // REG_RR0_STATUS
|
||||
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
|
||||
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
|
||||
#endif
|
||||
UINT8 m_rr3; // REG_RR3_INTERUPPT_PEND
|
||||
UINT8 m_rr4; // REG_RR4_WR4_OR_RR0
|
||||
UINT8 m_rr5; // REG_RR5_WR5_OR_RR0
|
||||
UINT8 m_rr6; // REG_RR6_LSB_OR_RR2
|
||||
UINT8 m_rr7; // REG_RR7_MSB_OR_RR3
|
||||
UINT8 m_rr8; // REG_RR8_RECEIVE_DATA
|
||||
UINT8 m_rr9; // REG_RR9_WR3_OR_RR13
|
||||
UINT8 m_rr10; // REG_RR10_MISC_STATUS
|
||||
UINT8 m_rr11; // REG_RR11_WR10_OR_RR15
|
||||
UINT8 m_rr12; // REG_RR12_LO_TIME_CONST
|
||||
UINT8 m_rr13; // REG_RR13_HI_TIME_CONST
|
||||
UINT8 m_rr14; // REG_RR14_WR7_OR_R10
|
||||
UINT8 m_rr15; // REG_RR15_WR15_EXT_STAT
|
||||
|
||||
// write registers enum
|
||||
#if 0 //defined by z80sio.h
|
||||
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
|
||||
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
|
||||
UINT8 m_wr2; // REG_WR2_INT_VECTOR
|
||||
UINT8 m_wr3; // REG_WR3_RX_CONTROL
|
||||
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
|
||||
UINT8 m_wr5; // REG_WR5_TX_CONTROL
|
||||
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
|
||||
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
|
||||
#endif
|
||||
UINT8 m_wr8; // REG_WR8_TRANSMIT_DATA
|
||||
UINT8 m_wr9; // REG_WR9_MASTER_INT_CTRL
|
||||
UINT8 m_wr10; // REG_WR10_MSC_RX_TX_CTRL
|
||||
UINT8 m_wr11; // REG_WR11_CLOCK_MODES
|
||||
UINT8 m_wr12; // REG_WR12_LO_BAUD_GEN
|
||||
UINT8 m_wr13; // REG_WR13_HI_BAUD_GEN
|
||||
UINT8 m_wr14; // REG_WR14_MISC_CTRL
|
||||
UINT8 m_wr15; // REG_WR15_EXT_ST_INT_CTRL
|
||||
|
||||
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
INT_TRANSMIT = 0,
|
||||
INT_EXTERNAL,
|
||||
INT_RECEIVE,
|
||||
INT_SPECIAL
|
||||
};
|
||||
|
||||
// Read registers
|
||||
enum
|
||||
{
|
||||
REG_RR0_STATUS = 0, // SIO
|
||||
REG_RR1_SPEC_RCV_COND = 1, // SIO
|
||||
REG_RR2_INTERRUPT_VECT = 2, // SIO
|
||||
REG_RR3_INTERUPPT_PEND = 3,
|
||||
REG_RR4_WR4_OR_RR0 = 4,
|
||||
REG_RR5_WR5_OR_RR0 = 5,
|
||||
REG_RR6_LSB_OR_RR2 = 6,
|
||||
REG_RR7_MSB_OR_RR3 = 7,
|
||||
REG_RR8_RECEIVE_DATA = 8,
|
||||
REG_RR9_WR3_OR_RR13 = 9,
|
||||
REG_RR10_MISC_STATUS = 10,
|
||||
REG_RR11_WR10_OR_RR15 = 11,
|
||||
REG_RR12_LO_TIME_CONST = 12,
|
||||
REG_RR13_HI_TIME_CONST = 13,
|
||||
REG_RR14_WR7_OR_R10 = 14,
|
||||
REG_RR15_WR15_EXT_STAT = 15
|
||||
};
|
||||
|
||||
// Write registers
|
||||
enum
|
||||
{
|
||||
REG_WR0_COMMAND_REGPT = 0, // SIO
|
||||
REG_WR1_INT_DMA_ENABLE = 1, // SIO
|
||||
REG_WR2_INT_VECTOR = 2, // SIO
|
||||
REG_WR3_RX_CONTROL = 3, // SIO
|
||||
REG_WR4_RX_TX_MODES = 4, // SIO
|
||||
REG_WR5_TX_CONTROL = 5, // SIO
|
||||
REG_WR6_SYNC_OR_SDLC_A = 6, // SIO
|
||||
REG_WR7_SYNC_OR_SDLC_F = 7, // SIO
|
||||
REG_WR8_TRANSMIT_DATA = 8,
|
||||
REG_WR9_MASTER_INT_CTRL = 9,
|
||||
REG_WR10_MSC_RX_TX_CTRL = 10,
|
||||
REG_WR11_CLOCK_MODES = 11,
|
||||
REG_WR12_LO_BAUD_GEN = 12,
|
||||
REG_WR13_HI_BAUD_GEN = 13,
|
||||
REG_WR14_MISC_CTRL = 14,
|
||||
REG_WR15_EXT_ST_INT_CTRL= 15
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit
|
||||
RR0_ZC = 0x02, // SCC bit
|
||||
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
|
||||
RR0_DCD = 0x08, // SIO
|
||||
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
|
||||
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
|
||||
RR0_CTS = 0x20, // SIO bit
|
||||
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
|
||||
RR0_BREAK_ABORT = 0x80 // SIO bit, not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RR1_ALL_SENT = 0x01, // SIO/SCC bit
|
||||
RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported
|
||||
RR1_PARITY_ERROR = 0x10, // SIO/SCC bits
|
||||
RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits
|
||||
RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits
|
||||
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{ // TODO: overload SIO functionality
|
||||
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
|
||||
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
|
||||
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
|
||||
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
|
||||
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
|
||||
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
|
||||
RR3_CHANA_EXT_IP = 0x08,
|
||||
RR3_CHANA_TX_IP = 0x10,
|
||||
RR3_CHANA_RX_IP = 0x20
|
||||
};
|
||||
|
||||
enum // Universal Bus WR0 commands for 85X30
|
||||
{
|
||||
WR0_REGISTER_MASK = 0x07,
|
||||
WR0_COMMAND_MASK = 0x38, // COMMANDS
|
||||
WR0_NULL = 0x00, // 0 0 0
|
||||
WR0_POINT_HIGH = 0x08, // 0 0 1
|
||||
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
|
||||
WR0_SEND_ABORT = 0x18, // 0 1 1
|
||||
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
|
||||
WR0_RESET_TX_INT = 0x28, // 1 0 1
|
||||
WR0_ERROR_RESET = 0x30, // 1 1 0
|
||||
WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
|
||||
WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
|
||||
WR0_CRC_RESET_NULL = 0x00, // 0 0
|
||||
WR0_CRC_RESET_RX = 0x40, // 0 1
|
||||
WR0_CRC_RESET_TX = 0x80, // 1 0
|
||||
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1
|
||||
};
|
||||
|
||||
enum // ZBUS WR0 commands or 80X30
|
||||
{
|
||||
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
|
||||
WR0_Z_NULL_1 = 0x00, // 0 0 0
|
||||
WR0_Z_NULL_2 = 0x08, // 0 0 1
|
||||
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
|
||||
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
|
||||
WR0_Z_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
|
||||
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
|
||||
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
|
||||
WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
|
||||
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
|
||||
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
|
||||
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR1_EXT_INT_ENABLE = 0x01,
|
||||
WR1_TX_INT_ENABLE = 0x02,
|
||||
WR1_STATUS_VECTOR = 0x04,
|
||||
WR1_RX_INT_MODE_MASK = 0x18,
|
||||
WR1_RX_INT_DISABLE = 0x00,
|
||||
WR1_RX_INT_FIRST = 0x08,
|
||||
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
|
||||
WR1_RX_INT_ALL = 0x18,
|
||||
WR1_WRDY_ON_RX_TX = 0x20, // not supported
|
||||
WR1_WRDY_FUNCTION = 0x40, // not supported
|
||||
WR1_WRDY_ENABLE = 0x80 // not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR2_DATA_XFER_INT = 0x00, // not supported
|
||||
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
|
||||
WR2_DATA_XFER_DMA = 0x02, // not supported
|
||||
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
|
||||
WR2_DATA_XFER_MASK = 0x03, // not supported
|
||||
WR2_PRIORITY = 0x04, // not supported
|
||||
WR2_MODE_8085_1 = 0x00, // not supported
|
||||
WR2_MODE_8085_2 = 0x08, // not supported
|
||||
WR2_MODE_8086_8088 = 0x10, // not supported
|
||||
WR2_MODE_ILLEGAL = 0x18, // not supported
|
||||
WR2_MODE_MASK = 0x18, // not supported
|
||||
WR2_VECTORED_INT = 0x20, // not supported
|
||||
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR3_RX_ENABLE = 0x01,
|
||||
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
|
||||
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
|
||||
WR3_RX_CRC_ENABLE = 0x08, // not supported
|
||||
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
|
||||
WR3_AUTO_ENABLES = 0x20,
|
||||
WR3_RX_WORD_LENGTH_MASK = 0xc0,
|
||||
WR3_RX_WORD_LENGTH_5 = 0x00,
|
||||
WR3_RX_WORD_LENGTH_7 = 0x40,
|
||||
WR3_RX_WORD_LENGTH_6 = 0x80,
|
||||
WR3_RX_WORD_LENGTH_8 = 0xc0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR4_PARITY_ENABLE = 0x01,
|
||||
WR4_PARITY_EVEN = 0x02,
|
||||
WR4_STOP_BITS_MASK = 0x0c,
|
||||
WR4_STOP_BITS_1 = 0x04,
|
||||
WR4_STOP_BITS_1_5 = 0x08, // not supported
|
||||
WR4_STOP_BITS_2 = 0x0c,
|
||||
WR4_SYNC_MODE_MASK = 0x30, // not supported
|
||||
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
|
||||
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
|
||||
WR4_SYNC_MODE_SDLC = 0x20, // not supported
|
||||
WR4_SYNC_MODE_EXT = 0x30, // not supported
|
||||
WR4_CLOCK_RATE_MASK = 0xc0,
|
||||
WR4_CLOCK_RATE_X1 = 0x00,
|
||||
WR4_CLOCK_RATE_X16 = 0x40,
|
||||
WR4_CLOCK_RATE_X32 = 0x80,
|
||||
WR4_CLOCK_RATE_X64 = 0xc0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR5_TX_CRC_ENABLE = 0x01, // not supported
|
||||
WR5_RTS = 0x02,
|
||||
WR5_CRC16 = 0x04, // not supported
|
||||
WR5_TX_ENABLE = 0x08,
|
||||
WR5_SEND_BREAK = 0x10,
|
||||
WR5_TX_WORD_LENGTH_MASK = 0x60,
|
||||
WR5_TX_WORD_LENGTH_5 = 0x00,
|
||||
WR5_TX_WORD_LENGTH_6 = 0x40,
|
||||
WR5_TX_WORD_LENGTH_7 = 0x20,
|
||||
WR5_TX_WORD_LENGTH_8 = 0x60,
|
||||
WR5_DTR = 0x80
|
||||
};
|
||||
|
||||
/* SCC specifics */
|
||||
enum
|
||||
{
|
||||
WR9_CMD_MASK = 0xC0,
|
||||
WR9_CMD_NORESET = 0x00,
|
||||
WR9_CMD_CHNB_RESET = 0x40,
|
||||
WR9_CMD_CHNA_RESET = 0x80,
|
||||
WR9_CMD_HW_RESET = 0xC0,
|
||||
WR9_BIT_VIS = 0x01,
|
||||
WR9_BIT_NV = 0x02,
|
||||
WR9_BIT_DLC = 0x04,
|
||||
WR9_BIT_MIE = 0x08,
|
||||
WR9_BIT_SHSL = 0x10,
|
||||
WR9_BIT_IACK = 0x20
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR11_RCVCLK_TYPE = 0x80,
|
||||
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
|
||||
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
|
||||
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
|
||||
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
|
||||
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
|
||||
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
|
||||
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
|
||||
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
|
||||
WR11_TRACLK_SRC_BR = 0x10, // 1 0
|
||||
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
|
||||
WR11_TRXC_DIRECTION = 0x04,
|
||||
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
|
||||
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
|
||||
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
|
||||
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
|
||||
WR11_TRXSRC_SRC_DPLL = 0x03, // 1 1
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR14_DPLL_CMD_MASK = 0xe0, // Command
|
||||
WR14_CMD_NULL = 0x00, // 0 0 0
|
||||
WR14_CMD_ESM = 0x20, // 0 0 1
|
||||
WR14_CMD_RMC = 0x40, // 0 1 0
|
||||
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
|
||||
WR14_CMD_SS_BGR = 0x80, // 1 0 0
|
||||
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
|
||||
WR14_CMD_SET_FM = 0xc0, // 1 1 0
|
||||
WR14_CMD_SET_NRZI = 0xe0 // 1 1 1
|
||||
};
|
||||
|
||||
void update_serial();
|
||||
void set_dtr(int state);
|
||||
void set_rts(int state);
|
||||
|
||||
int get_clock_mode();
|
||||
void update_rts();
|
||||
stop_bits_t get_stop_bits();
|
||||
int get_rx_word_length();
|
||||
int get_tx_word_length();
|
||||
|
||||
// receiver state
|
||||
UINT8 m_rx_data_fifo[3]; // receive data FIFO
|
||||
UINT8 m_rx_error_fifo[3]; // receive error FIFO
|
||||
UINT8 m_rx_error; // current receive error
|
||||
int m_rx_fifo; // receive FIFO pointer
|
||||
|
||||
int m_rx_clock; // receive clock pulse count
|
||||
int m_rx_first; // first character received
|
||||
int m_rx_break; // receive break condition
|
||||
UINT8 m_rx_rr0_latch; // read register 0 latched
|
||||
|
||||
int m_rxd;
|
||||
int m_ri; // ring indicator latch
|
||||
int m_cts; // clear to send latch
|
||||
int m_dcd; // data carrier detect latch
|
||||
|
||||
// transmitter state
|
||||
UINT8 m_tx_data; // transmit data register
|
||||
int m_tx_clock; // transmit clock pulse count
|
||||
|
||||
int m_dtr; // data terminal ready
|
||||
int m_rts; // request to send
|
||||
|
||||
// synchronous state
|
||||
UINT16 m_sync; // sync character
|
||||
|
||||
// int m_index;
|
||||
z80scc_device *m_uart;
|
||||
|
||||
// SCC specifics
|
||||
int m_ph; // Point high command to access regs 08-0f
|
||||
UINT8 m_zc;
|
||||
};
|
||||
|
||||
|
||||
// ======================> z80scc_device
|
||||
|
||||
class z80scc_device : public device_t
|
||||
,public device_z80daisy_interface
|
||||
{
|
||||
friend class z80scc_channel;
|
||||
|
||||
public:
|
||||
// construction/destruction
|
||||
z80scc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
|
||||
z80scc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
template<class _Object> static devcb_base &set_out_txda_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_txda_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_dtra_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_rtsa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_wrdya_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_wrdya_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_synca_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_synca_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_txdb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtrb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_dtrb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_rtsb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_wrdyb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_wrdyb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_syncb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_syncb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_int_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_int_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rxdrqa_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_rxdrqa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdrqa_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_txdrqa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rxdrqb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_rxdrqb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdrqb_callback(device_t &device, _Object object) { return downcast<z80scc_device &>(device).m_out_txdrqb_cb.set_callback(object); }
|
||||
|
||||
static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb)
|
||||
{
|
||||
z80scc_device &dev = downcast<z80scc_device &>(device);
|
||||
dev.m_rxca = rxa;
|
||||
dev.m_txca = txa;
|
||||
dev.m_rxcb = rxb;
|
||||
dev.m_txcb = txb;
|
||||
}
|
||||
|
||||
DECLARE_READ8_MEMBER( cd_ba_r );
|
||||
DECLARE_WRITE8_MEMBER( cd_ba_w );
|
||||
DECLARE_READ8_MEMBER( ba_cd_r );
|
||||
DECLARE_WRITE8_MEMBER( ba_cd_w );
|
||||
|
||||
DECLARE_READ8_MEMBER( da_r ) { return m_chanA->data_read(); }
|
||||
DECLARE_WRITE8_MEMBER( da_w ) { m_chanA->data_write(data); }
|
||||
DECLARE_READ8_MEMBER( db_r ) { return m_chanB->data_read(); }
|
||||
DECLARE_WRITE8_MEMBER( db_w ) { m_chanB->data_write(data); }
|
||||
|
||||
DECLARE_READ8_MEMBER( ca_r ) { return m_chanA->control_read(); }
|
||||
DECLARE_WRITE8_MEMBER( ca_w ) { m_chanA->control_write(data); }
|
||||
DECLARE_READ8_MEMBER( cb_r ) { return m_chanB->control_read(); }
|
||||
DECLARE_WRITE8_MEMBER( cb_w ) { m_chanB->control_write(data); }
|
||||
|
||||
// interrupt acknowledge
|
||||
int m1_r();
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { m_chanA->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { m_chanB->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { m_chanA->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { m_chanB->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { m_chanB->rxc_w(state); m_chanB->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( synca_w ) { m_chanA->sync_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { m_chanB->sync_w(state); }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
// device_z80daisy_interface overrides
|
||||
virtual int z80daisy_irq_state();
|
||||
virtual int z80daisy_irq_ack();
|
||||
virtual void z80daisy_irq_reti();
|
||||
|
||||
// internal interrupt management
|
||||
void check_interrupts();
|
||||
void reset_interrupts();
|
||||
void trigger_interrupt(int index, int state);
|
||||
int get_channel_index(z80scc_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
|
||||
|
||||
// Variants in the SCC family
|
||||
enum
|
||||
{
|
||||
TYPE_Z80SCC = 0x001,
|
||||
TYPE_SCC8030 = 0x002,
|
||||
TYPE_SCC80C30 = 0x004,
|
||||
TYPE_SCC80230 = 0x008,
|
||||
TYPE_SCC8530 = 0x010,
|
||||
TYPE_SCC85C30 = 0x020,
|
||||
TYPE_SCC85230 = 0x040,
|
||||
TYPE_SCC85233 = 0x080,
|
||||
TYPE_SCC8523L = 0x100
|
||||
};
|
||||
|
||||
#define SET_NMOS ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC8530 )
|
||||
#define SET_CMOS ( z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC85C30 )
|
||||
#define SET_ESCC ( z80scc_device::TYPE_SCC80230 | z80scc_device::TYPE_SCC85230 | z80scc_device::TYPE_SCC8523L )
|
||||
#define SET_EMSCC z80scc_device::TYPE_SCC85233
|
||||
#define SET_Z80X30 ( z80scc_device::TYPE_SCC8030 | z80scc_device::TYPE_SCC80C30 | z80scc_device::TYPE_SCC80230 )
|
||||
#define SET_Z85X3X ( z80scc_device::TYPE_SCC8530 | z80scc_device::TYPE_SCC85C30 | z80scc_device::TYPE_SCC85230 \
|
||||
| z80scc_device::TYPE_SCC8523L | z80scc_device::TYPE_SCC85233 )
|
||||
|
||||
enum
|
||||
{
|
||||
CHANNEL_A = 0,
|
||||
CHANNEL_B
|
||||
};
|
||||
|
||||
required_device<z80scc_channel> m_chanA;
|
||||
required_device<z80scc_channel> m_chanB;
|
||||
|
||||
// internal state
|
||||
int m_rxca;
|
||||
int m_txca;
|
||||
int m_rxcb;
|
||||
int m_txcb;
|
||||
|
||||
devcb_write_line m_out_txda_cb;
|
||||
devcb_write_line m_out_dtra_cb;
|
||||
devcb_write_line m_out_rtsa_cb;
|
||||
devcb_write_line m_out_wrdya_cb;
|
||||
devcb_write_line m_out_synca_cb;
|
||||
|
||||
devcb_write_line m_out_txdb_cb;
|
||||
devcb_write_line m_out_dtrb_cb;
|
||||
devcb_write_line m_out_rtsb_cb;
|
||||
devcb_write_line m_out_wrdyb_cb;
|
||||
devcb_write_line m_out_syncb_cb;
|
||||
|
||||
devcb_write_line m_out_int_cb;
|
||||
devcb_write_line m_out_rxdrqa_cb;
|
||||
devcb_write_line m_out_txdrqa_cb;
|
||||
devcb_write_line m_out_rxdrqb_cb;
|
||||
devcb_write_line m_out_txdrqb_cb;
|
||||
|
||||
int m_int_state[8]; // interrupt state
|
||||
|
||||
int m_variant;
|
||||
};
|
||||
|
||||
class scc8030_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc8030_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc80C30_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc80C30_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc80230_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc80230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc8530_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc8530_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc85C30_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc85C30_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc85230_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc85230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc85233_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc85233_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class scc8523L_device : public z80scc_device
|
||||
{
|
||||
public :
|
||||
scc8523L_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type Z80SCC;
|
||||
extern const device_type Z80SCC_CHANNEL;
|
||||
extern const device_type SCC8030;
|
||||
extern const device_type SCC80C30;
|
||||
extern const device_type SCC80230;
|
||||
extern const device_type SCC8530N; // remove trailing N when 8530scc.c is fully replaced and removed
|
||||
extern const device_type SCC85C30;
|
||||
extern const device_type SCC85230;
|
||||
extern const device_type SCC85233;
|
||||
extern const device_type SCC8523L;
|
||||
|
||||
#endif // __Z80SCC_H__
|
||||
1393
src/devices/machine/z80sio.c
Normal file
1393
src/devices/machine/z80sio.c
Normal file
File diff suppressed because it is too large
Load Diff
534
src/devices/machine/z80sio.h
Normal file
534
src/devices/machine/z80sio.h
Normal file
@ -0,0 +1,534 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Curt Coder, Joakim Larsson Edstrom
|
||||
/***************************************************************************
|
||||
|
||||
Z80-SIO Serial Input/Output
|
||||
|
||||
****************************************************************************
|
||||
_____ _____ _____ _____
|
||||
D1 1|* \_/ |40 D0 _/ |40 D0 _/ |40 D0
|
||||
D3 2| |39 D2 : |39 D2 : |39 D2
|
||||
D5 3| |38 D4 : |38 D4 : |38 D4
|
||||
D7 4| |37 D6 : |37 D6 : |37 D6
|
||||
_INT 5| |36 _IORQ : |36 _IORQ : |36 _IORQ
|
||||
IEO 6| |35 _CE : |35 _CE : |35 _CE
|
||||
IEI 7| |34 B/_A : |34 B/_A : |34 B/_A
|
||||
_M1 8| |33 C/_D : |33 C/_D : |33 C/_D
|
||||
VDD 9| DIP40 |32 _RD : DIP40 |32 _RD : DIP40 |32 _RD
|
||||
_W//RDYA 10| Z80 |31 GND : Z80 |31 GND : Z80 |31 GND
|
||||
_SYNCA 11| SIO/0 |30 _W/_RDYB: SIO/1 |30 _W/_RDYB: SIO/2 |30 _W/_RDYB
|
||||
RxDA 12| |29 _SYNCB : |29 _SYNCB : |29 _SYNCB
|
||||
_RxCA 13| |28 RxDB : |28 RxDB : |28 _RxCB
|
||||
_TxCA 14| |27 _RxTxCB : |27 _RxCB : |27 _TxCB
|
||||
TxDA 15| |26 TxDB : |26 _TxCB : |26 TxDB
|
||||
_DTRA 16| |25 _DTRB : |25 TxD_B : |25 _DTRB
|
||||
_RTSA 17| |24 _RTSB : |24 _RTSB : |24 _RTSB
|
||||
_CTSA 18| |23 _CTSB : |23 _CTSB : |23 _CTSB
|
||||
_DCDA 19| |22 _DCDB : |22 _DCDB : |22 _DCDB
|
||||
CLK 20|_____________|21 _RESET :_______|21 _RESET :_______|21 _RESET
|
||||
|
||||
*I *I
|
||||
*I N O *I O
|
||||
N D D D D / D D D D R N D D D D D D D D R*C
|
||||
T 7 5 3 1 C 0 2 4 6 Q T 7 5 3 1 0 2 4 6 Q E
|
||||
+----------------------+ +----------------------+
|
||||
IEI|34 22| *CE IEI|6 5 4 3 2 1 44 42 40|B/ *A
|
||||
IEO|35 21| B/ *A IEO|8 43 41 |C/ *D
|
||||
*M1| | C/ *D *M1|9 37|*RD
|
||||
+5v| | *RD +5V|10 36|GND
|
||||
*W/ *RDYA| QFP44 | GND *W/ *RDYA|11 PLCC44 35|*W/ *RDYB
|
||||
N/C| Z80 SIO/3 | N/C *SYNCA|12 Z80 SIO/4 34|*SYNCB
|
||||
*SYNCA| Z804C43 | *W/ *RDYB RxDA|13 33|RxDB
|
||||
RxDA| | *SYNCB *RxCA|14 32|*RxCB
|
||||
*RxCA|42 | RxDB *TxCA|15 31|*TxCB
|
||||
*TxCA|43 1 1 | *RxCB TxDA| 19 21 23 25 30|TxDB
|
||||
TxDA`. 2 3 4 5 6 7 8 9 0 1 | *TxCB N/C|18 20 22 24 26 29|N/C
|
||||
`--------------------+ +----------------------+
|
||||
*D*R*C*D C*R*D*C*R*D*T *D*R*C*D C*R*D*C*R*D N
|
||||
T T T C L E C*T T T x T T T C L E C T T T /
|
||||
R S S D K S D S S R D R S S D K S D S S R C
|
||||
A A A A E B B B B B A A A A E B B B B
|
||||
T T
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __Z80SIO_H__
|
||||
#define __Z80SIO_H__
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80daisy.h"
|
||||
|
||||
//**************************************************************************
|
||||
// DEVICE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MCFG_Z80SIO_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, Z80SIO, _clock) \
|
||||
MCFG_Z80SIO_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_Z80SIO_OFFSETS(_rxa, _txa, _rxb, _txb) \
|
||||
z80sio_device::configure_channels(*device, _rxa, _txa, _rxb, _txb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_TXDA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_txda_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_DTRA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_dtra_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_RTSA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_rtsa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_WRDYA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_wrdya_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_SYNCA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_synca_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_TXDB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_txdb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_DTRB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_dtrb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_RTSB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_rtsb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_WRDYB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_wrdyb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_SYNCB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_syncb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_INT_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_int_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_RXDRQA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_rxdrqa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_TXDRQA_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_txdrqa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_RXDRQB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_rxdrqb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_Z80SIO_OUT_TXDRQB_CB(_devcb) \
|
||||
devcb = &z80sio_device::set_out_txdrqb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> z80sio_channel
|
||||
|
||||
class z80sio_device;
|
||||
|
||||
class z80sio_channel : public device_t,
|
||||
public device_serial_interface
|
||||
{
|
||||
friend class z80sio_device;
|
||||
|
||||
public:
|
||||
z80sio_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
// device_serial_interface overrides
|
||||
virtual void tra_callback();
|
||||
virtual void tra_complete();
|
||||
virtual void rcv_callback();
|
||||
virtual void rcv_complete();
|
||||
|
||||
// read register handlers
|
||||
UINT8 do_sioreg_rr0();
|
||||
UINT8 do_sioreg_rr1();
|
||||
UINT8 do_sioreg_rr2();
|
||||
|
||||
// write register handlers
|
||||
void do_sioreg_wr0(UINT8 data);
|
||||
void do_sioreg_wr0_resets(UINT8 data);
|
||||
void do_sioreg_wr1(UINT8 data);
|
||||
void do_sioreg_wr2(UINT8 data);
|
||||
void do_sioreg_wr3(UINT8 data);
|
||||
void do_sioreg_wr4(UINT8 data);
|
||||
void do_sioreg_wr5(UINT8 data);
|
||||
void do_sioreg_wr6(UINT8 data);
|
||||
void do_sioreg_wr7(UINT8 data);
|
||||
|
||||
UINT8 control_read();
|
||||
void control_write(UINT8 data);
|
||||
|
||||
UINT8 data_read();
|
||||
void data_write(UINT8 data);
|
||||
|
||||
void receive_data(UINT8 data);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( write_rx );
|
||||
DECLARE_WRITE_LINE_MEMBER( cts_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dcd_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( ri_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rxc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( txc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( sync_w );
|
||||
|
||||
int m_rxc;
|
||||
int m_txc;
|
||||
|
||||
// Register state
|
||||
// read registers enum
|
||||
UINT8 m_rr0; // REG_RR0_STATUS
|
||||
UINT8 m_rr1; // REG_RR1_SPEC_RCV_COND
|
||||
UINT8 m_rr2; // REG_RR2_INTERRUPT_VECT
|
||||
// write registers enum
|
||||
UINT8 m_wr0; // REG_WR0_COMMAND_REGPT
|
||||
UINT8 m_wr1; // REG_WR1_INT_DMA_ENABLE
|
||||
UINT8 m_wr2; // REG_WR2_INT_VECTOR
|
||||
UINT8 m_wr3; // REG_WR3_RX_CONTROL
|
||||
UINT8 m_wr4; // REG_WR4_RX_TX_MODES
|
||||
UINT8 m_wr5; // REG_WR5_TX_CONTROL
|
||||
UINT8 m_wr6; // REG_WR6_SYNC_OR_SDLC_A
|
||||
UINT8 m_wr7; // REG_WR7_SYNC_OR_SDLC_F
|
||||
|
||||
int m_variant; // Set in device
|
||||
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
INT_TRANSMIT = 0,
|
||||
INT_EXTERNAL,
|
||||
INT_RECEIVE,
|
||||
INT_SPECIAL
|
||||
};
|
||||
|
||||
// Read registers
|
||||
enum
|
||||
{
|
||||
REG_RR0_STATUS = 0,
|
||||
REG_RR1_SPEC_RCV_COND = 1,
|
||||
REG_RR2_INTERRUPT_VECT = 2,
|
||||
};
|
||||
|
||||
// Write registers
|
||||
enum
|
||||
{
|
||||
REG_WR0_COMMAND_REGPT = 0,
|
||||
REG_WR1_INT_DMA_ENABLE = 1,
|
||||
REG_WR2_INT_VECTOR = 2,
|
||||
REG_WR3_RX_CONTROL = 3,
|
||||
REG_WR4_RX_TX_MODES = 4,
|
||||
REG_WR5_TX_CONTROL = 5,
|
||||
REG_WR6_SYNC_OR_SDLC_A = 6,
|
||||
REG_WR7_SYNC_OR_SDLC_F = 7,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RR0_RX_CHAR_AVAILABLE = 0x01,
|
||||
RR0_INTERRUPT_PENDING = 0x02,
|
||||
RR0_TX_BUFFER_EMPTY = 0x04,
|
||||
RR0_DCD = 0x08,
|
||||
RR0_SYNC_HUNT = 0x10,
|
||||
RR0_CTS = 0x20,
|
||||
RR0_TX_UNDERRUN = 0x40,
|
||||
RR0_BREAK_ABORT = 0x80
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
RR1_ALL_SENT = 0x01,
|
||||
RR1_RESIDUE_CODE_MASK = 0x0e,
|
||||
RR1_PARITY_ERROR = 0x10,
|
||||
RR1_RX_OVERRUN_ERROR = 0x20,
|
||||
RR1_CRC_FRAMING_ERROR = 0x40,
|
||||
RR1_END_OF_FRAME = 0x80
|
||||
};
|
||||
|
||||
enum
|
||||
{ // TODO: overload SIO functionality
|
||||
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
|
||||
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
|
||||
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
|
||||
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR0_REGISTER_MASK = 0x07,
|
||||
WR0_COMMAND_MASK = 0x38,
|
||||
WR0_NULL = 0x00,
|
||||
WR0_SEND_ABORT = 0x08, // not supported
|
||||
WR0_RESET_EXT_STATUS = 0x10,
|
||||
WR0_CHANNEL_RESET = 0x18,
|
||||
WR0_ENABLE_INT_NEXT_RX = 0x20,
|
||||
WR0_RESET_TX_INT = 0x28, // not supported
|
||||
WR0_ERROR_RESET = 0x30,
|
||||
WR0_RETURN_FROM_INT = 0x38, // not supported
|
||||
WR0_CRC_RESET_CODE_MASK = 0xc0, // not supported
|
||||
WR0_CRC_RESET_NULL = 0x00, // not supported
|
||||
WR0_CRC_RESET_RX = 0x40, // not supported
|
||||
WR0_CRC_RESET_TX = 0x80, // not supported
|
||||
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR1_EXT_INT_ENABLE = 0x01,
|
||||
WR1_TX_INT_ENABLE = 0x02,
|
||||
WR1_STATUS_VECTOR = 0x04,
|
||||
WR1_RX_INT_MODE_MASK = 0x18,
|
||||
WR1_RX_INT_DISABLE = 0x00,
|
||||
WR1_RX_INT_FIRST = 0x08,
|
||||
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
|
||||
WR1_RX_INT_ALL = 0x18,
|
||||
WR1_WRDY_ON_RX_TX = 0x20, // not supported
|
||||
WR1_WRDY_FUNCTION = 0x40, // not supported
|
||||
WR1_WRDY_ENABLE = 0x80 // not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR2_DATA_XFER_INT = 0x00, // not supported
|
||||
WR2_DATA_XFER_DMA_INT = 0x01, // not supported
|
||||
WR2_DATA_XFER_DMA = 0x02, // not supported
|
||||
WR2_DATA_XFER_ILLEGAL = 0x03, // not supported
|
||||
WR2_DATA_XFER_MASK = 0x03, // not supported
|
||||
WR2_PRIORITY = 0x04, // not supported
|
||||
WR2_MODE_8085_1 = 0x00, // not supported
|
||||
WR2_MODE_8085_2 = 0x08, // not supported
|
||||
WR2_MODE_8086_8088 = 0x10, // not supported
|
||||
WR2_MODE_ILLEGAL = 0x18, // not supported
|
||||
WR2_MODE_MASK = 0x18, // not supported
|
||||
WR2_VECTORED_INT = 0x20, // not supported
|
||||
WR2_PIN10_SYNDETB_RTSB = 0x80 // not supported
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR3_RX_ENABLE = 0x01,
|
||||
WR3_SYNC_CHAR_LOAD_INHIBIT= 0x02, // not supported
|
||||
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
|
||||
WR3_RX_CRC_ENABLE = 0x08, // not supported
|
||||
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
|
||||
WR3_AUTO_ENABLES = 0x20,
|
||||
WR3_RX_WORD_LENGTH_MASK = 0xc0,
|
||||
WR3_RX_WORD_LENGTH_5 = 0x00,
|
||||
WR3_RX_WORD_LENGTH_7 = 0x40,
|
||||
WR3_RX_WORD_LENGTH_6 = 0x80,
|
||||
WR3_RX_WORD_LENGTH_8 = 0xc0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR4_PARITY_ENABLE = 0x01,
|
||||
WR4_PARITY_EVEN = 0x02,
|
||||
WR4_STOP_BITS_MASK = 0x0c,
|
||||
WR4_STOP_BITS_1 = 0x04,
|
||||
WR4_STOP_BITS_1_5 = 0x08, // not supported
|
||||
WR4_STOP_BITS_2 = 0x0c,
|
||||
WR4_SYNC_MODE_MASK = 0x30, // not supported
|
||||
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
|
||||
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
|
||||
WR4_SYNC_MODE_SDLC = 0x20, // not supported
|
||||
WR4_SYNC_MODE_EXT = 0x30, // not supported
|
||||
WR4_CLOCK_RATE_MASK = 0xc0,
|
||||
WR4_CLOCK_RATE_X1 = 0x00,
|
||||
WR4_CLOCK_RATE_X16 = 0x40,
|
||||
WR4_CLOCK_RATE_X32 = 0x80,
|
||||
WR4_CLOCK_RATE_X64 = 0xc0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
WR5_TX_CRC_ENABLE = 0x01, // not supported
|
||||
WR5_RTS = 0x02,
|
||||
WR5_CRC16 = 0x04, // not supported
|
||||
WR5_TX_ENABLE = 0x08,
|
||||
WR5_SEND_BREAK = 0x10,
|
||||
WR5_TX_WORD_LENGTH_MASK = 0x60,
|
||||
WR5_TX_WORD_LENGTH_5 = 0x00,
|
||||
WR5_TX_WORD_LENGTH_6 = 0x40,
|
||||
WR5_TX_WORD_LENGTH_7 = 0x20,
|
||||
WR5_TX_WORD_LENGTH_8 = 0x60,
|
||||
WR5_DTR = 0x80
|
||||
};
|
||||
|
||||
void update_serial();
|
||||
void update_rts();
|
||||
void set_dtr(int state);
|
||||
void set_rts(int state);
|
||||
|
||||
int get_clock_mode();
|
||||
stop_bits_t get_stop_bits();
|
||||
int get_rx_word_length();
|
||||
int get_tx_word_length();
|
||||
|
||||
// receiver state
|
||||
UINT8 m_rx_data_fifo[3]; // receive data FIFO
|
||||
UINT8 m_rx_error_fifo[3]; // receive error FIFO
|
||||
UINT8 m_rx_error; // current receive error
|
||||
int m_rx_fifo; // receive FIFO pointer
|
||||
|
||||
int m_rx_clock; // receive clock pulse count
|
||||
int m_rx_first; // first character received
|
||||
int m_rx_break; // receive break condition
|
||||
UINT8 m_rx_rr0_latch; // read register 0 latched
|
||||
|
||||
int m_rxd;
|
||||
int m_sh; // sync hunt
|
||||
int m_cts; // clear to send latch
|
||||
int m_dcd; // data carrier detect latch
|
||||
|
||||
// transmitter state
|
||||
UINT8 m_tx_data; // transmit data register
|
||||
int m_tx_clock; // transmit clock pulse count
|
||||
|
||||
int m_dtr; // data terminal ready
|
||||
int m_rts; // request to send
|
||||
|
||||
// synchronous state
|
||||
UINT16 m_sync; // sync character
|
||||
|
||||
int m_index;
|
||||
z80sio_device *m_uart;
|
||||
};
|
||||
|
||||
|
||||
// ======================> z80sio_device
|
||||
|
||||
class z80sio_device : public device_t,
|
||||
public device_z80daisy_interface
|
||||
{
|
||||
friend class z80sio_channel;
|
||||
|
||||
public:
|
||||
// construction/destruction
|
||||
z80sio_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
|
||||
z80sio_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
template<class _Object> static devcb_base &set_out_txda_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txda_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_dtra_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rtsa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_wrdya_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_wrdya_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_synca_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_synca_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txdb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtrb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_dtrb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rtsb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_wrdyb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_wrdyb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_syncb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_syncb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_int_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_int_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rxdrqa_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rxdrqa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdrqa_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txdrqa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rxdrqb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_rxdrqb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_txdrqb_callback(device_t &device, _Object object) { return downcast<z80sio_device &>(device).m_out_txdrqb_cb.set_callback(object); }
|
||||
|
||||
static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb)
|
||||
{
|
||||
z80sio_device &dev = downcast<z80sio_device &>(device);
|
||||
dev.m_rxca = rxa;
|
||||
dev.m_txca = txa;
|
||||
dev.m_rxcb = rxb;
|
||||
dev.m_txcb = txb;
|
||||
}
|
||||
|
||||
DECLARE_READ8_MEMBER( cd_ba_r );
|
||||
DECLARE_WRITE8_MEMBER( cd_ba_w );
|
||||
DECLARE_READ8_MEMBER( ba_cd_r );
|
||||
DECLARE_WRITE8_MEMBER( ba_cd_w );
|
||||
|
||||
DECLARE_READ8_MEMBER( da_r ) { return m_chanA->data_read(); }
|
||||
DECLARE_WRITE8_MEMBER( da_w ) { m_chanA->data_write(data); }
|
||||
DECLARE_READ8_MEMBER( db_r ) { return m_chanB->data_read(); }
|
||||
DECLARE_WRITE8_MEMBER( db_w ) { m_chanB->data_write(data); }
|
||||
|
||||
DECLARE_READ8_MEMBER( ca_r ) { return m_chanA->control_read(); }
|
||||
DECLARE_WRITE8_MEMBER( ca_w ) { m_chanA->control_write(data); }
|
||||
DECLARE_READ8_MEMBER( cb_r ) { return m_chanB->control_read(); }
|
||||
DECLARE_WRITE8_MEMBER( cb_w ) { m_chanB->control_write(data); }
|
||||
|
||||
// interrupt acknowledge
|
||||
int m1_r();
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { m_chanA->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { m_chanB->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { m_chanA->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { m_chanB->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { m_chanB->rxc_w(state); m_chanB->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( synca_w ) { m_chanA->sync_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { m_chanB->sync_w(state); }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
// device_z80daisy_interface overrides
|
||||
virtual int z80daisy_irq_state();
|
||||
virtual int z80daisy_irq_ack();
|
||||
virtual void z80daisy_irq_reti();
|
||||
|
||||
// internal interrupt management
|
||||
void check_interrupts();
|
||||
void reset_interrupts();
|
||||
void trigger_interrupt(int index, int state);
|
||||
int get_channel_index(z80sio_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
|
||||
|
||||
enum
|
||||
{
|
||||
TYPE_Z80SIO,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
CHANNEL_A = 0,
|
||||
CHANNEL_B
|
||||
};
|
||||
|
||||
required_device<z80sio_channel> m_chanA;
|
||||
required_device<z80sio_channel> m_chanB;
|
||||
|
||||
// internal state
|
||||
int m_rxca;
|
||||
int m_txca;
|
||||
int m_rxcb;
|
||||
int m_txcb;
|
||||
|
||||
devcb_write_line m_out_txda_cb;
|
||||
devcb_write_line m_out_dtra_cb;
|
||||
devcb_write_line m_out_rtsa_cb;
|
||||
devcb_write_line m_out_wrdya_cb;
|
||||
devcb_write_line m_out_synca_cb;
|
||||
|
||||
devcb_write_line m_out_txdb_cb;
|
||||
devcb_write_line m_out_dtrb_cb;
|
||||
devcb_write_line m_out_rtsb_cb;
|
||||
devcb_write_line m_out_wrdyb_cb;
|
||||
devcb_write_line m_out_syncb_cb;
|
||||
|
||||
devcb_write_line m_out_int_cb;
|
||||
devcb_write_line m_out_rxdrqa_cb;
|
||||
devcb_write_line m_out_txdrqa_cb;
|
||||
devcb_write_line m_out_rxdrqb_cb;
|
||||
devcb_write_line m_out_txdrqb_cb;
|
||||
|
||||
int m_int_state[8]; // interrupt state
|
||||
|
||||
int m_variant;
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type Z80SIO;
|
||||
extern const device_type Z80SIO_CHANNEL;
|
||||
#endif
|
||||
@ -2614,6 +2614,7 @@ eacc
|
||||
argo
|
||||
applix
|
||||
mzr8105
|
||||
hk68v10
|
||||
fccpu1
|
||||
68ksbc
|
||||
lcmate2
|
||||
|
||||
371
src/mess/drivers/hk68v10.c
Normal file
371
src/mess/drivers/hk68v10.c
Normal file
@ -0,0 +1,371 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Joakim Larsson Edstrom
|
||||
/***************************************************************************
|
||||
*
|
||||
* Heurikon HK68/V10 6U SBC driver, initially derived from hk68v10.c
|
||||
*
|
||||
* 21/08/2015
|
||||
*
|
||||
* I baught this board from http://www.retrotechnology.com without documentation.
|
||||
* It has a Motorola 68010 CPU @ 10MHz and two 2764 EPROMS with HBUG firmware
|
||||
* The board is very populated and suitable to run a real server OS supported by
|
||||
* FPU,MMU and DMA controller chips. The firmware supports SCSI, Centronics/FPI
|
||||
* and a serial port. I have not found so much on the FPI interface yet and it is
|
||||
* possibly Heurikon specific. There is also a Heurikon Multibus board called
|
||||
* HK68/M10 for which I might add support from specs, however would need a ROM
|
||||
* to verify.
|
||||
*
|
||||
* ||
|
||||
* || ||
|
||||
* ||||--||
|
||||
* ||||--||
|
||||
* || ||____________________________________________________________ ___
|
||||
* || | | | 12 PALs 68/V-... | | | | | |_| |
|
||||
* || | | 2 x | |74 |74 |74 |74 | | | |
|
||||
* || | | 74273 | VS4-01 VM4-00 | 244 573 645 645 | | |
|
||||
* \==||| |SCSI | | VS3-00 VM3-03 | | | | | | | |
|
||||
* ||| | | | VS2-01 VM2-02 |___|___|___|___| | | |
|
||||
* || |NCR | | VS1-00 VM1-01 | | | | | | |
|
||||
* || | 8530| 2 x | VBX-00 VDB-00 |74 |74 |74 | | |VME|
|
||||
* || | | 74245 | VI1-00 VI2-00 | 244 641 245 | | |
|
||||
* || | | | (90 deg ccw) | | | | | |P1 |
|
||||
* SCSI || |_____| |_____________________|___|___|___| | | |
|
||||
* port || | | _________ _________________________________ | | |
|
||||
* || | | | || |74 |PAL | | | | |
|
||||
* || | | | || 5 x | 244 MP2| 2 x | | | |
|
||||
* || |CIO | | MC68881 || 74373 | | -00| 74646| | | |
|
||||
* || |paral| | FPU || | | | | | | |
|
||||
* || |Z8536| |_________||_________________|_ _| | | |_| |
|
||||
* ||| | | | | | | ------------ |___|
|
||||
* /==||| | | | | | | | 3 PALs | |
|
||||
* FSM || | | | MC68010 | MC68451 | MC68450 | | MP1-00 | |
|
||||
* 1234 || | | | CPU | MMU | DMA | | MX2-00 | |
|
||||
* LEDs || |-----| |_________|__________|_________|__| MX1-01 |---|
|
||||
* || | | ____ ____ ---| |__________|74 |
|
||||
* \==||| | | | | | | |74| 4 x | 3 PALs |145|
|
||||
* ||| |SCC | | | | | |804 74245 | CS3-00 |___|
|
||||
* FPI || |seria| |U12 | |U23 | | | | CS2-00 | |
|
||||
* paralell |Z8530| |HBUG| |HBUG| | | | CS1-00 | |___
|
||||
* port || | | | | | | ---_---------------|__________| _| |
|
||||
* || | | | | | | |MTTLDL|MDLDM| 2 x |___________ | | |
|
||||
* ||| | | |____|_|____|_|____40|TTL75|74280| | | | |
|
||||
* /==||| | || |19. | | | | | |_____| | | | |
|
||||
* \==||| |_____||75 |6608|16 |20 |74|74| ______| 9 x 4 | | | |
|
||||
* ||| +--------+|173| MHz| MHz | MHz| 74 08| | | RAM chips| | |VME|
|
||||
* || | ||___|____|_____|____|__|__||74 74 | on SIL | | | |
|
||||
* || | 2 x || | | |259|257 boards | | |P2 |
|
||||
* || | SIL || 12 PALs 90 deg ccw|74| -______- | | | |
|
||||
* || | boards || |240 | | | | | | |
|
||||
* || | with 2 || BER-00 FPI-01 | | |74 74 | | | | |
|
||||
* Serial|| | DIP16 || AC4-00 ARB-01 |__|___|138|257 | | | |
|
||||
* port || | surf || AC3-00 INT-00 |______| | | | |
|
||||
* || | mounted|| AC2-01 IAK-00 | | | | | | |
|
||||
* || | chips || AC1-01 PAS-01 |74 |74| | | | |
|
||||
* || | each || RFS-01 |590|257 | | | |
|
||||
* ||| | || RCT-01 | | | | |_| |
|
||||
* /==||| +--------+|__________________________|___|__|__________| |___|
|
||||
* || ||------------------------------------------------------------+-+
|
||||
* ||||--||
|
||||
* ||||--||
|
||||
* ||
|
||||
*
|
||||
* History of Heurikon
|
||||
*---------------------
|
||||
* The company was founded 1972 as cellar company. Heurikon was aquired
|
||||
* 1989 by Computer Products, 1990 by Artesyn and finally in 2005 by Emerson
|
||||
* Electric who consilidated it fully by 2009 and closed the office.
|
||||
*
|
||||
* Misc links about Heurikon and this board:
|
||||
* http://www.heurikon.com/
|
||||
* http://www.nytimes.com/1992/01/07/business/company-news-briefs.html
|
||||
* http://bitsavers.informatik.uni-stuttgart.de/pdf/heurikon/brochures/HK68_V10_Brochure.pdf
|
||||
* http://bitsavers.informatik.uni-stuttgart.de/pdf/heurikon/Heurikon_UNIX_System_V_and_V.2_Reference_Guide_Apr87.pdf
|
||||
*
|
||||
* Address Map from the UNIX Ref Guide
|
||||
* --------------------------------------------------------------------------
|
||||
* Address Range Memory Space (physical) Notes
|
||||
* --------------------------------------------------------------------------
|
||||
* 0xffffff (top of memory)
|
||||
* 0xffc200 0xffc220 Sky FFP 68881 FPU
|
||||
* 0xff8000 ... MCT Reel-to-reel tape (V10) VME
|
||||
* 0xff0000 0xff0100 Tapemaster(00B0,00B1) Reel-to-reel tape (M10) Multibus
|
||||
* Ethernet(0010,0011)
|
||||
* 0xff0000 (base of bus I/O)
|
||||
*
|
||||
* 0xfea000 SCC8530 device
|
||||
* 0xfe9000 offset 6 seems also to be 2 access registers, ie register offset + data pairs
|
||||
* 0xfe8000 offset E reading single byte
|
||||
* 0xfe4000 front LED:s? or move ROM from 0x0 to 0xfc0000...
|
||||
* 0xfe2000 cleared
|
||||
* 0xfe0000 HK68 On-card I/O MMU, DMAC, SCC, SCSI
|
||||
* 0xfc0000 HK68 ROM (128K) Hbug monitor
|
||||
* 0xf00000 (reserved)
|
||||
* (shared memory and logical area
|
||||
* for shared text.)
|
||||
* 0x800000 (Twilight Zone) (top of /dev/mem)
|
||||
* 0x7c0000 (reserved)
|
||||
* 0x780000 8 Chnl serial Expn(1-4) (CDC)
|
||||
* HK68 (1-15) VRTX
|
||||
* MLZ-93 (1-4) CP/M Shell
|
||||
* 0x700000
|
||||
* (open)
|
||||
* 0x*00000 (maxmeml)
|
||||
* RAM (bus) (optional)
|
||||
* 0x200000 (top of 2 meg RAM)
|
||||
* RAM (bus) (optional)
|
||||
* 0x100000 (top of 1 meg RAM)
|
||||
* User RAM
|
||||
* 0x001000 UNIX Kernel
|
||||
* Exception Vectors
|
||||
* 0x000000 (bottom of memory)
|
||||
* --------------------------------------------------------------------------
|
||||
*
|
||||
* Interrupt sources M10/V10
|
||||
* ----------------------------------------------------------
|
||||
* Description Device Lvl IRQ VME board
|
||||
* /Board Vector Address
|
||||
* ----------------------------------------------------------
|
||||
* On board Sources M10/V10
|
||||
*
|
||||
* Off board Sources (other VME boards)
|
||||
* EXOS Ethernet 5 4
|
||||
* TapeMaster Reel-to-Reel Tape 3
|
||||
* MCT Reel-to-Reel Tape 5
|
||||
* CDC MB1031 Serial Expansion 2 2
|
||||
* IT 2190 SMD Interface 1 3
|
||||
* IT 3200 SMD Interface 3
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
* DMAC Channel Assignments
|
||||
* ----------------------------------------------------------
|
||||
* Channel M10 V10
|
||||
* ----------------------------------------------------------
|
||||
* 0 SCSI SCSI
|
||||
* 1 Streamer (P3) n/a
|
||||
* 2 n/a n/a
|
||||
* 3 SBX-FDIO n/a
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
* TODO:
|
||||
* - Dump the ROMs (DONE)
|
||||
* - Setup a working address map (DONE)
|
||||
* - Fix terminal for HBUG (DONE)
|
||||
* - Add VME bus driver
|
||||
* - Add DMA/MMU devices
|
||||
* - Add CIO port
|
||||
* - ADD SCSI controller device
|
||||
* - dump PALs and describe descrete logic
|
||||
* - Setup BAUD generation correctly, (eg find that x32 divider)
|
||||
* - Add LED:s
|
||||
* - Add Jumpers and strap areas
|
||||
* - Find and Boot Heurikon Unix from a SCSI device
|
||||
* - Support that optional 68881 FPU
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/z80scc.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
#include "machine/clock.h"
|
||||
|
||||
#define LOG(x) /* x */
|
||||
|
||||
#define BAUDGEN_CLOCK XTAL_19_6608MHz /* Raltron */
|
||||
/*
|
||||
*/
|
||||
#define SCC_CLOCK (BAUDGEN_CLOCK / 128) /* This will give prompt */
|
||||
//#define SCC_CLOCK (BAUDGEN_CLOCK / 4) /* This is correct */
|
||||
class hk68v10_state : public driver_device
|
||||
{
|
||||
public:
|
||||
hk68v10_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device (mconfig, type, tag),
|
||||
m_maincpu (*this, "maincpu")
|
||||
,m_sccterm(*this, "scc")
|
||||
// ,m_cart(*this, "exp_rom1")
|
||||
{
|
||||
}
|
||||
|
||||
DECLARE_READ16_MEMBER (bootvect_r);
|
||||
DECLARE_WRITE16_MEMBER (bootvect_w);
|
||||
DECLARE_READ16_MEMBER (vme_a24_r);
|
||||
DECLARE_WRITE16_MEMBER (vme_a24_w);
|
||||
DECLARE_READ16_MEMBER (vme_a16_r);
|
||||
DECLARE_WRITE16_MEMBER (vme_a16_w);
|
||||
virtual void machine_start ();
|
||||
virtual void machine_reset ();
|
||||
DECLARE_WRITE_LINE_MEMBER (write_sccterm_clock);
|
||||
|
||||
protected:
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<scc8530_device> m_sccterm;
|
||||
|
||||
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
|
||||
UINT16 *m_sysrom;
|
||||
UINT16 m_sysram[4];
|
||||
};
|
||||
|
||||
static ADDRESS_MAP_START (hk68v10_mem, AS_PROGRAM, 16, hk68v10_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just durin reset */
|
||||
AM_RANGE (0x000000, 0x000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
|
||||
AM_RANGE (0x000008, 0x1fffff) AM_RAM /* 2 Mb RAM */
|
||||
AM_RANGE (0xFC0000, 0xFC3fff) AM_ROM /* System EPROM Area 16Kb HBUG */
|
||||
AM_RANGE (0xFC4000, 0xFDffff) AM_ROM /* System EPROM Area an additional 112Kb for System ROM */
|
||||
AM_RANGE (0xFE9000, 0xFE9009) AM_RAM //AM_DEVREADWRITE8("scc", scc8530_device, ba_cd_r, ba_cd_w, 0xffff) /* Z80-PIO? */
|
||||
AM_RANGE (0xFEA000, 0xFEA001) AM_DEVREADWRITE8("scc", scc8530_device, ca_r, ca_w, 0xff00) /* Dual serial port Z80-SCC */
|
||||
AM_RANGE (0xFEA002, 0xFEA003) AM_DEVREADWRITE8("scc", scc8530_device, cb_r, cb_w, 0xff00) /* Dual serial port Z80-SCC */
|
||||
AM_RANGE (0xFEA004, 0xFEA005) AM_DEVREADWRITE8("scc", scc8530_device, da_r, da_w, 0xff00) /* Dual serial port Z80-SCC */
|
||||
AM_RANGE (0xFEA006, 0xFEA007) AM_DEVREADWRITE8("scc", scc8530_device, db_r, db_w, 0xff00) /* Dual serial port Z80-SCC */
|
||||
//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
|
||||
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START (hk68v10)
|
||||
INPUT_PORTS_END
|
||||
|
||||
/* Start it up */
|
||||
void hk68v10_state::machine_start ()
|
||||
{
|
||||
LOG (logerror ("machine_start\n"));
|
||||
|
||||
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
|
||||
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x0fc0000);
|
||||
}
|
||||
|
||||
/* Support CPU resets
|
||||
|
||||
TODO: Investigate why the user need two 'softreset' commands for the below to work. Eg F3 + F11 + F3 + F11
|
||||
If only one 'softreset' is given the reset PC gets the RAM content, not the intended ROM vector.
|
||||
Race conditions? Wrong call order in memory system? Debugger prefetch accesses? Better way to to this?
|
||||
*/
|
||||
void hk68v10_state::machine_reset ()
|
||||
{
|
||||
LOG (logerror ("machine_reset\n"));
|
||||
|
||||
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
|
||||
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
|
||||
m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0x0fc0000);
|
||||
}
|
||||
|
||||
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xfc0000 to 0x0 at reset*/
|
||||
/*
|
||||
Right after HBUG reset the bootvector is masked by RAM:
|
||||
FC001C: move.w #$700, $fe4000.l
|
||||
FC0024: move.l #$0, $0.l # <- zeroing the reset vector
|
||||
FC002E: move.l #$0, $4.l # There is for sure some hardware mapping going in here
|
||||
*/
|
||||
READ16_MEMBER (hk68v10_state::bootvect_r){
|
||||
//LOG (logerror ("bootvect_r %s\n", m_sysrom != &m_sysram[0] ? "as reset" : "as swapped"));
|
||||
return m_sysrom [offset];
|
||||
}
|
||||
|
||||
WRITE16_MEMBER (hk68v10_state::bootvect_w){
|
||||
LOG (logerror("bootvect_w offset %08x, mask %08x, data %04x\n", offset, mem_mask, data));
|
||||
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
|
||||
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
|
||||
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Dummy VME access methods until the VME bus device is ready for use */
|
||||
READ16_MEMBER (hk68v10_state::vme_a24_r){
|
||||
LOG (logerror ("vme_a24_r\n"));
|
||||
return (UINT16) 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER (hk68v10_state::vme_a24_w){
|
||||
LOG (logerror ("vme_a24_w\n"));
|
||||
}
|
||||
|
||||
READ16_MEMBER (hk68v10_state::vme_a16_r){
|
||||
LOG (logerror ("vme_16_r\n"));
|
||||
return (UINT16) 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER (hk68v10_state::vme_a16_w){
|
||||
LOG (logerror ("vme_a16_w\n"));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial port clock source depends on the CPU clock and divider settings
|
||||
* HBUG has a control byte that needs to be patched accordingly:
|
||||
*
|
||||
* CPU clock SCC clock Baud rate offset 0x0b value
|
||||
* 10 Mhz 4.9152MHz 9600 15
|
||||
* 10 Mhz 4.9152MHz 19200 55
|
||||
* 12 Mhz 4.9152MHz 9600 16
|
||||
* 12 Mhz 4.9152MHz 19200 56
|
||||
*
|
||||
* Configuration word detail:
|
||||
* D15-D8 reserved ( = 0 )
|
||||
* D7(MSB) = 0
|
||||
* D6 = 0 for console default 9600 baud
|
||||
* D6 = 1 for console default 19,200 baud
|
||||
* D5,D4,D3,D2 = 0101 for 4.9152 Mhz SCC clock
|
||||
* D1,DO
|
||||
* 01 for 10 Mhz MPU clock
|
||||
* D1,DO = 10 for 12 Mhz MPU clock
|
||||
*
|
||||
* Original HBUG configuration word: 0x003D = 0000 0000 0011 1101
|
||||
*
|
||||
*/
|
||||
WRITE_LINE_MEMBER (hk68v10_state::write_sccterm_clock){
|
||||
m_sccterm->txca_w (state);
|
||||
m_sccterm->rxca_w (state);
|
||||
}
|
||||
|
||||
/*
|
||||
* Machine configuration
|
||||
*/
|
||||
static MACHINE_CONFIG_START (hk68v10, hk68v10_state)
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD ("maincpu", M68010, XTAL_10MHz)
|
||||
MCFG_CPU_PROGRAM_MAP (hk68v10_mem)
|
||||
|
||||
/* Terminal Port config */
|
||||
MCFG_SCC8530_ADD("scc", XTAL_4MHz, 0, 0, 0, 0 )
|
||||
MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
|
||||
MCFG_Z80SCC_OUT_DTRA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_dtr))
|
||||
MCFG_Z80SCC_OUT_RTSA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
|
||||
|
||||
MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("scc", scc8530_device, rxa_w))
|
||||
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("scc", scc8530_device, ctsa_w))
|
||||
|
||||
MCFG_DEVICE_ADD ("sccterm_clock", CLOCK, SCC_CLOCK)
|
||||
MCFG_CLOCK_SIGNAL_HANDLER (WRITELINE (hk68v10_state, write_sccterm_clock))
|
||||
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* ROM definitions */
|
||||
ROM_START (hk68v10)
|
||||
ROM_REGION (0x1000000, "maincpu", 0)
|
||||
|
||||
ROM_LOAD16_BYTE ("hk68kv10U23.bin", 0xFC0001, 0x2000, CRC (632aa026) SHA1 (f2b1ed0cc38dfbeb1602c013e00757015400720d))
|
||||
ROM_LOAD16_BYTE ("hk68kv10U12.bin", 0xFC0000, 0x2000, CRC (f2d688e9) SHA1 (e68699965645f0ce53de47625163c3eb02c8b727))
|
||||
/*
|
||||
* System ROM information
|
||||
*
|
||||
* The ROMs contains HBUG v1.8, known commands from different sources:
|
||||
*
|
||||
* 'uc' Print HK68 Configuration
|
||||
* 'um' Perform RAM test
|
||||
* 'dm adrs' Display Memory
|
||||
* 'sb adrs' Substitute Byte at adrs
|
||||
* 'c adrs' Call Routine at adrs
|
||||
* 'bw' Boot from Winchester
|
||||
* 'bf' Boot from floppy (MIO, SBX-FDIO)
|
||||
* 'bsf' Boot from floppy (SCSI)
|
||||
*
|
||||
*/
|
||||
ROM_END
|
||||
|
||||
/* Driver */
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
COMP (1985, hk68v10, 0, 0, hk68v10, hk68v10, driver_device, 0, "Heurikon Corporation", "HK68/V10", MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
|
||||
Loading…
Reference in New Issue
Block a user