mirror of
https://github.com/holub/mame
synced 2025-10-06 17:08:28 +03:00
Implemented most of the instruction set for Patinho Feio
This commit is contained in:
Felipe Corrêa da Silva Sanches
parent
0618c642ba
commit
51b8dfa01b
@ -5,32 +5,146 @@
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CPU_DISASSEMBLE( patinho_feio )
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{
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// int md;
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// int x;
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// md = oprom[1] << 8 | oprom[0];
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// x = md & 0xFFF;
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//single-opcode instructions
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switch (oprom[0])
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int addr, value, n, f;
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switch (oprom[0] & 0xF0)
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{
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case 0x80:
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sprintf (buffer, "LIMPO");
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break;
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case 0x85:
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sprintf (buffer, "INC");
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break;
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case 0x96:
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sprintf (buffer, "SV 1");
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break;
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case 0x99:
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sprintf (buffer, "TRE");
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break;
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case 0x9D:
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sprintf (buffer, "PARE");
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break;
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default:
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sprintf (buffer, "illegal");
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break;
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case 0x00:
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//PLA = "Pula": Unconditionally JUMP to effective address
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "PLA /%03X", addr);
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return 2;
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case 0x10:
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//PLAX = "Pulo indexado": Unconditionally JUMP to indexed address
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "PLAX (IDX) + /%03X", addr);
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return 2;
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case 0x20:
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//ARM = "Armazena": Stores the contents of the
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// accumulator in the given 12bit address
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "ARM /%03X", addr);
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return 2;
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case 0x30:
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//ARMX = "Armazenamento indexado": Stores the contents of the accumulator in the
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// given 12bit address (indexed by IDX)
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "ARMX (IDX) + /%03X", addr);
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return 2;
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case 0x40:
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//CAR = "Carrega": Loads the contents of the given 12bit address
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// into the accumulator
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "CAR /%03X", addr);
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return 2;
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case 0x50:
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//CARX = "Carga indexada": Loads the contents of the given 12bit address
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// (indexed by IDX) into the accumulator
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "CARX (IDX) + /%03X", addr);
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return 2;
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case 0x60:
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//SOM = "Soma": Adds the contents of the given 12bit address
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// into the accumulator
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "SOM /%03X", addr);
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return 2;
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case 0x70:
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//SOMX = "Soma indexada": Adds the contents of the given 12bit address
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// (indexed by IDX) into the accumulator
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "SOMX (IDX) + /%03X", addr);
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return 2;
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case 0x80:
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case 0x90:
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switch (oprom[0])
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{
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case 0x80: sprintf (buffer, "LIMPO"); return 1;
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case 0x81: sprintf (buffer, "UM"); return 1;
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case 0x82: sprintf (buffer, "CMP1"); return 1;
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case 0x83: sprintf (buffer, "CMP2"); return 1;
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case 0x84: sprintf (buffer, "LIN"); return 1;
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case 0x85: sprintf (buffer, "INC"); return 1;
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case 0x86: sprintf (buffer, "UNEG"); return 1;
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case 0x87: sprintf (buffer, "LIMP1"); return 1;
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case 0x90: sprintf (buffer, "ST 0"); return 1;
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case 0x91: sprintf (buffer, "STM 0"); return 1;
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case 0x92: sprintf (buffer, "ST 1"); return 1;
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case 0x93: sprintf (buffer, "STM 1"); return 1;
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case 0x94: sprintf (buffer, "SV 0"); return 1;
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case 0x95: sprintf (buffer, "SVM 0"); return 1;
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case 0x96: sprintf (buffer, "SV 1"); return 1;
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case 0x97: sprintf (buffer, "SVM 1"); return 1;
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case 0x98: sprintf (buffer, "PUL"); return 1;
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case 0x99: sprintf (buffer, "TRE"); return 1;
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case 0x9A: sprintf (buffer, "INIB"); return 1;
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case 0x9B: sprintf (buffer, "PERM"); return 1;
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case 0x9C: sprintf (buffer, "ESP"); return 1;
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case 0x9D: sprintf (buffer, "PARE"); return 1;
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case 0x9E: sprintf (buffer, "TRI"); return 1;
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case 0x9F: sprintf (buffer, "IND"); return 1;
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}
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break;
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case 0xA0:
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//PLAN = "Pula se ACC for negativo": Jumps to the 12bit address
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// if the accumulator is negative
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "PLAN /%03X", addr);
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return 2;
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case 0xB0:
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//PLAZ = "Pula se ACC for zero": Jumps to the 12bit address
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// if the accumulator is zero
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "PLAZ /%03X", addr);
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return 2;
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case 0xC0:
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n = (oprom[0] & 0x0F);
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f = (oprom[1] & 0x0F);
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n+= (n < 10) ? '0' : 'A'-10;
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f+= (f < 10) ? '0' : 'A'-10;
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switch(oprom[1] & 0xF0)
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{
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case 0x10: sprintf (buffer, "FNC /%c%c", n, f); return 2;
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case 0x20: sprintf (buffer, "SAL /%c%c", n, f); return 2;
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case 0x40: sprintf (buffer, "ENTR /%c0", n); return 2;
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case 0x80: sprintf (buffer, "SAI /%c0", n); return 2;
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}
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break;
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case 0xD0:
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value = oprom[1];
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switch (oprom[0] & 0x0F)
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{
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case 0x01:
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switch (oprom[1] & 0xF0)
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{
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case 0x00: sprintf (buffer, "DD /%02X", value); return 2; //DD = "Deslocamento para a direita": Shift right
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case 0x10: sprintf (buffer, "DDV /%02X", value); return 2; //DDV = "Deslocamento para a direita c/ V": Shift right with carry
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case 0x20: sprintf (buffer, "GD /%02X", value); return 2; //GD = "Giro para a direita": Rotate right
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case 0x30: sprintf (buffer, "GDV /%02X", value); return 2; //GDV = "Giro para a direita c/ V": Rotate right with carry
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case 0x40: sprintf (buffer, "DE /%02X", value); return 2; //DE = "Deslocamento para a esquerda": Shift right
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case 0x50: sprintf (buffer, "DEV /%02X", value); return 2; //DEV = "Deslocamento para a esquerda c/ V": Shift right with carry
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case 0x60: sprintf (buffer, "GE /%02X", value); return 2; //GE = "Giro para a esquerda": Rotate right
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case 0x70: sprintf (buffer, "GEV /%02X", value); return 2; //GEV = "Giro para a esquerda c/ V": Rotate right with carry
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case 0x80: sprintf (buffer, "DDS /%02X", value); return 2; //DDS = "Deslocamento para a direita com duplicacao de sinal": Shift right with sign duplication
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}
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break;
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case 0x02: sprintf (buffer, "XOR /%02X", value); return 2; //Logical XOR
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case 0x04: sprintf (buffer, "NAND /%02X", value); return 2; //Logical NAND
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case 0x08: sprintf (buffer, "SOMI /%02X", value); return 2; //SOMI = "Soma imediata": Add immediate value into accumulator
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case 0x0A: sprintf (buffer, "CARI /%02X", value); return 2; //CARI = "Carrega imediato": Loads an immediate value into the accumulator
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}
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break;
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case 0xE0:
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//SUS = "Subtrai um ou salta"
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "SUS /%03X", addr);
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return 2;
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case 0xF0:
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//PUG = "Pula e guarda"
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addr = (oprom[0] & 0x0F) << 8 | oprom[1];
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sprintf (buffer, "PUG /%03X", addr);
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return 2;
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}
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sprintf (buffer, "illegal instruction");
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return 1;
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}
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