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-cpu/arm7: Added interrupt helpers, hid details from most clients.

Browse Source 
* cpu/arm7: Moved input line and state item numbers into class
  declaration so most users don't need the internal header.
* cpu/arm7: Added callbacks so run to next interrupt works in the
  debugger.
* cpu/arm7: Added helpers for SoCs that generate effective FIQ/IRQ
  signals with and onboard interrupt controller.
* igs/igs027a.cpp: Moved presumed onboard RAM and possible FIQ enable
  into the device.

-igs/igs_m027.cpp: Cleaned up installation of varying numbers of PPIs,
 got rid of the chessc2 and gonefsh2 PPIs that don't really exist.
This commit is contained in:
Vas Crabb 2024-09-22 03:22:43 +10:00
parent 6aeb83416c
commit 520f5c5dab
81 changed files with 468 additions and 424 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/devices/bus/bbc/tube/tube_arm7.cpp
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@ -155,8 +155,8 @@ void bbc_tube_arm7_device::update_interrupts()
int firq = BIT(m_registers[INTERRUPT][4], 0) && m_efiq_state;
int irq = BIT(m_registers[EXP_INTERRUPT][6], 28, 4) && m_exint3_state;
m_maincpu->set_input_line(ARM7_FIRQ_LINE, firq ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(ARM7_IRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, firq ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, irq ? ASSERT_LINE : CLEAR_LINE);
}
void bbc_tube_arm7_device::efiq_w(int state)

1
src/devices/bus/bbc/tube/tube_arm7.h
View File

@ -14,7 +14,6 @@
#include "tube.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/ram.h"
#include "machine/tube.h"

4
src/devices/cpu/arm7/ap2010cpu.cpp
View File

@ -7,9 +7,11 @@
***************************************************************************/
#include "emu.h"
#include "ap2010cpu.h"
#include "arm7core.h"
DEFINE_DEVICE_TYPE(AP2010CPU, ap2010cpu_device, "ap2010cpu", "AP2010 CPU")
ap2010cpu_device::ap2010cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)

1
src/devices/cpu/arm7/ap2010cpu.h
View File

@ -12,7 +12,6 @@
#pragma once
#include "arm7.h"
#include "arm7core.h"
class ap2010cpu_device : public arm7_cpu_device
{

49
src/devices/cpu/arm7/arm7.cpp
View File

@ -31,12 +31,16 @@ TODO:
*****************************************************************************/
#include "emu.h"
#include "debug/debugcon.h"
#include "debugger.h"
#include "arm7.h"
#include "arm7core.h" //include arm7 core
#include "arm7help.h"
#include "debug/debugcon.h"
#include "debugger.h"
#include <cassert>
#define LOG_MMU (1U << 1)
#define LOG_DSP (1U << 2)
#define LOG_COPRO_READS (1U << 3)
@ -1166,10 +1170,6 @@ void arm1176jzf_s_cpu_device::device_reset()
m_control = 0x00050078;
}
#define UNEXECUTED() \
m_r[eR15] += 4; \
m_icount +=2; /* Any unexecuted instruction only takes 1 cycle (page 193) */
void arm7_cpu_device::update_insn_prefetch(uint32_t curr_pc)
{
curr_pc &= ~3;
@ -1249,6 +1249,8 @@ void arm7_cpu_device::add_ce_kernel_addr(offs_t addr, std::string value)
void arm7_cpu_device::execute_run()
{
auto const UNEXECUTED = [this] { m_r[eR15] += 4; m_icount += 2; }; // Any unexecuted instruction only takes 1 cycle (page 193)
m_tlb_log = m_actual_log;
uint32_t insn;
@ -1585,24 +1587,25 @@ skip_exec:
void arm7_cpu_device::execute_set_input(int irqline, int state)
{
switch (irqline) {
case ARM7_IRQ_LINE: /* IRQ */
m_pendingIrq = state ? true : false;
switch (irqline)
{
case ARM7_IRQ_LINE: // IRQ
m_pendingIrq = state != 0;
break;
case ARM7_FIRQ_LINE: /* FIRQ */
m_pendingFiq = state ? true : false;
case ARM7_FIRQ_LINE: // FIQ
m_pendingFiq = state != 0;
break;
case ARM7_ABORT_EXCEPTION:
m_pendingAbtD = state ? true : false;
m_pendingAbtD = state != 0;
break;
case ARM7_ABORT_PREFETCH_EXCEPTION:
m_pendingAbtP = state ? true : false;
m_pendingAbtP = state != 0;
break;
case ARM7_UNDEFINE_EXCEPTION:
m_pendingUnd = state ? true : false;
m_pendingUnd = state != 0;
break;
}
@ -1611,6 +1614,24 @@ void arm7_cpu_device::execute_set_input(int irqline, int state)
}
void arm7_cpu_device::set_irq(int state)
{
assert((machine().scheduler().currently_executing() == static_cast<device_execute_interface *>(this)) || !machine().scheduler().currently_executing());
m_pendingIrq = state != 0;
update_irq_state();
arm7_check_irq_state();
}
void arm7_cpu_device::set_fiq(int state)
{
assert((machine().scheduler().currently_executing() == static_cast<device_execute_interface *>(this)) || !machine().scheduler().currently_executing());
m_pendingFiq = state != 0;
update_irq_state();
arm7_check_irq_state();
}
std::unique_ptr<util::disasm_interface> arm7_cpu_device::create_disassembler()
{
return std::make_unique<arm7_disassembler>(this);

102
src/devices/cpu/arm7/arm7.h
View File

@ -50,6 +50,24 @@
class arm7_cpu_device : public cpu_device, public arm7_disassembler::config
{
public:
enum
{
ARM7_IRQ_LINE=0, ARM7_FIRQ_LINE,
ARM7_ABORT_EXCEPTION, ARM7_ABORT_PREFETCH_EXCEPTION, ARM7_UNDEFINE_EXCEPTION,
ARM7_NUM_LINES
};
// Really there's only 1 ABORT Line.. and cpu decides whether it's during data fetch or prefetch, but we let the user specify
enum
{
ARM7_PC = 0,
ARM7_R0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7,
ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15,
ARM7_FR8, ARM7_FR9, ARM7_FR10, ARM7_FR11, ARM7_FR12, ARM7_FR13, ARM7_FR14,
ARM7_IR13, ARM7_IR14, ARM7_SR13, ARM7_SR14, ARM7_FSPSR, ARM7_ISPSR, ARM7_SSPSR,
ARM7_CPSR, ARM7_AR13, ARM7_AR14, ARM7_ASPSR, ARM7_UR13, ARM7_UR14, ARM7_USPSR, ARM7_LOGTLB
};
// construction/destruction
arm7_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
virtual ~arm7_cpu_device();
@ -57,62 +75,8 @@ public:
void set_high_vectors() { m_vectorbase = 0xffff0000; }
protected:
enum
{
ARCHFLAG_T = 1, // Thumb present
ARCHFLAG_E = 2, // extended DSP operations present (only for v5+)
ARCHFLAG_J = 4, // "Jazelle" (direct execution of Java bytecode)
ARCHFLAG_MMU = 8, // has on-board MMU (traditional ARM style like the SA1110)
ARCHFLAG_SA = 16, // StrongARM extensions (enhanced TLB)
ARCHFLAG_XSCALE = 32, // XScale extensions (CP14, enhanced TLB)
ARCHFLAG_MODE26 = 64, // supports 26-bit backwards compatibility mode
ARCHFLAG_K = 128, // enhanced MMU extensions present (only for v6)
ARCHFLAG_T2 = 256, //Thumb-2 present
};
enum
{
ARM9_COPRO_ID_STEP_SA1110_A0 = 0,
ARM9_COPRO_ID_STEP_SA1110_B0 = 4,
ARM9_COPRO_ID_STEP_SA1110_B1 = 5,
ARM9_COPRO_ID_STEP_SA1110_B2 = 8,
ARM9_COPRO_ID_STEP_SA1110_B4 = 8,
ARM9_COPRO_ID_STEP_PXA255_A0 = 6,
ARM9_COPRO_ID_STEP_ARM946_A0 = 1,
ARM9_COPRO_ID_STEP_ARM1176JZF_S_R0P0 = 0,
ARM9_COPRO_ID_STEP_ARM1176JZF_S_R0P7 = 7,
ARM9_COPRO_ID_PART_ARM1176JZF_S = 0xB76 << 4,
ARM9_COPRO_ID_PART_SA1110 = 0xB11 << 4,
ARM9_COPRO_ID_PART_ARM946 = 0x946 << 4,
ARM9_COPRO_ID_PART_ARM920 = 0x920 << 4,
ARM9_COPRO_ID_PART_ARM710 = 0x710 << 4,
ARM9_COPRO_ID_PART_PXA250 = 0x200 << 4,
ARM9_COPRO_ID_PART_PXA255 = 0x2d0 << 4,
ARM9_COPRO_ID_PART_PXA270 = 0x411 << 4,
ARM9_COPRO_ID_PART_GENERICARM7 = 0x700 << 4,
ARM9_COPRO_ID_PXA255_CORE_REV_SHIFT = 10,
ARM9_COPRO_ID_ARCH_V4 = 0x01 << 16,
ARM9_COPRO_ID_ARCH_V4T = 0x02 << 16,
ARM9_COPRO_ID_ARCH_V5 = 0x03 << 16,
ARM9_COPRO_ID_ARCH_V5T = 0x04 << 16,
ARM9_COPRO_ID_ARCH_V5TE = 0x05 << 16,
ARM9_COPRO_ID_ARCH_V5TEJ = 0x06 << 16,
ARM9_COPRO_ID_ARCH_V6 = 0x07 << 16,
ARM9_COPRO_ID_ARCH_CPUID = 0x0F << 16,
ARM9_COPRO_ID_SPEC_REV0 = 0x00 << 20,
ARM9_COPRO_ID_SPEC_REV1 = 0x01 << 20,
ARM9_COPRO_ID_MFR_ARM = 0x41 << 24,
ARM9_COPRO_ID_MFR_DEC = 0x44 << 24,
ARM9_COPRO_ID_MFR_INTEL = 0x69 << 24
};
enum arm_arch_flag : uint32_t;
enum arm_copro_id : uint32_t;
arm7_cpu_device(
const machine_config &mconfig,
@ -127,34 +91,28 @@ protected:
void postload();
// device-level overrides
// device_t implementation
virtual void device_start() override;
virtual void device_reset() override;
// device_execute_interface overrides
// device_execute_interface implementation
virtual uint32_t execute_min_cycles() const noexcept override { return 3; }
virtual uint32_t execute_max_cycles() const noexcept override { return 4; }
virtual void execute_run() override;
virtual void execute_set_input(int inputnum, int state) override;
// device_memory_interface overrides
// device_memory_interface implementation
virtual space_config_vector memory_space_config() const override;
virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override;
// device_state_interface overrides
// device_state_interface implementation
virtual void state_export(const device_state_entry &entry) override;
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// device_disasm_interface overrides
// device_disasm_interface implementation
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual bool get_t_flag() const override;
address_space_config m_program_config;
memory_access<32, 2, 0, ENDIANNESS_LITTLE>::cache m_cachele;
memory_access<32, 2, 0, ENDIANNESS_BIG>::cache m_cachebe;
uint32_t m_r[/*NUM_REGS*/37];
void translate_insn_command(const std::vector<std::string_view> &params);
void translate_data_command(const std::vector<std::string_view> &params);
void translate_command(const std::vector<std::string_view> &params, int intention);
@ -167,6 +125,16 @@ protected:
void init_ce_kernel_addrs();
void print_ce_kernel_address(const offs_t addr);
// for SoCs with onboard interrupt controllers - only call from scheduler or CPU's own context
void set_irq(int state);
void set_fiq(int state);
address_space_config m_program_config;
memory_access<32, 2, 0, ENDIANNESS_LITTLE>::cache m_cachele;
memory_access<32, 2, 0, ENDIANNESS_BIG>::cache m_cachebe;
uint32_t m_r[/*NUM_REGS*/37];
std::string m_ce_kernel_addrs[0x10400];
bool m_ce_kernel_addr_present[0x10400];

90
src/devices/cpu/arm7/arm7core.h
View File

@ -18,10 +18,12 @@
******************************************************************************/
#ifndef MAME_CPU_ARM7_ARM7CORE_H
#define MAME_CPU_ARM7_ARM7CORE_H
#pragma once
#ifndef __ARM7CORE_H__
#define __ARM7CORE_H__
#include "arm7.h"
#define ARM7_MMU_ENABLE_HACK 0
#define ARM7_DEBUG_CORE 0
@ -30,26 +32,10 @@
/****************************************************************************************************
* INTERRUPT LINES/EXCEPTIONS
***************************************************************************************************/
enum
{
ARM7_IRQ_LINE=0, ARM7_FIRQ_LINE,
ARM7_ABORT_EXCEPTION, ARM7_ABORT_PREFETCH_EXCEPTION, ARM7_UNDEFINE_EXCEPTION,
ARM7_NUM_LINES
};
// Really there's only 1 ABORT Line.. and cpu decides whether it's during data fetch or prefetch, but we let the user specify
/****************************************************************************************************
* ARM7 CORE REGISTERS
***************************************************************************************************/
enum
{
ARM7_PC = 0,
ARM7_R0, ARM7_R1, ARM7_R2, ARM7_R3, ARM7_R4, ARM7_R5, ARM7_R6, ARM7_R7,
ARM7_R8, ARM7_R9, ARM7_R10, ARM7_R11, ARM7_R12, ARM7_R13, ARM7_R14, ARM7_R15,
ARM7_FR8, ARM7_FR9, ARM7_FR10, ARM7_FR11, ARM7_FR12, ARM7_FR13, ARM7_FR14,
ARM7_IR13, ARM7_IR14, ARM7_SR13, ARM7_SR14, ARM7_FSPSR, ARM7_ISPSR, ARM7_SSPSR,
ARM7_CPSR, ARM7_AR13, ARM7_AR14, ARM7_ASPSR, ARM7_UR13, ARM7_UR14, ARM7_USPSR, ARM7_LOGTLB
};
/* There are 36 Unique - 32 bit processor registers */
/* Each mode has 17 registers (except user & system, which have 16) */
@ -516,19 +502,61 @@ enum
#define ARM7_TLB_WRITE (1 << 3)
/* ARM flavors */
enum arm_flavor
enum arm7_cpu_device::arm_arch_flag : uint32_t
{
/* ARM7 variants */
ARM_TYPE_ARM7,
ARM_TYPE_ARM7BE,
ARM_TYPE_ARM7500,
ARM_TYPE_PXA255,
ARM_TYPE_SA1110,
/* ARM9 variants */
ARM_TYPE_ARM9,
ARM_TYPE_ARM920T,
ARM_TYPE_ARM946ES
ARCHFLAG_T = 1U << 0, // Thumb present
ARCHFLAG_E = 1U << 1, // extended DSP operations present (only for v5+)
ARCHFLAG_J = 1U << 2, // "Jazelle" (direct execution of Java bytecode)
ARCHFLAG_MMU = 1U << 3, // has on-board MMU (traditional ARM style like the SA1110)
ARCHFLAG_SA = 1U << 4, // StrongARM extensions (enhanced TLB)
ARCHFLAG_XSCALE = 1U << 5, // XScale extensions (CP14, enhanced TLB)
ARCHFLAG_MODE26 = 1U << 6, // supports 26-bit backwards compatibility mode
ARCHFLAG_K = 1U << 7, // enhanced MMU extensions present (only for v6)
ARCHFLAG_T2 = 1U << 8, // Thumb-2 present
};
#endif /* __ARM7CORE_H__ */
enum arm7_cpu_device::arm_copro_id : uint32_t
{
ARM9_COPRO_ID_STEP_SA1110_A0 = 0,
ARM9_COPRO_ID_STEP_SA1110_B0 = 4,
ARM9_COPRO_ID_STEP_SA1110_B1 = 5,
ARM9_COPRO_ID_STEP_SA1110_B2 = 8,
ARM9_COPRO_ID_STEP_SA1110_B4 = 8,
ARM9_COPRO_ID_STEP_PXA255_A0 = 6,
ARM9_COPRO_ID_STEP_ARM946_A0 = 1,
ARM9_COPRO_ID_STEP_ARM1176JZF_S_R0P0 = 0,
ARM9_COPRO_ID_STEP_ARM1176JZF_S_R0P7 = 7,
ARM9_COPRO_ID_PART_ARM1176JZF_S = 0xB76 << 4,
ARM9_COPRO_ID_PART_SA1110 = 0xB11 << 4,
ARM9_COPRO_ID_PART_ARM946 = 0x946 << 4,
ARM9_COPRO_ID_PART_ARM920 = 0x920 << 4,
ARM9_COPRO_ID_PART_ARM710 = 0x710 << 4,
ARM9_COPRO_ID_PART_PXA250 = 0x200 << 4,
ARM9_COPRO_ID_PART_PXA255 = 0x2d0 << 4,
ARM9_COPRO_ID_PART_PXA270 = 0x411 << 4,
ARM9_COPRO_ID_PART_GENERICARM7 = 0x700 << 4,
ARM9_COPRO_ID_PXA255_CORE_REV_SHIFT = 10,
ARM9_COPRO_ID_ARCH_V4 = 0x01 << 16,
ARM9_COPRO_ID_ARCH_V4T = 0x02 << 16,
ARM9_COPRO_ID_ARCH_V5 = 0x03 << 16,
ARM9_COPRO_ID_ARCH_V5T = 0x04 << 16,
ARM9_COPRO_ID_ARCH_V5TE = 0x05 << 16,
ARM9_COPRO_ID_ARCH_V5TEJ = 0x06 << 16,
ARM9_COPRO_ID_ARCH_V6 = 0x07 << 16,
ARM9_COPRO_ID_ARCH_CPUID = 0x0F << 16,
ARM9_COPRO_ID_SPEC_REV0 = 0x00 << 20,
ARM9_COPRO_ID_SPEC_REV1 = 0x01 << 20,
ARM9_COPRO_ID_MFR_ARM = 0x41 << 24,
ARM9_COPRO_ID_MFR_DEC = 0x44 << 24,
ARM9_COPRO_ID_MFR_INTEL = 0x69 << 24
};
#endif // MAME_CPU_ARM7_ARM7CORE_H

10
src/devices/cpu/arm7/arm7core.hxx
View File

@ -113,7 +113,7 @@ void arm7_cpu_device::arm7_check_irq_state()
// Data Abort
if (m_pendingAbtD)
{
if (MODE26) fatalerror( "ARM7: pendingAbtD (todo)\n");
if (MODE26) fatalerror("ARM7: pendingAbtD (todo)\n");
SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
SetRegister(14, pc - 8 + 8); /* save PC to R14 */
SetRegister(SPSR, cpsr); /* Save current CPSR */
@ -129,7 +129,8 @@ void arm7_cpu_device::arm7_check_irq_state()
// FIQ
if (m_pendingFiq && (cpsr & F_MASK) == 0)
{
if (MODE26) fatalerror( "pendingFiq (todo)\n");
standard_irq_callback(ARM7_FIRQ_LINE, pc);
if (MODE26) fatalerror("pendingFiq (todo)\n");
SwitchMode(eARM7_MODE_FIQ); /* Set FIQ mode so PC is saved to correct R14 bank */
SetRegister(14, pc - 4 + 4); /* save PC to R14 */
SetRegister(SPSR, cpsr); /* Save current CPSR */
@ -144,6 +145,7 @@ void arm7_cpu_device::arm7_check_irq_state()
// IRQ
if (m_pendingIrq && (cpsr & I_MASK) == 0)
{
standard_irq_callback(ARM7_IRQ_LINE, pc);
SwitchMode(eARM7_MODE_IRQ); /* Set IRQ mode so PC is saved to correct R14 bank */
SetRegister(14, pc - 4 + 4); /* save PC to R14 */
if (MODE32)
@ -168,7 +170,7 @@ void arm7_cpu_device::arm7_check_irq_state()
// Prefetch Abort
if (m_pendingAbtP)
{
if (MODE26) fatalerror( "pendingAbtP (todo)\n");
if (MODE26) fatalerror("pendingAbtP (todo)\n");
SwitchMode(eARM7_MODE_ABT); /* Set ABT mode so PC is saved to correct R14 bank */
SetRegister(14, pc - 4 + 4); /* save PC to R14 */
SetRegister(SPSR, cpsr); /* Save current CPSR */
@ -184,7 +186,7 @@ void arm7_cpu_device::arm7_check_irq_state()
// Undefined instruction
if (m_pendingUnd)
{
if (MODE26) printf( "ARM7: pendingUnd (todo)\n");
if (MODE26) printf("ARM7: pendingUnd (todo)\n");
SwitchMode(eARM7_MODE_UND); /* Set UND mode so PC is saved to correct R14 bank */
// compensate for prefetch (should this also be done for normal IRQ?)
if (T_IS_SET(GET_CPSR))

3
src/devices/cpu/arm7/lpc210x.cpp
View File

@ -15,6 +15,9 @@
#include "emu.h"
#include "lpc210x.h"
#include "arm7core.h"
DEFINE_DEVICE_TYPE(LPC2103, lpc210x_device, "lpc2103", "NXP LPC2103")
void lpc210x_device::lpc2103_map(address_map &map)

3
src/devices/cpu/arm7/lpc210x.h
View File

@ -7,9 +7,10 @@
#pragma once
#include "arm7.h"
#include "arm7core.h"
#include "machine/vic_pl192.h"
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/

3
src/devices/cpu/arm7/upd800468.cpp
View File

@ -12,6 +12,9 @@
#include "emu.h"
#include "upd800468.h"
#include "arm7core.h"
DEFINE_DEVICE_TYPE(UPD800468_TIMER, upd800468_timer_device, "upd800468_timer", "NEC uPD800468 timer")
upd800468_timer_device::upd800468_timer_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)

3
src/devices/cpu/arm7/upd800468.h
View File

@ -7,10 +7,11 @@
#pragma once
#include "arm7.h"
#include "arm7core.h"
#include "machine/gt913_kbd.h"
#include "machine/vic_pl192.h"
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/

2
src/devices/machine/arm_iomd.cpp
View File

@ -427,7 +427,7 @@ inline u8 arm_iomd_device::update_irqa_type(u8 data)
inline void arm_iomd_device::flush_irq(unsigned Which)
{
if (m_irq_status[Which] & m_irq_mask[Which])
m_host_cpu->pulse_input_line(ARM7_IRQ_LINE, m_host_cpu->minimum_quantum_time());
m_host_cpu->pulse_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_host_cpu->minimum_quantum_time());
}
template <unsigned Which> inline void arm_iomd_device::trigger_irq(u8 irq_type)

1
src/devices/machine/arm_iomd.h
View File

@ -12,7 +12,6 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/acorn_vidc.h"
#include "machine/at_keybc.h"
#include "bus/pc_kbd/pc_kbdc.h"

4
src/devices/machine/pxa255.cpp
View File

@ -877,8 +877,8 @@ void pxa255_periphs_device::update_interrupts()
{
m_intc_regs.icfp = (m_intc_regs.icpr & m_intc_regs.icmr) & m_intc_regs.iclr;
m_intc_regs.icip = (m_intc_regs.icpr & m_intc_regs.icmr) & (~m_intc_regs.iclr);
m_maincpu->set_input_line(ARM7_FIRQ_LINE, m_intc_regs.icfp ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(ARM7_IRQ_LINE, m_intc_regs.icip ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_intc_regs.icfp ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_intc_regs.icip ? ASSERT_LINE : CLEAR_LINE);
}
void pxa255_periphs_device::set_irq_line(u32 line, int irq_state)

1
src/devices/machine/pxa255.h
View File

@ -15,7 +15,6 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/dmadac.h"
#include "emupal.h"

2
src/devices/machine/s3c2400.cpp
View File

@ -11,8 +11,6 @@
#include "emu.h"
#include "s3c2400.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "screen.h"

2
src/devices/machine/s3c2410.cpp
View File

@ -11,8 +11,6 @@
#include "emu.h"
#include "s3c2410.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "screen.h"

2
src/devices/machine/s3c2440.cpp
View File

@ -11,8 +11,6 @@
#include "emu.h"
#include "s3c2440.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "screen.h"

9
src/devices/machine/s3c24xx.hxx
View File

@ -8,7 +8,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "coreutil.h"
/*******************************************************************************
@ -1126,7 +1125,7 @@ void S3C24_CLASS_NAME::s3c24xx_check_pending_irq()
{
LOGMASKED(LOG_IRQS, "triggering IRQ line\n");
m_cpu->resume(SUSPEND_REASON_HALT);
m_cpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_irq.line_irq = ASSERT_LINE;
}
}
@ -1136,7 +1135,7 @@ void S3C24_CLASS_NAME::s3c24xx_check_pending_irq()
{
LOGMASKED(LOG_IRQS, "IRQ: srcpnd %08X intmsk %08X intmod %08X\n", m_irq.regs.srcpnd, m_irq.regs.intmsk, m_irq.regs.intmod);
LOGMASKED(LOG_IRQS, "clearing IRQ line\n");
m_cpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
m_irq.line_irq = CLEAR_LINE;
}
}
@ -1150,7 +1149,7 @@ void S3C24_CLASS_NAME::s3c24xx_check_pending_irq()
{
LOGMASKED(LOG_IRQS, "asserting FIQ line\n");
m_cpu->resume(SUSPEND_REASON_HALT);
m_cpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, ASSERT_LINE);
m_irq.line_fiq = ASSERT_LINE;
}
}
@ -1159,7 +1158,7 @@ void S3C24_CLASS_NAME::s3c24xx_check_pending_irq()
if (m_irq.line_fiq != CLEAR_LINE)
{
LOGMASKED(LOG_IRQS, "clearing FIQ line\n");
m_cpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, CLEAR_LINE);
m_irq.line_fiq = CLEAR_LINE;
}
}

9
src/devices/machine/s3c44b0.cpp
View File

@ -12,7 +12,6 @@
#include "s3c44b0.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "screen.h"
#include <algorithm>
@ -891,7 +890,7 @@ void s3c44b0_device::check_pending_irq()
m_irq.regs.i_ispr |= (1 << int_type);
if (m_irq.line_irq != ASSERT_LINE)
{
m_cpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_irq.line_irq = ASSERT_LINE;
}
}
@ -899,7 +898,7 @@ void s3c44b0_device::check_pending_irq()
{
if (m_irq.line_irq != CLEAR_LINE)
{
m_cpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
m_irq.line_irq = CLEAR_LINE;
}
}
@ -909,7 +908,7 @@ void s3c44b0_device::check_pending_irq()
{
if (m_irq.line_fiq != ASSERT_LINE)
{
m_cpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, ASSERT_LINE);
m_irq.line_fiq = ASSERT_LINE;
}
}
@ -917,7 +916,7 @@ void s3c44b0_device::check_pending_irq()
{
if (m_irq.line_fiq != CLEAR_LINE)
{
m_cpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
m_cpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, CLEAR_LINE);
m_irq.line_fiq = CLEAR_LINE;
}
}

4
src/devices/machine/sa1110.cpp
View File

@ -2287,14 +2287,14 @@ void sa1110_periphs_device::update_interrupts()
m_intc_regs.icfp = (m_intc_regs.icpr & m_intc_regs.icmr) & m_intc_regs.iclr;
if (old_fiq != m_intc_regs.icfp)
{
m_maincpu->set_input_line(ARM7_FIRQ_LINE, m_intc_regs.icfp ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_intc_regs.icfp ? ASSERT_LINE : CLEAR_LINE);
}
const u32 old_irq = m_intc_regs.icip;
m_intc_regs.icip = (m_intc_regs.icpr & m_intc_regs.icmr) & (~m_intc_regs.iclr);
if (old_irq != m_intc_regs.icip)
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, m_intc_regs.icip ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_intc_regs.icip ? ASSERT_LINE : CLEAR_LINE);
}
}

1
src/devices/machine/sa1110.h
View File

@ -12,7 +12,6 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/input_merger.h"
#include "machine/ucb1200.h"

1
src/devices/machine/sa1111.h
View File

@ -12,7 +12,6 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
class sa1111_device : public device_t
{

1
src/mame/acorn/riscpc.cpp
View File

@ -16,7 +16,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/acorn_vidc.h"
#include "machine/arm_iomd.h"
#include "machine/i2cmem.h"

1
src/mame/acorn/ssfindo.cpp
View File

@ -128,7 +128,6 @@ Notes:
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/acorn_vidc.h"
#include "machine/arm_iomd.h"
#include "machine/i2cmem.h"

5
src/mame/apple/iphone2g.cpp
View File

@ -10,7 +10,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/vic_pl192.h"
#include "screen.h"
@ -283,8 +282,8 @@ void iphone2g_state::iphone2g(machine_config &config)
m_maincpu->set_addrmap(AS_PROGRAM, &iphone2g_state::mem_map);
PL192_VIC(config, m_vic0);
m_vic0->out_irq_cb().set_inputline("maincpu", ARM7_IRQ_LINE);
m_vic0->out_fiq_cb().set_inputline("maincpu", ARM7_FIRQ_LINE);
m_vic0->out_irq_cb().set_inputline("maincpu", arm7_cpu_device::ARM7_IRQ_LINE);
m_vic0->out_fiq_cb().set_inputline("maincpu", arm7_cpu_device::ARM7_FIRQ_LINE);
IPHONE2G_SPI(config, m_spi[0], XTAL(12'000'000));
m_spi[0]->out_irq_cb().set(m_vic0, FUNC(vic_pl192_device::irq_w<0x09>));

1
src/mame/apple/newton.cpp
View File

@ -22,7 +22,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/ram.h"
#include "emupal.h"
#include "screen.h"

1
src/mame/eolith/ghosteo.cpp
View File

@ -59,7 +59,6 @@ ToDo: verify QS1000 hook-up
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/gen_latch.h"
#include "machine/i2cmem.h"
//#include "machine/nandflash.h"

7
src/mame/gamepark/gp32.cpp
View File

@ -35,7 +35,6 @@
#include "gp32.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "softlist_dev.h"
#include "speaker.h"
@ -471,11 +470,11 @@ void gp32_state::s3c240x_check_pending_irq()
}
m_s3c240x_irq_regs[4] |= (1 << int_type); // INTPND
m_s3c240x_irq_regs[5] = int_type; // INTOFFSET
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
else
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
}
@ -487,7 +486,7 @@ void gp32_state::s3c240x_request_irq(uint32_t int_type)
m_s3c240x_irq_regs[0] |= (1 << int_type); // SRCPND
m_s3c240x_irq_regs[4] |= (1 << int_type); // INTPND
m_s3c240x_irq_regs[5] = int_type; // INTOFFSET
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
else
{

5
src/mame/gamepark/gp32.h
View File

@ -4,9 +4,12 @@
#ifndef MAME_GAMEPARK_GP32_H
#define MAME_GAMEPARK_GP32_H
#pragma once
#include "machine/nvram.h"
#include "machine/smartmed.h"
#include "sound/dac.h"
#include "machine/nvram.h"
#include "emupal.h"
#include "screen.h"

1
src/mame/hp/jornada.cpp
View File

@ -8,7 +8,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/m950x0.h"
#include "machine/sa1110.h"
#include "machine/sa1111.h"

76
src/mame/igs/igs027a.cpp
View File

@ -42,16 +42,12 @@ igs027a_cpu_device::~igs027a_cpu_device()
}
void igs027a_cpu_device::trigger_irq(unsigned num)
void igs027a_cpu_device::device_resolve_objects()
{
if (!BIT(m_irq_enable, num))
{
m_irq_pending &= ~(u8(1) << num);
pulse_input_line(ARM7_IRQ_LINE, minimum_quantum_time());
}
m_ext_fiq = 0;
m_ext_irq = 0;
}
void igs027a_cpu_device::device_start()
{
arm7_cpu_device::device_start();
@ -59,6 +55,9 @@ void igs027a_cpu_device::device_start()
m_irq_timers[0] = timer_alloc(FUNC(igs027a_cpu_device::timer_irq<0>), this);
m_irq_timers[1] = timer_alloc(FUNC(igs027a_cpu_device::timer_irq<1>), this);
save_item(NAME(m_ext_fiq));
save_item(NAME(m_ext_irq));
save_item(NAME(m_fiq_enable));
save_item(NAME(m_irq_enable));
save_item(NAME(m_irq_pending));
}
@ -67,8 +66,41 @@ void igs027a_cpu_device::device_reset()
{
arm7_cpu_device::device_reset();
if (!BIT(m_fiq_enable, 0))
machine().scheduler().synchronize(timer_expired_delegate(FUNC(igs027a_cpu_device::check_fiq), this));
m_fiq_enable = 0x01; // superkds and fearless never write to 0x4000'0014 but expect FIQ to be triggered
m_irq_enable = 0xff;
m_irq_pending = 0xff;
set_irq(0);
}
void igs027a_cpu_device::execute_set_input(int irqline, int state)
{
switch (irqline)
{
case ARM7_IRQ_LINE:
if (state && !m_ext_irq && !BIT(m_irq_enable, 3))
{
m_irq_pending &= ~(u8(1) << 3);
set_irq(1);
}
m_ext_irq = state ? 1 : 0;
break;
case ARM7_FIRQ_LINE:
if (state && !m_ext_fiq && BIT(m_fiq_enable, 0))
{
set_fiq(1);
set_fiq(0); // hacky - depends on ARM7 core checking interrupts outside execute loop; how is this actually acknowledged?
}
m_ext_fiq = state ? 1 : 0;
break;
default:
arm7_cpu_device::execute_set_input(irqline, state);
}
}
@ -76,7 +108,10 @@ void igs027a_cpu_device::onboard_peripherals(address_map &map)
{
map(0x0000'0000, 0x0000'3fff).rom().region(DEVICE_SELF, 0);
map(0x1000'0000, 0x1000'03ff).ram(); // onboard RAM?
map(0x4000'000c, 0x4000'000f).r(FUNC(igs027a_cpu_device::in_port_r));
map(0x4000'0014, 0x4000'0017).umask32(0x0000'00ff).w(FUNC(igs027a_cpu_device::fiq_enable_w)); // sets bit 0 before waiting on FIRQ, maybe it's an enable here?
map(0x4000'0018, 0x4000'001b).umask32(0x0000'00ff).w(FUNC(igs027a_cpu_device::out_port_w));
map(0x7000'0100, 0x7000'0107).umask32(0x0000'00ff).w(FUNC(igs027a_cpu_device::timer_rate_w));
@ -119,10 +154,22 @@ u8 igs027a_cpu_device::irq_pending_r()
{
u8 const result = m_irq_pending;
if (!machine().side_effects_disabled())
{
m_irq_pending = 0xff;
set_irq(0);
}
return result;
}
void igs027a_cpu_device::fiq_enable_w(u8 data)
{
if (BIT(~m_fiq_enable & data, 0))
machine().scheduler().synchronize(timer_expired_delegate(FUNC(igs027a_cpu_device::check_fiq), this));
else if (BIT(m_fiq_enable & ~data, 0))
set_fiq(0);
m_fiq_enable = data;
}
void igs027a_cpu_device::irq_enable_w(u8 data)
{
m_irq_enable = data;
@ -138,5 +185,18 @@ void igs027a_cpu_device::bus_sizing_w(u8 data)
template <unsigned N>
TIMER_CALLBACK_MEMBER(igs027a_cpu_device::timer_irq)
{
trigger_irq(N);
if (!BIT(m_irq_enable, N))
{
m_irq_pending &= ~(u8(1) << N);
set_irq(1);
}
}
TIMER_CALLBACK_MEMBER(igs027a_cpu_device::check_fiq)
{
if (m_ext_fiq && BIT(m_fiq_enable, 0))
{
set_fiq(1);
set_fiq(0); // hacky - depends on ARM7 core checking interrupts outside execute loop; how is this actually acknowledged?
}
}

10
src/mame/igs/igs027a.h
View File

@ -19,12 +19,13 @@ public:
auto in_port() { return m_in_port_cb.bind(); }
auto out_port() { return m_out_port_cb.bind(); }
void trigger_irq(unsigned num);
protected:
virtual void device_resolve_objects() override ATTR_COLD;
virtual void device_start() override ATTR_COLD;
virtual void device_reset() override ATTR_COLD;
virtual void execute_set_input(int irqline, int state) override;
private:
void onboard_peripherals(address_map &map) ATTR_COLD;
@ -32,17 +33,22 @@ private:
void out_port_w(u8 data);
void timer_rate_w(offs_t offset, u8 data);
u8 irq_pending_r();
void fiq_enable_w(u8 data);
void irq_enable_w(u8 data);
void bus_sizing_w(u8 data);
template <unsigned N> TIMER_CALLBACK_MEMBER(timer_irq);
TIMER_CALLBACK_MEMBER(check_fiq);
devcb_read32 m_in_port_cb;
devcb_write8 m_out_port_cb;
emu_timer *m_irq_timers[2];
u8 m_ext_fiq;
u8 m_ext_irq;
u8 m_fiq_enable;
u8 m_irq_enable;
u8 m_irq_pending;
};

15
src/mame/igs/igs_fear.cpp
View File

@ -11,7 +11,6 @@
#include "pgmcrypt.h"
#include "xamcu.h"
#include "cpu/arm7/arm7core.h"
#include "machine/nvram.h"
#include "machine/ticket.h"
#include "machine/v3021.h"
@ -63,7 +62,6 @@ private:
void main_map(address_map &map) ATTR_COLD;
void main_xor_map(address_map &map) ATTR_COLD;
void sound_irq(int state);
void vblank_irq(int state);
void draw_sprite(bitmap_ind16 &bitmap, const rectangle &cliprect, int xpos, int ypos, int height, int width, int palette, int flipx, int romoffset);
@ -341,18 +339,9 @@ INPUT_PORTS_START( superkds )
PORT_BIT( 0xff, 0x00, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(20) PORT_KEYDELTA(20)
INPUT_PORTS_END
void igs_fear_state::sound_irq(int state)
{
LOGMASKED(LOG_DEBUG, "sound irq = %d\n", state);
if (state)
m_maincpu->trigger_irq(3);
}
void igs_fear_state::vblank_irq(int state)
{
if (state)
if (m_screen->frame_number() & 1)
m_maincpu->pulse_input_line(ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time());
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, (state && m_screen->frame_number() & 1) ? 1 : 0);
}
@ -479,7 +468,7 @@ void igs_fear_state::igs_fear(machine_config &config)
/* sound hardware */
IGS_XA_ICS_SOUND(config, m_xa, 50'000'000/3);
m_xa->irq().set(FUNC(igs_fear_state::sound_irq));
m_xa->irq().set_inputline(m_maincpu, arm7_cpu_device::ARM7_IRQ_LINE);
}
void igs_fear_state::igs_fear_xor(machine_config &config)

245
src/mame/igs/igs_m027.cpp
View File

@ -29,8 +29,6 @@
#include "mahjong.h"
#include "pgmcrypt.h"
#include "cpu/arm7/arm7core.h"
#include "machine/i8255.h"
#include "machine/nvram.h"
#include "machine/ticket.h"
@ -58,7 +56,6 @@ public:
igs_m027_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_external_rom(*this, "user1"),
m_igs_mainram(*this, "igs_mainram"),
m_maincpu(*this, "maincpu"),
m_ppi(*this, "ppi%u", 1U),
m_igs017_igs031(*this, "igs017_igs031"),
@ -77,21 +74,22 @@ public:
template <unsigned N> void counter_w(int state);
void m027(machine_config &config) ATTR_COLD;
void m027_xor(machine_config &config) ATTR_COLD;
void slqz3_xor(machine_config &config) ATTR_COLD;
void jking02_xor(machine_config &config) ATTR_COLD;
void qlgs_xor(machine_config &config) ATTR_COLD;
void lhdmg_xor(machine_config &config) ATTR_COLD;
void cjddz_xor(machine_config &config) ATTR_COLD;
void lhzb4_xor(machine_config &config) ATTR_COLD;
void lthy_xor(machine_config &config) ATTR_COLD;
void zhongguo_xor(machine_config &config) ATTR_COLD;
void mgzz_xor(machine_config &config) ATTR_COLD;
void oceanpar_xor(machine_config &config) ATTR_COLD;
void tripslot_xor(machine_config &config) ATTR_COLD;
template <bool Xor> void m027_noppi(machine_config &config) ATTR_COLD;
template <bool Xor> void m027_1ppi(machine_config &config) ATTR_COLD;
template <bool Xor> void m027_2ppis(machine_config &config) ATTR_COLD;
void slqz3(machine_config &config) ATTR_COLD;
void jking02(machine_config &config) ATTR_COLD;
void qlgs(machine_config &config) ATTR_COLD;
void lhdmg(machine_config &config) ATTR_COLD;
void cjddz(machine_config &config) ATTR_COLD;
void lhzb4(machine_config &config) ATTR_COLD;
void lthy(machine_config &config) ATTR_COLD;
void zhongguo(machine_config &config) ATTR_COLD;
void mgzz(machine_config &config) ATTR_COLD;
void oceanpar(machine_config &config) ATTR_COLD;
void tripslot(machine_config &config) ATTR_COLD;
void extradrw(machine_config &config) ATTR_COLD;
void chessc2_xor(machine_config &config) ATTR_COLD;
void chessc2(machine_config &config) ATTR_COLD;
void init_sdwx() ATTR_COLD;
void init_lhzb4() ATTR_COLD;
@ -122,7 +120,6 @@ protected:
private:
required_region_ptr<u32> m_external_rom;
optional_shared_ptr<u32> m_igs_mainram;
required_device<igs027a_cpu_device> m_maincpu;
optional_device_array<i8255_device, 2> m_ppi;
@ -167,11 +164,11 @@ private:
void pgm_create_dummy_internal_arm_region() ATTR_COLD;
void igs_mahjong_map(address_map &map) ATTR_COLD;
void igs_mahjong_xor_map(address_map &map) ATTR_COLD;
void cjddz_xor_map(address_map &map) ATTR_COLD;
void tripslot_xor_map(address_map &map) ATTR_COLD;
void extradrw_map(address_map &map) ATTR_COLD;
template <bool Xor> void m027_noppi_map(address_map &map) ATTR_COLD;
template <bool Xor> void m027_1ppi_map(address_map &map) ATTR_COLD;
template <bool Xor> void m027_2ppis_map(address_map &map) ATTR_COLD;
void cjddz_map(address_map &map) ATTR_COLD;
void tripslot_map(address_map &map) ATTR_COLD;
void oki_128k_map(address_map &map) ATTR_COLD;
};
@ -206,48 +203,52 @@ void igs_m027_state::video_start()
***************************************************************************/
void igs_m027_state::igs_mahjong_map(address_map &map)
template <bool Xor>
void igs_m027_state::m027_noppi_map(address_map &map)
{
map(0x0800'0000, 0x0807'ffff).rom().region("user1", 0); // Game ROM
map(0x1000'0000, 0x1000'03ff).ram().share("igs_mainram"); // main RAM for ASIC?
if (Xor)
map(0x0800'0000, 0x0807'ffff).r(FUNC(igs_m027_state::external_rom_r)); // Game ROM
else
map(0x0800'0000, 0x0807'ffff).rom().region("user1", 0); // Game ROM
map(0x1800'0000, 0x1800'7fff).ram().mirror(0x0000f'8000).share("nvram");
map(0x3800'0000, 0x3800'7fff).rw(m_igs017_igs031, FUNC(igs017_igs031_device::read), FUNC(igs017_igs031_device::write));
map(0x3800'8000, 0x3800'8003).umask32(0x0000'00ff).rw(m_oki, FUNC(okim6295_device::read), FUNC(okim6295_device::write));
map(0x3800'9000, 0x3800'9003).rw(m_ppi[0], FUNC(i8255_device::read), FUNC(i8255_device::write));
map(0x5000'0000, 0x5000'03ff).umask32(0x0000'00ff).w(FUNC(igs_m027_state::xor_table_w)); // uploads XOR table to external ROM here
}
void igs_m027_state::igs_mahjong_xor_map(address_map &map)
template <bool Xor>
void igs_m027_state::m027_1ppi_map(address_map &map)
{
igs_mahjong_map(map);
m027_noppi_map<Xor>(map);
map(0x0800'0000, 0x0807'ffff).r(FUNC(igs_m027_state::external_rom_r)); // Game ROM
map(0x3800'9000, 0x3800'9003).rw(m_ppi[0], FUNC(i8255_device::read), FUNC(i8255_device::write));
}
void igs_m027_state::cjddz_xor_map(address_map &map)
template <bool Xor>
void igs_m027_state::m027_2ppis_map(address_map &map)
{
igs_mahjong_xor_map(map);
m027_1ppi_map<Xor>(map);
map(0x3800'a000, 0x3800'a003).rw(m_ppi[1], FUNC(i8255_device::read), FUNC(i8255_device::write));
}
void igs_m027_state::cjddz_map(address_map &map)
{
m027_1ppi_map<true>(map);
map(0x3800'b000, 0x3800'b003).umask32(0x0000'00ff).w(FUNC(igs_m027_state::oki_128k_bank_w));
}
void igs_m027_state::tripslot_xor_map(address_map &map)
void igs_m027_state::tripslot_map(address_map &map)
{
igs_mahjong_xor_map(map);
m027_1ppi_map<true>(map);
map(0x3800'c000, 0x3800'c003).umask32(0x0000'00ff).w(FUNC(igs_m027_state::tripslot_misc_w));
}
void igs_m027_state::extradrw_map(address_map &map)
{
igs_mahjong_map(map);
map(0x3800'a000, 0x3800'a003).rw(m_ppi[1], FUNC(i8255_device::read), FUNC(i8255_device::write));
}
void igs_m027_state::oki_128k_map(address_map &map)
{
map(0x00000, 0x1ffff).bankr(m_okibank[0]);
@ -1459,10 +1460,10 @@ TIMER_DEVICE_CALLBACK_MEMBER(igs_m027_state::interrupt)
int scanline = param;
if (scanline == 240 && m_igs017_igs031->get_irq_enable())
m_maincpu->trigger_irq(3); // source?
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_maincpu->minimum_quantum_time()); // source?
if (scanline == 0 && m_igs017_igs031->get_nmi_enable())
m_maincpu->pulse_input_line(ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time()); // vbl?
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time()); // vbl?
}
@ -1627,10 +1628,11 @@ void igs_m027_state::counter_w(int state)
}
void igs_m027_state::m027(machine_config &config)
template <bool Xor>
void igs_m027_state::m027_noppi(machine_config &config)
{
IGS027A(config, m_maincpu, 22'000'000); // Jungle King 2002 has a 22Mhz Xtal, what about the others?
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::igs_mahjong_map);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::m027_noppi_map<Xor>);
m_maincpu->out_port().set(FUNC(igs_m027_state::io_select_w<1>));
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
@ -1645,11 +1647,6 @@ void igs_m027_state::m027(machine_config &config)
TIMER(config, "scantimer").configure_scanline(FUNC(igs_m027_state::interrupt), "screen", 0, 1);
I8255A(config, m_ppi[0]);
m_ppi[0]->tri_pa_callback().set_constant(0x00);
m_ppi[0]->tri_pb_callback().set_constant(0x00);
m_ppi[0]->tri_pc_callback().set_constant(0x00);
IGS017_IGS031(config, m_igs017_igs031, 0);
m_igs017_igs031->set_text_reverse_bits(true);
m_igs017_igs031->in_pa_callback().set(NAME((&igs_m027_state::dsw_r<1, 0>)));
@ -1661,16 +1658,35 @@ void igs_m027_state::m027(machine_config &config)
OKIM6295(config, m_oki, 1000000, okim6295_device::PIN7_HIGH).add_route(ALL_OUTPUTS, "mono", 0.5);
}
void igs_m027_state::m027_xor(machine_config &config)
template <bool Xor>
void igs_m027_state::m027_1ppi(machine_config &config)
{
m027(config);
m027_noppi<Xor>(config);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::igs_mahjong_xor_map);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::m027_1ppi_map<Xor>);
I8255A(config, m_ppi[0]);
m_ppi[0]->tri_pa_callback().set_constant(0x00);
m_ppi[0]->tri_pb_callback().set_constant(0x00);
m_ppi[0]->tri_pc_callback().set_constant(0x00);
}
void igs_m027_state::slqz3_xor(machine_config &config)
template <bool Xor>
void igs_m027_state::m027_2ppis(machine_config &config)
{
m027_xor(config);
m027_1ppi<Xor>(config);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::m027_2ppis_map<Xor>);
I8255A(config, m_ppi[1]);
m_ppi[0]->tri_pa_callback().set_constant(0x00);
m_ppi[0]->tri_pb_callback().set_constant(0x00);
m_ppi[0]->tri_pc_callback().set_constant(0x00);
}
void igs_m027_state::slqz3(machine_config &config)
{
m027_1ppi<true>(config);
m_maincpu->in_port().set(FUNC(igs_m027_state::slqz3_gpio_r)); // what lives here?
@ -1685,9 +1701,9 @@ void igs_m027_state::slqz3_xor(machine_config &config)
HOPPER(config, m_hopper, attotime::from_msec(50));
}
void igs_m027_state::qlgs_xor(machine_config &config)
void igs_m027_state::qlgs(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->in_port().set_ioport("PLAYER");
m_maincpu->out_port().append(m_oki, FUNC(okim6295_device::set_rom_bank)).rshift(3);
@ -1698,9 +1714,9 @@ void igs_m027_state::qlgs_xor(machine_config &config)
m_igs017_igs031->in_pc_callback().set_ioport("JOY");
}
void igs_m027_state::lhdmg_xor(machine_config &config)
void igs_m027_state::lhdmg(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->in_port().set(FUNC(igs_m027_state::lhdmg_gpio_r));
@ -1715,11 +1731,11 @@ void igs_m027_state::lhdmg_xor(machine_config &config)
HOPPER(config, m_hopper, attotime::from_msec(50));
}
void igs_m027_state::cjddz_xor(machine_config &config)
void igs_m027_state::cjddz(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::cjddz_xor_map);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::cjddz_map);
m_maincpu->in_port().set_ioport("PLAYER");
m_oki->set_addrmap(0, &igs_m027_state::oki_128k_map);
@ -1735,16 +1751,16 @@ void igs_m027_state::cjddz_xor(machine_config &config)
HOPPER(config, m_hopper, attotime::from_msec(50));
}
void igs_m027_state::lhzb4_xor(machine_config &config)
void igs_m027_state::lhzb4(machine_config &config)
{
cjddz_xor(config);
cjddz(config);
m_oki->set_clock(2'000'000);
}
void igs_m027_state::lthy_xor(machine_config &config)
void igs_m027_state::lthy(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_ppi[0]->in_pa_callback().set_ioport("TEST");
m_ppi[0]->in_pb_callback().set(NAME((&igs_m027_state::kbd_r<1, 0, 2>)));
@ -1755,16 +1771,16 @@ void igs_m027_state::lthy_xor(machine_config &config)
m_igs017_igs031->in_pc_callback().set_ioport("JOY");
}
void igs_m027_state::zhongguo_xor(machine_config &config)
void igs_m027_state::zhongguo(machine_config &config)
{
lthy_xor(config);
lthy(config);
HOPPER(config, m_hopper, attotime::from_msec(50));
}
void igs_m027_state::jking02_xor(machine_config &config)
void igs_m027_state::jking02(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->in_port().set_ioport("PLAYER");
@ -1773,9 +1789,9 @@ void igs_m027_state::jking02_xor(machine_config &config)
m_ppi[0]->out_pc_callback().set(FUNC(igs_m027_state::lamps_w<0>));
}
void igs_m027_state::mgzz_xor(machine_config &config)
void igs_m027_state::mgzz(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_ppi[0]->out_pa_callback().set(FUNC(igs_m027_state::mahjong_output_w));
m_ppi[0]->in_pb_callback().set_ioport("TEST");
@ -1788,9 +1804,9 @@ void igs_m027_state::mgzz_xor(machine_config &config)
HOPPER(config, m_hopper, attotime::from_msec(50));
}
void igs_m027_state::oceanpar_xor(machine_config &config)
void igs_m027_state::oceanpar(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->in_port().set_ioport("PLAYER");
m_maincpu->out_port().append(m_oki, FUNC(okim6295_device::set_rom_bank)).rshift(3);
@ -1803,11 +1819,11 @@ void igs_m027_state::oceanpar_xor(machine_config &config)
TICKET_DISPENSER(config, m_ticket, attotime::from_msec(200));
}
void igs_m027_state::tripslot_xor(machine_config &config)
void igs_m027_state::tripslot(machine_config &config)
{
m027_xor(config);
m027_1ppi<true>(config);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::tripslot_xor_map);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::tripslot_map);
m_maincpu->in_port().set_ioport("PLAYER");
m_maincpu->out_port().append(FUNC(igs_m027_state::tripslot_okibank_low_w)).rshift(3);
@ -1820,19 +1836,20 @@ void igs_m027_state::tripslot_xor(machine_config &config)
void igs_m027_state::extradrw(machine_config &config)
{
m027(config);
m027_2ppis<false>(config);
m_maincpu->set_addrmap(AS_PROGRAM, &igs_m027_state::extradrw_map);
//m_ppi[0]->in_pa_callback().set(...);
//m_ppi[0]->in_pb_callback().set(...);
//m_ppi[0]->out_pc_callback().set(...);
I8255A(config, m_ppi[1]);
m_ppi[1]->tri_pa_callback().set_constant(0x00);
m_ppi[1]->tri_pb_callback().set_constant(0x00);
m_ppi[1]->tri_pc_callback().set_constant(0x00);
//m_ppi[1]->out_pa_callback().set(...);
//m_ppi[1]->out_pb_callback().set(...);
//m_ppi[1]->in_pc_callback().set(...);
}
void igs_m027_state::chessc2_xor(machine_config &config)
void igs_m027_state::chessc2(machine_config &config)
{
m027_xor(config);
m027_noppi<true>(config);
m_maincpu->in_port().set_ioport("PLAYER");
}
@ -2955,37 +2972,37 @@ void igs_m027_state::init_chessc2()
***************************************************************************/
// Complete dumps
GAME( 1999, slqz3, 0, slqz3_xor, slqz3, igs_m027_state, init_slqz3, ROT0, "IGS", "Shuang Long Qiang Zhu 3 (China, VS107C)", 0 )
GAME( 1999, qlgs, 0, qlgs_xor, qlgs, igs_m027_state, init_qlgs, ROT0, "IGS", "Que Long Gaoshou", MACHINE_NODEVICE_LAN )
GAME( 1999, lhdmg, 0, lhdmg_xor, lhdmg, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Da Manguan", 0 )
GAME( 1999, lhdmgp, lhdmg, lhdmg_xor, lhdmg, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Da Manguan Plus", 0 )
GAME( 1999, lhzb3, 0, lhdmg_xor, lhzb3, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Zhengba III", 0 )
GAME( 2004, lhzb4, 0, lhzb4_xor, lhzb4, igs_m027_state, init_lhzb4, ROT0, "IGS", "Long Hu Zhengba 4", 0 )
GAME( 1999, lthy, 0, lthy_xor, lthy, igs_m027_state, init_lthy, ROT0, "IGS", "Long Teng Hu Yue", MACHINE_NODEVICE_LAN )
GAME( 2000, zhongguo, 0, zhongguo_xor, zhongguo, igs_m027_state, init_zhongguo, ROT0, "IGS", "Zhongguo Chu Da D", 0 )
GAMEL( 200?, jking02, 0, jking02_xor, jking02, igs_m027_state, init_jking02, ROT0, "IGS", "Jungle King 2002 (V209US)", MACHINE_NODEVICE_LAN, layout_jking02 )
GAME( 2003, mgzz, 0, mgzz_xor, mgzz, igs_m027_state, init_mgzz, ROT0, "IGS", "Manguan Zhizun (V101CN)", 0 )
GAME( 2003, mgzza, mgzz, mgzz_xor, mgzza, igs_m027_state, init_mgzz, ROT0, "IGS", "Manguan Zhizun (V100CN)", 0 )
GAME( 2007, mgcs3, 0, lhzb4_xor, mgcs3, igs_m027_state, init_mgcs3, ROT0, "IGS", "Manguan Caishen 3 (V101CN)", 0 )
GAMEL( 1999, oceanpar, 0, oceanpar_xor, oceanpar, igs_m027_state, init_oceanpar, ROT0, "IGS", "Ocean Paradise (V105US)", 0, layout_oceanpar ) // 1999 copyright in ROM
GAMEL( 1999, oceanpara, oceanpar, oceanpar_xor, oceanpara,igs_m027_state, init_oceanpar, ROT0, "IGS", "Ocean Paradise (V101US)", 0, layout_oceanpar ) // 1999 copyright in ROM
GAMEL( 1999, fruitpar, 0, oceanpar_xor, oceanpar, igs_m027_state, init_fruitpar, ROT0, "IGS", "Fruit Paradise (V214)", 0, layout_oceanpar )
GAMEL( 1999, fruitpara, fruitpar, oceanpar_xor, fruitpara,igs_m027_state, init_fruitpar, ROT0, "IGS", "Fruit Paradise (V206US)", 0, layout_oceanpar )
GAME( 200?, cjddz, 0, cjddz_xor, cjddz, igs_m027_state, init_cjddz, ROT0, "IGS", "Chaoji Dou Dizhu", 0 )
GAMEL( 2007, tripslot, 0, tripslot_xor, tripslot, igs_m027_state, init_tripslot, ROT0, "IGS", "Triple Slot (V200VE)", 0, layout_tripslot ) // 2007 date in internal ROM at least, could be later, default settings password is all 'start 1'
GAME( 1999, slqz3, 0, slqz3, slqz3, igs_m027_state, init_slqz3, ROT0, "IGS", "Shuang Long Qiang Zhu 3 (China, VS107C)", 0 )
GAME( 1999, qlgs, 0, qlgs, qlgs, igs_m027_state, init_qlgs, ROT0, "IGS", "Que Long Gaoshou", MACHINE_NODEVICE_LAN )
GAME( 1999, lhdmg, 0, lhdmg, lhdmg, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Da Manguan", 0 )
GAME( 1999, lhdmgp, lhdmg, lhdmg, lhdmg, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Da Manguan Plus", 0 )
GAME( 1999, lhzb3, 0, lhdmg, lhzb3, igs_m027_state, init_lhdmg, ROT0, "IGS", "Long Hu Zhengba III", 0 )
GAME( 2004, lhzb4, 0, lhzb4, lhzb4, igs_m027_state, init_lhzb4, ROT0, "IGS", "Long Hu Zhengba 4", 0 )
GAME( 1999, lthy, 0, lthy, lthy, igs_m027_state, init_lthy, ROT0, "IGS", "Long Teng Hu Yue", MACHINE_NODEVICE_LAN )
GAME( 2000, zhongguo, 0, zhongguo, zhongguo, igs_m027_state, init_zhongguo, ROT0, "IGS", "Zhongguo Chu Da D", 0 )
GAMEL( 200?, jking02, 0, jking02, jking02, igs_m027_state, init_jking02, ROT0, "IGS", "Jungle King 2002 (V209US)", MACHINE_NODEVICE_LAN, layout_jking02 )
GAME( 2003, mgzz, 0, mgzz, mgzz, igs_m027_state, init_mgzz, ROT0, "IGS", "Manguan Zhizun (V101CN)", 0 )
GAME( 2003, mgzza, mgzz, mgzz, mgzza, igs_m027_state, init_mgzz, ROT0, "IGS", "Manguan Zhizun (V100CN)", 0 )
GAME( 2007, mgcs3, 0, lhzb4, mgcs3, igs_m027_state, init_mgcs3, ROT0, "IGS", "Manguan Caishen 3 (V101CN)", 0 )
GAMEL( 1999, oceanpar, 0, oceanpar, oceanpar, igs_m027_state, init_oceanpar, ROT0, "IGS", "Ocean Paradise (V105US)", 0, layout_oceanpar ) // 1999 copyright in ROM
GAMEL( 1999, oceanpara, oceanpar, oceanpar, oceanpara,igs_m027_state, init_oceanpar, ROT0, "IGS", "Ocean Paradise (V101US)", 0, layout_oceanpar ) // 1999 copyright in ROM
GAMEL( 1999, fruitpar, 0, oceanpar, oceanpar, igs_m027_state, init_fruitpar, ROT0, "IGS", "Fruit Paradise (V214)", 0, layout_oceanpar )
GAMEL( 1999, fruitpara, fruitpar, oceanpar, fruitpara,igs_m027_state, init_fruitpar, ROT0, "IGS", "Fruit Paradise (V206US)", 0, layout_oceanpar )
GAME( 200?, cjddz, 0, cjddz, cjddz, igs_m027_state, init_cjddz, ROT0, "IGS", "Chaoji Dou Dizhu", 0 )
GAMEL( 2007, tripslot, 0, tripslot, tripslot, igs_m027_state, init_tripslot, ROT0, "IGS", "Triple Slot (V200VE)", 0, layout_tripslot ) // 2007 date in internal ROM at least, could be later, default settings password is all 'start 1'
// this has a 2nd 8255
GAME( 2001, extradrw, 0, extradrw, base, igs_m027_state, init_extradrw, ROT0, "IGS", "Extra Draw (V100VE)", MACHINE_NOT_WORKING )
// these have an IGS025 protection device instead of the 8255
GAME( 2002, chessc2, 0, chessc2_xor, chessc2, igs_m027_state, init_chessc2, ROT0, "IGS", "Chess Challenge II", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION )
GAME( 2002, chessc2, 0, chessc2, chessc2, igs_m027_state, init_chessc2, ROT0, "IGS", "Chess Challenge II", MACHINE_NOT_WORKING | MACHINE_UNEMULATED_PROTECTION )
// Incomplete dumps
GAME( 1999, amazonia, 0, m027, amazonia, igs_m027_state, init_amazonia, ROT0, "IGS", "Amazonia King (V104BR)", MACHINE_NOT_WORKING )
GAME( 1999, amazonkp, amazonia, m027, amazonia, igs_m027_state, init_amazonia, ROT0, "IGS", "Amazonia King Plus (V204BR)", MACHINE_NOT_WORKING )
GAME( 2005, olympic5, 0, m027, base, igs_m027_state, init_olympic5, ROT0, "IGS", "Olympic 5 (V112US)", MACHINE_NOT_WORKING ) // IGS FOR V112US 2005 02 14
GAME( 2003, olympic5a, olympic5, m027, base, igs_m027_state, init_olympic5, ROT0, "IGS", "Olympic 5 (V107US)", MACHINE_NOT_WORKING ) // IGS FOR V107US 2003 10 2
GAME( 200?, luckycrs, 0, m027, base, igs_m027_state, init_luckycrs, ROT0, "IGS", "Lucky Cross (V106SA)", MACHINE_NOT_WORKING )
GAME( 2003, amazoni2, 0, m027, base, igs_m027_state, init_amazoni2, ROT0, "IGS", "Amazonia King II (V202BR)", MACHINE_NOT_WORKING )
GAME( 2002, sdwx, 0, m027, base, igs_m027_state, init_sdwx, ROT0, "IGS", "Sheng Dan Wu Xian", MACHINE_NOT_WORKING ) // aka Christmas 5 Line? (or Amazonia King II, shares roms at least?)
GAME( 200?, klxyj, 0, m027, base, igs_m027_state, init_klxyj, ROT0, "IGS", "Kuai Le Xi You Ji", MACHINE_NOT_WORKING )
GAME( 1999, amazonia, 0, m027_1ppi<false>, amazonia, igs_m027_state, init_amazonia, ROT0, "IGS", "Amazonia King (V104BR)", MACHINE_NOT_WORKING )
GAME( 1999, amazonkp, amazonia, m027_1ppi<false>, amazonia, igs_m027_state, init_amazonia, ROT0, "IGS", "Amazonia King Plus (V204BR)", MACHINE_NOT_WORKING )
GAME( 2005, olympic5, 0, m027_1ppi<false>, base, igs_m027_state, init_olympic5, ROT0, "IGS", "Olympic 5 (V112US)", MACHINE_NOT_WORKING ) // IGS FOR V112US 2005 02 14
GAME( 2003, olympic5a, olympic5, m027_1ppi<false>, base, igs_m027_state, init_olympic5, ROT0, "IGS", "Olympic 5 (V107US)", MACHINE_NOT_WORKING ) // IGS FOR V107US 2003 10 2
GAME( 200?, luckycrs, 0, m027_1ppi<false>, base, igs_m027_state, init_luckycrs, ROT0, "IGS", "Lucky Cross (V106SA)", MACHINE_NOT_WORKING )
GAME( 2003, amazoni2, 0, m027_1ppi<false>, base, igs_m027_state, init_amazoni2, ROT0, "IGS", "Amazonia King II (V202BR)", MACHINE_NOT_WORKING )
GAME( 2002, sdwx, 0, m027_1ppi<false>, base, igs_m027_state, init_sdwx, ROT0, "IGS", "Sheng Dan Wu Xian", MACHINE_NOT_WORKING ) // aka Christmas 5 Line? (or Amazonia King II, shares roms at least?)
GAME( 200?, klxyj, 0, m027_1ppi<false>, base, igs_m027_state, init_klxyj, ROT0, "IGS", "Kuai Le Xi You Ji", MACHINE_NOT_WORKING )
// these have an IGS025 protection device instead of the 8255
GAME( 200?, gonefsh2, 0, m027, base, igs_m027_state, init_gonefsh2, ROT0, "IGS", "Gone Fishing 2", MACHINE_NOT_WORKING )
GAME( 200?, gonefsh2, 0, m027_noppi<false>,base, igs_m027_state, init_gonefsh2, ROT0, "IGS", "Gone Fishing 2", MACHINE_NOT_WORKING )

1
src/mame/igs/igs_m027_link.cpp
View File

@ -125,7 +125,6 @@ Notes:
#include "pgmcrypt.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "cpu/m68000/m68000.h"
#include "machine/nvram.h"
#include "machine/timer.h"

30
src/mame/igs/igs_m027xa.cpp
View File

@ -18,8 +18,6 @@ apparently attempting serial communication with something.
#include "pgmcrypt.h"
#include "xamcu.h"
#include "cpu/arm7/arm7core.h"
#include "machine/i8255.h"
#include "machine/nvram.h"
#include "machine/ticket.h"
@ -44,7 +42,6 @@ class igs_m027xa_state : public driver_device
public:
igs_m027xa_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_igs_mainram(*this, "igs_mainram"),
m_maincpu(*this, "maincpu"),
m_xa(*this, "xa"),
m_ppi(*this, "ppi8255"),
@ -73,7 +70,6 @@ protected:
virtual void video_start() override;
private:
optional_shared_ptr<u32> m_igs_mainram;
required_device<igs027a_cpu_device> m_maincpu;
required_device<igs_xa_mcu_subcpu_device> m_xa;
required_device<i8255_device> m_ppi;
@ -93,8 +89,6 @@ private:
bool m_irq_from_igs031;
u32 m_igs_40000014;
TIMER_DEVICE_CALLBACK_MEMBER(interrupt);
void pgm_create_dummy_internal_arm_region();
@ -111,8 +105,6 @@ private:
void output_w(u8 data);
void lamps_w(u8 data);
void igs_40000014_w(offs_t offset, u32 data, u32 mem_mask);
void xa_irq(int state);
u32 gpio_r();
@ -125,8 +117,6 @@ private:
void igs_m027xa_state::machine_reset()
{
m_irq_from_igs031 = false;
m_igs_40000014 = 0;
}
void igs_m027xa_state::machine_start()
@ -139,8 +129,6 @@ void igs_m027xa_state::machine_start()
save_item(NAME(m_io_select));
save_item(NAME(m_irq_from_igs031));
save_item(NAME(m_igs_40000014));
}
void igs_m027xa_state::video_start()
@ -157,14 +145,13 @@ void igs_m027xa_state::video_start()
void igs_m027xa_state::main_map(address_map &map)
{
map(0x08000000, 0x0807ffff).rom().region("user1", 0); // Game ROM
map(0x10000000, 0x100003ff).ram().share("igs_mainram"); // main RAM for ASIC?
map(0x18000000, 0x18007fff).ram().mirror(0xf8000).share("nvram");
map(0x38000000, 0x38007fff).rw(m_igs017_igs031, FUNC(igs017_igs031_device::read), FUNC(igs017_igs031_device::write));
map(0x38008000, 0x38008003).umask32(0x000000ff).rw(m_oki, FUNC(okim6295_device::read), FUNC(okim6295_device::write));
map(0x38009000, 0x38009003).rw(m_ppi, FUNC(i8255_device::read), FUNC(i8255_device::write));
map(0x3800c000, 0x3800c003).umask32(0x000000ff).w(FUNC(igs_m027xa_state::oki_bank_w));
map(0x40000014, 0x40000017).w(FUNC(igs_m027xa_state::igs_40000014_w));
map(0x50000000, 0x500003ff).umask32(0x000000ff).w(FUNC(igs_m027xa_state::xor_table_w));
@ -378,12 +365,6 @@ void igs_m027xa_state::lamps_w(u8 data)
}
void igs_m027xa_state::igs_40000014_w(offs_t offset, u32 data, u32 mem_mask)
{
// sets bit 1 before waiting on FIRQ, maybe it's an enable here?
m_igs_40000014 = data;
}
u32 igs_m027xa_state::gpio_r()
{
u32 ret = m_io_test[2].read_safe(0xfffff);
@ -418,7 +399,7 @@ void igs_m027xa_state::io_select_w(u8 data)
void igs_m027xa_state::xa_irq(int state)
{
if (state)
m_maincpu->trigger_irq(3);
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_maincpu->minimum_quantum_time()); // TODO: when is the IRQ line cleared?
}
u32 igs_m027xa_state::external_rom_r(offs_t offset)
@ -438,20 +419,17 @@ TIMER_DEVICE_CALLBACK_MEMBER(igs_m027xa_state::interrupt)
{
int scanline = param;
// should be using m_maincpu->trigger_irq with more compelx interrupt logic?
switch (scanline)
{
case 0:
if (m_igs_40000014 & 1)
m_maincpu->pulse_input_line(ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time()); // vbl?
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time()); // vbl?
m_irq_from_igs031 = false;
break;
case 240:
if (m_igs017_igs031->get_irq_enable())
{
m_irq_from_igs031 = true;
m_maincpu->trigger_irq(3);
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_maincpu->minimum_quantum_time()); // TODO: when is the IRQ line cleared?
}
break;
}

1
src/mame/igs/igs_m036.cpp
View File

@ -63,7 +63,6 @@ check more info and photo from cjdh2.zip!!!
#include "igs036crypt.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/okim6295.h"
#include "sound/tt5665.h"

1
src/mame/igs/pgm.h
View File

@ -11,7 +11,6 @@
#include "pgmcrypt.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "cpu/m68000/m68000.h"
#include "cpu/z80/z80.h"
#include "machine/gen_latch.h"

24
src/mame/igs/pgm2.cpp
View File

@ -683,8 +683,8 @@ INPUT_PORTS_END
void pgm2_state::irq(int state)
{
// logerror("irq\n");
if (state == ASSERT_LINE) m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
else m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
if (state == ASSERT_LINE) m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
else m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
void pgm2_state::machine_start()
@ -1444,10 +1444,6 @@ void pgm2_state::init_ddpdojt()
}
// currently we don't know how to derive address/data xor values from real keys, so we need both
static const kov3_module_key kov3_104_key = { { 0x40,0xac,0x30,0x00,0x47,0x49,0x00,0x00 } ,{ 0xeb,0x7d,0x8d,0x90,0x2c,0xf4,0x09,0x82 }, 0x18ec71, 0xb89d }; // fake zero-key
static const kov3_module_key kov3_102_key = { { 0x49,0xac,0xb0,0xec,0x47,0x49,0x95,0x38 } ,{ 0x09,0xbd,0xf1,0x31,0xe6,0xf0,0x65,0x2b }, 0x021d37, 0x81d0 };
static const kov3_module_key kov3_101_key = { { 0xc1,0x2c,0xc1,0xe5,0x3c,0xc1,0x59,0x9e } ,{ 0xf2,0xb2,0xf0,0x89,0x37,0xf2,0xc7,0x0b }, 0, 0xffff }; // real xor values is unknown
static const kov3_module_key kov3_100_key = { { 0x40,0xac,0x30,0x00,0x47,0x49,0x00,0x00 } ,{ 0x96,0xf0,0x91,0xe1,0xb3,0xf1,0xef,0x90 }, 0x3e8aa8, 0xc530 }; // fake zero-key
void pgm2_state::init_kov3()
{
@ -1472,24 +1468,40 @@ void pgm2_state::decrypt_kov3_module(u32 addrxor, u16 dataxor)
void pgm2_state::init_kov3_104()
{
static const kov3_module_key kov3_104_key = {
{ 0x40,0xac,0x30,0x00,0x47,0x49,0x00,0x00 },
{ 0xeb,0x7d,0x8d,0x90,0x2c,0xf4,0x09,0x82 },
0x18ec71, 0xb89d }; // fake zero-key
module_key = &kov3_104_key;
init_kov3();
}
void pgm2_state::init_kov3_102()
{
static const kov3_module_key kov3_102_key = {
{ 0x49,0xac,0xb0,0xec,0x47,0x49,0x95,0x38 },
{ 0x09,0xbd,0xf1,0x31,0xe6,0xf0,0x65,0x2b },
0x021d37, 0x81d0 };
module_key = &kov3_102_key;
init_kov3();
}
void pgm2_state::init_kov3_101()
{
static const kov3_module_key kov3_101_key = {
{ 0xc1,0x2c,0xc1,0xe5,0x3c,0xc1,0x59,0x9e },
{ 0xf2,0xb2,0xf0,0x89,0x37,0xf2,0xc7,0x0b },
0, 0xffff }; // real xor values is unknown
module_key = &kov3_101_key;
init_kov3();
}
void pgm2_state::init_kov3_100()
{
static const kov3_module_key kov3_100_key = {
{ 0x40,0xac,0x30,0x00,0x47,0x49,0x00,0x00 },
{ 0x96,0xf0,0x91,0xe1,0xb3,0xf1,0xef,0x90 },
0x3e8aa8, 0xc530 }; // fake zero-key
module_key = &kov3_100_key;
init_kov3();
}

42
src/mame/igs/pgm2.h
View File

@ -5,26 +5,20 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/ymz770.h"
#include "igs036crypt.h"
#include "screen.h"
#include "speaker.h"
#include "pgm2_memcard.h"
#include "cpu/arm7/arm7.h"
#include "machine/atmel_arm_aic.h"
#include "machine/nvram.h"
#include "machine/timer.h"
#include "machine/atmel_arm_aic.h"
#include "pgm2_memcard.h"
#include "sound/ymz770.h"
#include "emupal.h"
#include "screen.h"
#include "speaker.h"
#include "tilemap.h"
struct kov3_module_key
{
u8 key[8];
u8 sum[8];
u32 addr_xor; // 22bit
u16 data_xor;
};
class pgm2_state : public driver_device
{
@ -75,7 +69,22 @@ public:
void pgm2_module_rom_map(address_map &map);
void pgm2_ram_rom_map(address_map &map);
void pgm2_rom_map(address_map &map);
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
virtual void device_post_load() override;
private:
struct kov3_module_key
{
u8 key[8];
u8 sum[8];
u32 addr_xor; // 22bit
u16 data_xor;
};
u32 unk_startup_r();
u32 rtc_r();
u32 mcu_r(offs_t offset);
@ -109,11 +118,6 @@ private:
void encryption_do_w(u32 data);
void sprite_encryption_w(offs_t offset, u32 data, u32 mem_mask = ~0);
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
virtual void device_post_load() override;
TILE_GET_INFO_MEMBER(get_fg_tile_info);
TILE_GET_INFO_MEMBER(get_bg_tile_info);

1
src/mame/igs/pgm3.cpp
View File

@ -48,7 +48,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "emupal.h"
#include "screen.h"

6
src/mame/igs/pgmprot_igs027a_type2.cpp
View File

@ -47,7 +47,7 @@
u32 pgm_arm_type2_state::arm7_latch_arm_r(offs_t offset, u32 mem_mask)
{
if (!machine().side_effects_disabled())
m_prot->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE ); // guess
m_prot->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, CLEAR_LINE); // guess
LOGPROT("%s ARM7: Latch read: %08x (%08x)\n", machine().describe_context(), m_kov2_latchdata_68k_w, mem_mask);
return m_kov2_latchdata_68k_w;
@ -83,7 +83,7 @@ void pgm_arm_type2_state::arm7_latch_68k_w(offs_t offset, u16 data, u16 mem_mask
LOGPROT("%s M68K: Latch write: %04x (%04x)\n", machine().describe_context(), data & 0x0000ffff, mem_mask);
COMBINE_DATA(&m_kov2_latchdata_68k_w);
m_prot->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE ); // guess
m_prot->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, ASSERT_LINE); // guess
}
u16 pgm_arm_type2_state::arm7_ram_r(offs_t offset, u16 mem_mask)
@ -236,7 +236,7 @@ u32 pgm_arm_type2_state::ddp2_speedup_r(address_space &space)
if (pc == 0x080109b4)
{
/* if we've hit the loop where this is read and both values are 0 then the only way out is an interrupt */
int r4 = (m_prot->state_int(ARM7_R4));
int r4 = (m_prot->state_int(arm7_cpu_device::ARM7_R4));
r4 += 0xe;
if (r4 == 0x18002f9e)

2
src/mame/igs/pgmprot_igs027a_type3.cpp
View File

@ -98,7 +98,7 @@ u16 pgm_arm_type3_state::svg_68k_nmi_r()
void pgm_arm_type3_state::svg_68k_nmi_w(u16 data)
{
m_prot->pulse_input_line(ARM7_FIRQ_LINE, m_prot->minimum_quantum_time());
m_prot->pulse_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_prot->minimum_quantum_time());
}
void pgm_arm_type3_state::svg_latch_68k_w(offs_t offset, u16 data, u16 mem_mask)

1
src/mame/leapfrog/leapster_explorer.cpp
View File

@ -15,7 +15,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"

1
src/mame/mattel/pixtermu.cpp
View File

@ -47,7 +47,6 @@
#include "bus/generic/carts.h"
#include "bus/generic/slot.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "softlist_dev.h"

1
src/mame/misc/39in1.cpp
View File

@ -45,7 +45,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/eepromser.h"
#include "machine/pxa255.h"

4
src/mame/misc/3do_m.cpp
View File

@ -62,7 +62,7 @@ Expansion bus stuff:
#include "emu.h"
#include "3do.h"
#include "cpu/arm7/arm7core.h"
#include "cpu/arm7/arm7.h"
#include "debugger.h"
#include "screen.h"
@ -121,7 +121,7 @@ void _3do_state::m_request_fiq(uint32_t irq_req, uint8_t type)
if((m_clio.irq0 & m_clio.irq0_enable) || (m_clio.irq1 & m_clio.irq1_enable))
{
//printf("Go irq %08x & %08x %08x & %08x\n",m_clio.irq0, m_clio.irq0_enable, m_clio.irq1, m_clio.irq1_enable);
m_maincpu->pulse_input_line(ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time());
m_maincpu->pulse_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_maincpu->minimum_quantum_time());
}
}

1
src/mame/misc/belatra.cpp
View File

@ -46,7 +46,6 @@ Viking's Fun Mill
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/acorn_vidc.h"
#include "machine/arm_iomd.h"

5
src/mame/misc/nexus3d.cpp
View File

@ -15,7 +15,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/nandflash.h"
#include "emupal.h"
#include "screen.h"
@ -125,9 +124,9 @@ void nexus3d_state::IntReq(int level)
uint32_t inten = m_intmask ^ 0xffffffff;
if (m_intpend & inten)
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
else
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}

1
src/mame/misc/sanremmg.cpp
View File

@ -33,7 +33,6 @@ M30624FG (M16C/62A family) needs CPU core and dumping of internal ROM
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "emupal.h"
#include "screen.h"

9
src/mame/nintendo/gba.cpp
View File

@ -17,6 +17,7 @@
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/gb.h"
#include "softlist_dev.h"
#include "speaker.h"
@ -148,8 +149,8 @@ void gba_state::request_irq(uint32_t int_type)
// master enable?
if (IME & 1)
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
}
}
@ -1182,12 +1183,12 @@ uint32_t gba_state::gba_10000000_r(offs_t offset, uint32_t mem_mask)
{
auto &mspace = m_maincpu->space(AS_PROGRAM);
uint32_t data;
uint32_t pc = m_maincpu->state_int(ARM7_PC);
uint32_t pc = m_maincpu->state_int(arm7_cpu_device::ARM7_PC);
if (pc >= 0x10000000)
{
return 0;
}
uint32_t cpsr = m_maincpu->state_int(ARM7_CPSR);
uint32_t cpsr = m_maincpu->state_int(arm7_cpu_device::ARM7_CPSR);
if (T_IS_SET( cpsr))
{
data = mspace.read_dword(pc + 8);

8
src/mame/nintendo/nds.cpp
View File

@ -839,8 +839,8 @@ void nds_state::request_irq(int cpu, uint32_t int_type)
{
if (cpu == 0)
{
m_arm9->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_arm9->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_arm9->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_arm9->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
else
{
@ -851,8 +851,8 @@ void nds_state::request_irq(int cpu, uint32_t int_type)
m_arm7halted = false;
}
m_arm7->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_arm7->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_arm7->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_arm7->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
}
}

1
src/mame/nintendo/nds.h
View File

@ -6,7 +6,6 @@
#define MAME_NINTENDO_NDS_H
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/bankdev.h"
#include "machine/timer.h"

3
src/mame/nokia/nokia_3310.cpp
View File

@ -14,7 +14,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/intelfsh.h"
#include "video/pcd8544.h"
@ -242,7 +241,7 @@ void noki3310_state::machine_reset()
{
// according to the boot rom disassembly here http://www.nokix.pasjagsm.pl/help/blacksphere/sub_100hardware/sub_arm/sub_bootrom.htm
// flash entry point is at 0x200040, we can probably reassemble the above code, but for now this should be enough.
m_maincpu->set_state_int(ARM7_R15, 0x200040);
m_maincpu->set_state_int(arm7_cpu_device::ARM7_R15, 0x200040);
memset(m_mad2_regs, 0, 0x100);
m_mad2_regs[0x01] = 0x01; // power-on flag

1
src/mame/pinball/sam.cpp
View File

@ -54,7 +54,6 @@ ToDo:
*********************************************************************************************************************/
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
namespace {

4
src/mame/psion/psion5.cpp
View File

@ -125,8 +125,8 @@ void psion5mx_state::check_interrupts()
{
m_maincpu->resume(SUSPEND_REASON_HALT);
}
m_maincpu->set_input_line(ARM7_FIRQ_LINE, m_pending_ints & m_int_mask & IRQ_FIQ_MASK ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(ARM7_IRQ_LINE, m_pending_ints & m_int_mask & IRQ_IRQ_MASK ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, m_pending_ints & m_int_mask & IRQ_FIQ_MASK ? ASSERT_LINE : CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, m_pending_ints & m_int_mask & IRQ_IRQ_MASK ? ASSERT_LINE : CLEAR_LINE);
}
TIMER_CALLBACK_MEMBER(psion5mx_state::update_timer1)

1
src/mame/psion/psion5.h
View File

@ -15,7 +15,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "etna.h"
#include "sound/spkrdev.h"

1
src/mame/saturn/st17xx.cpp
View File

@ -37,7 +37,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "emupal.h"
#include "screen.h"

3
src/mame/sega/dc.cpp
View File

@ -14,7 +14,6 @@
#include "mie.h"
#include "cpu/sh/sh4.h"
#include "cpu/arm7/arm7core.h"
//#include "debugger.h"
@ -624,7 +623,7 @@ void dc_state::soundram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
void dc_state::aica_irq(int state)
{
m_soundcpu->set_input_line(ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
m_soundcpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
}
void dc_state::sh4_aica_irq(int state)

1
src/mame/sega/dc.h
View File

@ -12,7 +12,6 @@
#include "powervr2.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "cpu/sh/sh4.h"
#include "machine/timer.h"
#include "sound/aica.h"

1
src/mame/sega/dccons.cpp
View File

@ -59,7 +59,6 @@
#include "bus/ata/gdrom.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "cpu/sh/sh4.h"
#include "imagedev/cdromimg.h"
#include "machine/aicartc.h"

8
src/mame/sega/sega_beena.cpp
View File

@ -1679,15 +1679,15 @@ int32_t sega_9h0_0008_state::rescale_alpha_step(uint8_t step)
void sega_9h0_0008_state::request_irq()
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
void sega_9h0_0008_state::request_fiq()
{
if (m_requested_fiq) {
m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, CLEAR_LINE);
m_requested_fiq = false;
}

1
src/mame/sharp/wizard.cpp
View File

@ -62,7 +62,6 @@ More info:
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
#include "cpu/arm7/arm7.h" // wrong, needs CPU core
#include "cpu/arm7/arm7core.h"
#include "screen.h"
#include "softlist_dev.h"

4
src/mame/sharp/zaurus.cpp
View File

@ -1401,7 +1401,6 @@ Note:
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/locomo.h"
#include "machine/pxa255.h"
#include "machine/sa1110.h"
@ -1417,8 +1416,7 @@ Note:
#define PXA255_CLOCK 400000000
#define PXA270_CLOCK 416000000
namespace
{
namespace {
class zaurus_state : public driver_device
{

12
src/mame/skeleton/cxhumax.cpp
View File

@ -95,7 +95,7 @@ void cxhumax_state::cx_gxa_w(offs_t offset, uint32_t data, uint32_t mem_mask)
if((m_intctrl_regs[INTREG(INTGROUP2, INTIRQ)] & m_intctrl_regs[INTREG(INTGROUP2, INTENABLE)])
|| (m_intctrl_regs[INTREG(INTGROUP1, INTIRQ)] & m_intctrl_regs[INTREG(INTGROUP1, INTENABLE)]))
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
break;
default:
@ -298,7 +298,7 @@ TIMER_CALLBACK_MEMBER(cxhumax_state::timer_tick)
/* Interrupt if Timer interrupt is not masked in ITC_INTENABLE_REG */
if (m_intctrl_regs[INTREG(INTGROUP2, INTENABLE)] & INT_TIMER_BIT)
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
}
attotime period = attotime::from_hz(XTAL(54'000'000))*m_timer_regs.timer[param].timebase;
@ -394,7 +394,7 @@ void cxhumax_state::cx_uart2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
/* If INT is enabled at INT Ctrl raise it */
if(m_intctrl_regs[INTREG(INTGROUP1, INTENABLE)]&INT_UART2_BIT) {
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
}
}
@ -525,9 +525,9 @@ void cxhumax_state::cx_intctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask
/* check if */
if((m_intctrl_regs[INTREG(INTGROUP2, INTIRQ)] & m_intctrl_regs[INTREG(INTGROUP2, INTENABLE)])
|| (m_intctrl_regs[INTREG(INTGROUP1, INTIRQ)] & m_intctrl_regs[INTREG(INTGROUP1, INTENABLE)]))
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
else
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
@ -711,7 +711,7 @@ void cxhumax_state::cx_i2c1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
m_intctrl_regs[INTREG(INTGROUP1, INTSTATSET)] |= 1<<7;
if (m_intctrl_regs[INTREG(INTGROUP1, INTENABLE)] & (1<<7)) {
LOG("%s: (I2C1) Int\n", machine().describe_context());
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
break;
case I2C_STAT_REG:

3
src/mame/skeleton/cxhumax.h
View File

@ -6,9 +6,8 @@
#pragma once
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/intelfsh.h"
#include "machine/i2cmem.h"
#include "machine/intelfsh.h"
#include "machine/terminal.h"

1
src/mame/skeleton/digiblast.cpp
View File

@ -10,7 +10,6 @@
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/s3c2410.h"
#include "emupal.h"

3
src/mame/skeleton/easy_karaoke.cpp
View File

@ -82,7 +82,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
@ -164,7 +163,7 @@ void easy_karaoke_cartslot_state::machine_start()
void ivl_karaoke_state::machine_reset()
{
m_maincpu->set_state_int(ARM7_R15, 0x04000000);
m_maincpu->set_state_int(arm7_cpu_device::ARM7_R15, 0x04000000);
}
DEVICE_IMAGE_LOAD_MEMBER(easy_karaoke_cartslot_state::cart_load)

1
src/mame/skeleton/koto_zevio.cpp
View File

@ -6,7 +6,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "screen.h"
#include "speaker.h"

1
src/mame/skeleton/sansa_fuze.cpp
View File

@ -10,7 +10,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
namespace {

6
src/mame/sony/news_r3k.cpp
View File

@ -11,10 +11,10 @@
* - http://bitsavers.org/pdf/sony/news/Sony_NEWS_Technical_Manual_3ed_199103.pdf
*
* TODO:
* - lcd controller
* - screen params
* - LCD controller
* - screen timing parameters
* - floppy density/eject
* - centronics port
* - Centronics port
* - sound
* - other models, including slots/cards
*/

11
src/mame/sony/pockstat.cpp
View File

@ -34,7 +34,6 @@
#include "bus/generic/carts.h"
#include "bus/generic/slot.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "sound/dac.h"
#include "emupal.h"
#include "screen.h"
@ -336,21 +335,21 @@ void pockstat_state::set_interrupt_line(uint32_t line, int state)
const uint32_t new_irq = m_intc_regs.hold & m_intc_regs.enable & INT_IRQ_MASK;
if (new_irq)
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, ASSERT_LINE);
}
else
{
m_maincpu->set_input_line(ARM7_IRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_IRQ_LINE, CLEAR_LINE);
}
const uint32_t new_fiq = m_intc_regs.hold & m_intc_regs.enable & INT_FIQ_MASK;
if (new_fiq)
{
m_maincpu->set_input_line(ARM7_FIRQ_LINE, ASSERT_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, ASSERT_LINE);
}
else
{
m_maincpu->set_input_line(ARM7_FIRQ_LINE, CLEAR_LINE);
m_maincpu->set_input_line(arm7_cpu_device::ARM7_FIRQ_LINE, CLEAR_LINE);
}
}
@ -934,7 +933,7 @@ void pockstat_state::machine_start()
void pockstat_state::machine_reset()
{
m_maincpu->set_state_int(ARM7_R15, 0x4000000);
m_maincpu->set_state_int(arm7_cpu_device::ARM7_R15, 0x4000000);
m_flash_write_enable_count = 0;
m_flash_write_count = 0;

1
src/mame/tvgames/generalplus_gpl32612.cpp
View File

@ -23,7 +23,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"
#include "softlist_dev.h"

1
src/mame/tvgames/gpm4530a_lexibook_jg7420.cpp
View File

@ -6,7 +6,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "machine/spi_sdcard.h"
#include "screen.h"

1
src/mame/tvgames/monkey_king_3b.cpp
View File

@ -65,7 +65,6 @@ TODO:
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "emupal.h"
#include "screen.h"

1
src/mame/tvgames/titan_soc.cpp
View File

@ -64,7 +64,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "emupal.h"
#include "screen.h"

1
src/mame/vtech/innotv_innotabmax.cpp
View File

@ -60,7 +60,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"

1
src/mame/vtech/storio.cpp
View File

@ -24,7 +24,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"

1
src/mame/vtech/vtech_innotab.cpp
View File

@ -15,7 +15,6 @@
#include "emu.h"
#include "cpu/arm7/arm7.h"
#include "cpu/arm7/arm7core.h"
#include "bus/generic/slot.h"
#include "bus/generic/carts.h"