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sh4drc: optimize FPU CMP instructions (nw)

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This commit is contained in:
arbee 2018-05-16 13:35:06 -04:00
parent 59686860c9
commit 523df415fa
1 changed files with 8 additions and 20 deletions
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28
src/devices/cpu/sh/sh4.cpp
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@ -3517,26 +3517,20 @@ bool sh34_base_device::generate_group_15_FDIV(drcuml_block &block, compiler_stat
bool sh34_base_device::generate_group_15_FCMP_EQ(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) bool sh34_base_device::generate_group_15_FCMP_EQ(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{ {
UML_MOV(block, I1, 0);
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0); UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum); UML_JMPc(block, COND_Z, compiler.labelnum);
UML_AND(block, I0, uml::mem(&m_sh2_state->sr), ~SH_T);
UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14)); UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14));
UML_MOVc(block, COND_Z, I1, SH_T); UML_SETc(block, COND_Z, I0);
UML_OR(block, I0, I0, I1); UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
UML_MOV(block, uml::mem(&m_sh2_state->sr), I0);
UML_JMP(block, compiler.labelnum+1); UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum: UML_LABEL(block, compiler.labelnum++); // labelnum:
UML_AND(block, I0, uml::mem(&m_sh2_state->sr), ~SH_T);
UML_FSCMP(block, FPS32(Rm), FPS32(Rn)); UML_FSCMP(block, FPS32(Rm), FPS32(Rn));
UML_MOVc(block, COND_Z, I1, SH_T); UML_SETc(block, COND_Z, I0);
UML_OR(block, I0, I0, I1); UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
UML_MOV(block, uml::mem(&m_sh2_state->sr), I0);
UML_LABEL(block, compiler.labelnum++); // labelnum+1: UML_LABEL(block, compiler.labelnum++); // labelnum+1:
return true; return true;
@ -3544,26 +3538,20 @@ bool sh34_base_device::generate_group_15_FCMP_EQ(drcuml_block &block, compiler_s
bool sh34_base_device::generate_group_15_FCMP_GT(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc) bool sh34_base_device::generate_group_15_FCMP_GT(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{ {
UML_MOV(block, I1, 0);
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0); UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum); UML_JMPc(block, COND_Z, compiler.labelnum);
UML_AND(block, I0, uml::mem(&m_sh2_state->sr), ~SH_T);
UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14)); UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14));
UML_MOVc(block, COND_C, I1, SH_T); UML_SETc(block, COND_C, I0);
UML_OR(block, I0, I0, I1); UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
UML_MOV(block, uml::mem(&m_sh2_state->sr), I0);
UML_JMP(block, compiler.labelnum+1); UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum: UML_LABEL(block, compiler.labelnum++); // labelnum:
UML_AND(block, I0, uml::mem(&m_sh2_state->sr), ~SH_T);
UML_FSCMP(block, FPS32(Rm), FPS32(Rn)); UML_FSCMP(block, FPS32(Rm), FPS32(Rn));
UML_MOVc(block, COND_C, I1, SH_T); UML_SETc(block, COND_C, I0);
UML_OR(block, I0, I0, I1); UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
UML_MOV(block, uml::mem(&m_sh2_state->sr), I0);
UML_LABEL(block, compiler.labelnum++); // labelnum+1: UML_LABEL(block, compiler.labelnum++); // labelnum+1:
return true; return true;