diff --git a/src/mame/drivers/namcos21.cpp b/src/mame/drivers/namcos21.cpp index f04b1cd8ba1..c9c134d4faf 100644 --- a/src/mame/drivers/namcos21.cpp +++ b/src/mame/drivers/namcos21.cpp @@ -67,7 +67,7 @@ STATUS: - posirq handling broken Driver's Eyes - crashes + Left and Right screen TODO: (*) Extract DSP BIOS @@ -1501,7 +1501,7 @@ static ADDRESS_MAP_START( winrun_gpu_map, AS_PROGRAM, 16, namcos21_state ) AM_RANGE(0x000000, 0x07ffff) AM_ROM AM_RANGE(0x100000, 0x100001) AM_READWRITE(winrun_gpu_color_r,winrun_gpu_color_w) /* ? */ AM_RANGE(0x180000, 0x19ffff) AM_RAM /* work RAM */ - AM_RANGE(0x1c0000, 0x1fffff) AM_READWRITE(namcos21_68k_gpu_C148_r,namcos21_68k_gpu_C148_w) + AM_RANGE(0x1c0000, 0x1fffff) AM_DEVICE("gpu_intc", namco_c148_device, map) AM_RANGE(0x200000, 0x20ffff) AM_RAM AM_SHARE("gpu_comram") AM_RANGE(0x400000, 0x40ffff) AM_RAM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette") AM_RANGE(0x410000, 0x41ffff) AM_RAM_DEVWRITE("palette", palette_device, write_ext) AM_SHARE("palette_ext") @@ -2007,6 +2007,8 @@ static MACHINE_CONFIG_START( winrun, namcos21_state ) MCFG_CPU_PROGRAM_MAP(winrun_gpu_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos21_state, namcos2_68k_gpu_vblank) + MCFG_NAMCO_C148_ADD("gpu_intc") + MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame */ MCFG_MACHINE_START_OVERRIDE(namcos21_state,namcos21) diff --git a/src/mame/includes/namcos21.h b/src/mame/includes/namcos21.h index e4e9e4c6adb..bf38b81dac4 100644 --- a/src/mame/includes/namcos21.h +++ b/src/mame/includes/namcos21.h @@ -6,6 +6,7 @@ #include "namcos2.h" #include "machine/namcoio_gearbox.h" +#include "machine/namco_c148.h" #define NAMCOS21_POLY_FRAME_WIDTH 496 #define NAMCOS21_POLY_FRAME_HEIGHT 480 @@ -54,7 +55,8 @@ public: m_ptrom24(*this,"point24"), m_ptrom16(*this,"point16"), m_dsp(*this, "dsp"), - m_io_gearbox(*this, "gearbox") + m_io_gearbox(*this, "gearbox"), + m_gpu_intc(*this, "gpu_intc") { } optional_shared_ptr m_winrun_dspbios; @@ -68,6 +70,7 @@ public: optional_device m_dsp; optional_device m_io_gearbox; + optional_device m_gpu_intc; std::unique_ptr m_videoram; std::unique_ptr m_winrun_dspcomram; diff --git a/src/mame/machine/namco_c148.cpp b/src/mame/machine/namco_c148.cpp new file mode 100644 index 00000000000..0c7dceb71c1 --- /dev/null +++ b/src/mame/machine/namco_c148.cpp @@ -0,0 +1,100 @@ +// license:BSD-3-Clause +// copyright-holders: +/*************************************************************************** + + Namco C148 Interrupt Controller + +***************************************************************************/ +/* +Interrupt Controller C148 1C0000-1FFFFF R/W D00-D02 + ???????? 1C0XXX + ???????? 1C2XXX + ???????? 1C4XXX + Master/Slave IRQ level 1C6XXX D00-D02 + EXIRQ level 1C8XXX D00-D02 + POSIRQ level 1CAXXX D00-D02 + SCIRQ level 1CCXXX D00-D02 + VBLANK IRQ level 1CEXXX D00-D02 + ???????? 1D0XXX + ???????? 1D4000 trigger master/slave INT? + + Acknowlegde Master/Slave IRQ 1D6XXX ack master/slave INT + Acknowledge EXIRQ 1D8XXX + Acknowledge POSIRQ 1DAXXX + Acknowledge SCIRQ 1DCXXX + Acknowledge VBLANK IRQ 1DEXXX + + EEPROM Ready status 1E0XXX R D01 + Sound CPU Reset control 1E2XXX W D01 + Slave 68000 & IO CPU Reset 1E4XXX W D01 + Watchdog reset kicker 1E6XXX W + */ + +#include "emu.h" +#include "namco_c148.h" + + + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + +// device type definition +const device_type NAMCO_C148 = &device_creator; + + +//************************************************************************** +// LIVE DEVICE +//************************************************************************** + +//------------------------------------------------- +// namco_c148_device - constructor +//------------------------------------------------- + +namco_c148_device::namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) + : device_t(mconfig, NAMCO_C148, "Namco C148 Interrupt Controller", tag, owner, clock, "namco_c148", __FILE__) +{ +} + +// (*) denotes master CPU only +DEVICE_ADDRESS_MAP_START( map, 16, namco_c148_device ) +// AM_RANGE(0x06000, 0x07fff) // CPUIRQ lv +// AM_RANGE(0x08000, 0x09fff) // EXIRQ lv +// AM_RANGE(0x0a000, 0x0bfff) // POSIRQ lv +// AM_RANGE(0x0c000, 0x0dfff) // SCIRQ lv +// AM_RANGE(0x0e000, 0x0ffff) // VBlank IRQ lv + +// AM_RANGE(0x16000, 0x17fff) // CPUIRQ ack +// AM_RANGE(0x18000, 0x19fff) // EXIRQ ack +// AM_RANGE(0x1a000, 0x1bfff) // POSIRQ ack +// AM_RANGE(0x1c000, 0x1dfff) // SCIRQ ack +// AM_RANGE(0x1e000, 0x1ffff) // VBlank IRQ ack +// AM_RANGE(0x20000, 0x21fff) // EEPROM ready status +// AM_RANGE(0x22000, 0x23fff) // sound CPU reset (*) +// AM_RANGE(0x24000, 0x25fff) // slave & i/o reset (*) + AM_RANGE(0x26000, 0x27fff) AM_NOP // watchdog +ADDRESS_MAP_END + + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void namco_c148_device::device_start() +{ +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void namco_c148_device::device_reset() +{ +} + +//************************************************************************** +// READ/WRITE HANDLERS +//************************************************************************** + diff --git a/src/mame/machine/namco_c148.h b/src/mame/machine/namco_c148.h new file mode 100644 index 00000000000..75e1aab3099 --- /dev/null +++ b/src/mame/machine/namco_c148.h @@ -0,0 +1,58 @@ +// license:BSD-3-Clause +// copyright-holders: +/*************************************************************************** + +Template for skeleton device + +***************************************************************************/ + +#pragma once + +#ifndef __NAMCO_C148DEV_H__ +#define __NAMCO_C148DEV_H__ + + + +//************************************************************************** +// INTERFACE CONFIGURATION MACROS +//************************************************************************** + +#define MCFG_NAMCO_C148_ADD(_tag) \ + MCFG_DEVICE_ADD(_tag, NAMCO_C148, 0) + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +// ======================> namco_c148_device + +class namco_c148_device : public device_t +{ +public: + // construction/destruction + namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + + DECLARE_ADDRESS_MAP(map, 16); + +protected: + // device-level overrides +// virtual void device_validity_check(validity_checker &valid) const; + virtual void device_start() override; + virtual void device_reset() override; +private: + // ... +}; + + +// device type definition +extern const device_type NAMCO_C148; + + + +//************************************************************************** +// GLOBAL VARIABLES +//************************************************************************** + + + +#endif