Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-23 00:39:36 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

pc_vga: added non-writable area if VRAM bank is set past the end of available VRAM on the S3 Trio64 and Virge. S3 BIOSes will now correctly probe RAM size and store it in the strapping registers.

Browse Source
This commit is contained in:
mahlemiut 2015-05-26 20:15:07 +12:00
parent 081000955c
commit 526aa03040
2 changed files with 46 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/emu/bus/isa/s3virge.c
View File

@ -162,12 +162,6 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index)
break;
case 0x36: // Configuration register 1
res = s3.strapping & 0x000000ff;
if(vga.svga_intf.vram_size == 0x200000)
res |= 0x80;
else if(vga.svga_intf.vram_size == 0x400000)
res |= 0x00;
else
res |= 0x80; // shouldn't get here...
break;
case 0x37: // Configuration register 2
res = (s3.strapping & 0x0000ff00) >> 8;
@ -714,12 +708,15 @@ READ8_MEMBER(s3virge_vga_device::mem_r)
{
if (svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb32_en)
{
int data;
UINT8 data;
if(offset & 0x10000)
return 0;
data = 0;
data = 0xff;
if(vga.sequencer.data[4] & 0x8)
data = vga.memory[offset + (svga.bank_r*0x10000)];
{
if(offset + (svga.bank_r*0x10000) < vga.svga_intf.vram_size)
data = vga.memory[offset + (svga.bank_r*0x10000)];
}
else
{
int i;
@ -727,12 +724,18 @@ READ8_MEMBER(s3virge_vga_device::mem_r)
for(i=0;i<4;i++)
{
if(vga.sequencer.map_mask & 1 << i)
data |= vga.memory[offset*4+i+(svga.bank_r*0x10000)];
{
if(offset*4+i+(svga.bank_r*0x10000) < vga.svga_intf.vram_size)
data |= vga.memory[offset*4+i+(svga.bank_r*0x10000)];
}
}
}
return data;
}
return vga_device::mem_r(space,offset,mem_mask);
if((offset + (svga.bank_r*0x10000)) < vga.svga_intf.vram_size)
return vga_device::mem_r(space,offset,mem_mask);
else
return 0xff;
}
WRITE8_MEMBER(s3virge_vga_device::mem_w)
@ -749,18 +752,25 @@ WRITE8_MEMBER(s3virge_vga_device::mem_w)
if(offset & 0x10000)
return;
if(vga.sequencer.data[4] & 0x8)
vga.memory[(offset + (svga.bank_w*0x10000)) % vga.svga_intf.vram_size] = data;
{
if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga.memory[(offset + (svga.bank_w*0x10000))] = data;
}
else
{
int i;
for(i=0;i<4;i++)
{
if(vga.sequencer.map_mask & 1 << i)
vga.memory[(offset*4+i+(svga.bank_w*0x10000)) % vga.svga_intf.vram_size] = data;
{
if((offset*4+i+(svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga.memory[(offset*4+i+(svga.bank_w*0x10000))] = data;
}
}
}
return;
}
vga_device::mem_w(space,offset,data,mem_mask);
if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga_device::mem_w(space,offset,data,mem_mask);
}

40
src/emu/video/pc_vga.c
View File

@ -2561,16 +2561,6 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index)
break;
case 0x36: // Configuration register 1
res = s3.strapping & 0x000000ff; // PCI (not really), Fast Page Mode DRAM
if(vga.svga_intf.vram_size == 0x80000)
res |= 0xe0;
else if(vga.svga_intf.vram_size == 0x100000)
res |= 0xc0;
else if(vga.svga_intf.vram_size == 0x200000)
res |= 0x80;
else if(vga.svga_intf.vram_size == 0x400000)
res |= 0x00;
else
res |= 0xe0; // shouldn't get here...
break;
case 0x37: // Configuration register 2
res = (s3.strapping & 0x0000ff00) >> 8; // enable chipset, 64k BIOS size, internal DCLK/MCLK
@ -2989,8 +2979,6 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
case 0x6a:
svga.bank_w = data & 0x3f;
svga.bank_r = svga.bank_w;
if(data & 0x60)
popmessage("TODO: s3 bank selects above 1M\n");
break;
case 0x6f:
if(s3.reg_lock2 == 0xa5)
@ -4645,7 +4633,10 @@ READ8_MEMBER(s3_vga_device::mem_r)
return 0;
data = 0;
if(vga.sequencer.data[4] & 0x8)
data = vga.memory[(offset + (svga.bank_r*0x10000)) % vga.svga_intf.vram_size];
{
if((offset + (svga.bank_r*0x10000)) < vga.svga_intf.vram_size)
data = vga.memory[(offset + (svga.bank_r*0x10000))];
}
else
{
int i;
@ -4653,12 +4644,18 @@ READ8_MEMBER(s3_vga_device::mem_r)
for(i=0;i<4;i++)
{
if(vga.sequencer.map_mask & 1 << i)
data |= vga.memory[(offset*4+i+(svga.bank_r*0x10000)) % vga.svga_intf.vram_size];
{
if((offset*4+i+(svga.bank_r*0x10000)) < vga.svga_intf.vram_size)
data |= vga.memory[(offset*4+i+(svga.bank_r*0x10000))];
}
}
}
return data;
}
return vga_device::mem_r(space,offset,mem_mask);
if((offset + (svga.bank_r*0x10000)) < vga.svga_intf.vram_size)
return vga_device::mem_r(space,offset,mem_mask);
else
return 0xff;
}
WRITE8_MEMBER(s3_vga_device::mem_w)
@ -4906,20 +4903,27 @@ WRITE8_MEMBER(s3_vga_device::mem_w)
if(offset & 0x10000)
return;
if(vga.sequencer.data[4] & 0x8)
vga.memory[(offset + (svga.bank_w*0x10000)) % vga.svga_intf.vram_size] = data;
{
if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga.memory[(offset + (svga.bank_w*0x10000))] = data;
}
else
{
int i;
for(i=0;i<4;i++)
{
if(vga.sequencer.map_mask & 1 << i)
vga.memory[(offset*4+i+(svga.bank_w*0x10000)) % vga.svga_intf.vram_size] = data;
{
if((offset*4+i+(svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga.memory[(offset*4+i+(svga.bank_w*0x10000))] = data;
}
}
}
return;
}
vga_device::mem_w(space,offset,data,mem_mask);
if((offset + (svga.bank_w*0x10000)) < vga.svga_intf.vram_size)
vga_device::mem_w(space,offset,data,mem_mask);
}
/******************************************