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h8: H8S analog I/O is now routed to the driver like in the original H8s [R. Belmont]

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R. Belmont 2012-12-02 22:04:10 +00:00
parent 610ed62433
commit 52a5317274
2 changed files with 27 additions and 2 deletions
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16
src/emu/cpu/h83002/h8.h
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@ -87,6 +87,14 @@ enum
H8_ADC_2_L, H8_ADC_2_L,
H8_ADC_3_H, H8_ADC_3_H,
H8_ADC_3_L, H8_ADC_3_L,
H8_ADC_4_H,
H8_ADC_4_L,
H8_ADC_5_H,
H8_ADC_5_L,
H8_ADC_6_H,
H8_ADC_6_L,
H8_ADC_7_H,
H8_ADC_7_L,
// serial ports // serial ports
H8_SERIAL_0 = 0x30, H8_SERIAL_0 = 0x30,
@ -193,6 +201,14 @@ enum
#define H8S_IO_SCMR2 H8S_IO(0xFF8E) #define H8S_IO_SCMR2 H8S_IO(0xFF8E)
// ADC // ADC
#define H8S_IO_ADDRA H8S_IO(0xFF90)
#define H8S_IO_ADDRB H8S_IO(0xFF92)
#define H8S_IO_ADDRC H8S_IO(0xFF94)
#define H8S_IO_ADDRD H8S_IO(0xFF96)
#define H8S_IO_ADDRE H8S_IO(0xFF98)
#define H8S_IO_ADDRF H8S_IO(0xFF9A)
#define H8S_IO_ADDRG H8S_IO(0xFF9C)
#define H8S_IO_ADDRH H8S_IO(0xFF9E)
#define H8S_IO_ADCSR H8S_IO(0xFFA0) #define H8S_IO_ADCSR H8S_IO(0xFFA0)
#define H8S_IO_ADCR H8S_IO(0xFFA1) #define H8S_IO_ADCR H8S_IO(0xFFA1)

13
src/emu/cpu/h83002/h8speriph.c
View File

@ -1384,7 +1384,6 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data)
verboselog( h8->device->machine(), 9, "%08X | %08X <- %02X\n", h8->ppc, H8S_IO_ADDR(offset), data); verboselog( h8->device->machine(), 9, "%08X | %08X <- %02X\n", h8->ppc, H8S_IO_ADDR(offset), data);
switch (offset) switch (offset)
{ {
#if 0
// SCI 0 // SCI 0
case H8S_IO_SSR0 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 0); break; case H8S_IO_SSR0 : h8->per_regs[offset] = data; if ((data & H8S_SSR_TDRE) == 0) h8s_sci_execute(h8, 0); break;
case H8S_IO_SCR0 : h8->per_regs[offset] = data; if (data & H8S_SCR_TIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(0)->int_tx); break; case H8S_IO_SCR0 : h8->per_regs[offset] = data; if (data & H8S_SCR_TIE) h8s2xxx_interrupt_request(h8, h8s_sci_entry(0)->int_tx); break;
@ -1407,8 +1406,8 @@ void h8s_onchip_reg_write_8_ddr(h83xx_state *h8, int offset, UINT8 data)
case H8S_IO_TCNT1 : h8s_tmr_x_write_tcnt( h8, 1, data); break; case H8S_IO_TCNT1 : h8s_tmr_x_write_tcnt( h8, 1, data); break;
case H8S_IO_TCORA1 : h8s_tmr_x_write_tcora( h8, 1, data); break; case H8S_IO_TCORA1 : h8s_tmr_x_write_tcora( h8, 1, data); break;
case H8S_IO_TCORB1 : h8s_tmr_x_write_tcorb( h8, 1, data); break; case H8S_IO_TCORB1 : h8s_tmr_x_write_tcorb( h8, 1, data); break;
#endif
case H8S_IO_IER:
case H8S_IO_IFR: case H8S_IO_IFR:
h8->per_regs[offset] = data; h8->per_regs[offset] = data;
break; break;
@ -1620,6 +1619,16 @@ UINT16 h8s_onchip_reg_read_16(h83xx_state *h8, int offset)
case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 3); break; case H8S_IO_TCNT3_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 3); break;
case H8S_IO_TCNT4_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 4); break; case H8S_IO_TCNT4_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 4); break;
case H8S_IO_TCNT5_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 5); break; case H8S_IO_TCNT5_H : if (h8->tpu_max == 6) data = h8s_tpu_x_read_tcnt( h8, 5); break;
case H8S_IO_ADDRA: case H8S_IO_ADDRB: case H8S_IO_ADDRC: case H8S_IO_ADDRD:
case H8S_IO_ADDRE: case H8S_IO_ADDRF: case H8S_IO_ADDRG: case H8S_IO_ADDRH:
{
int pbase = (offset - H8S_IO_ADDRA) + H8_ADC_0_H;
data = (h8->io->read_byte(pbase) << 8);
data |= h8->io->read_byte(pbase+1);
}
break;
default : default :
{ {
UINT8 b[2]; UINT8 b[2];