diff --git a/.gitattributes b/.gitattributes index 9b669f4bc91..d994221a944 100644 --- a/.gitattributes +++ b/.gitattributes @@ -6632,6 +6632,8 @@ src/mame/machine/btime.c svneol=native#text/plain src/mame/machine/bublbobl.c svneol=native#text/plain src/mame/machine/buggychl.c svneol=native#text/plain src/mame/machine/buggychl.h svneol=native#text/plain +src/mame/machine/c117.c svneol=native#text/plain +src/mame/machine/c117.h svneol=native#text/plain src/mame/machine/carpolo.c svneol=native#text/plain src/mame/machine/cchasm.c svneol=native#text/plain src/mame/machine/cchip.c svneol=native#text/plain diff --git a/src/mame/drivers/namcos1.c b/src/mame/drivers/namcos1.c index 9408e315483..d073d5d9d07 100644 --- a/src/mame/drivers/namcos1.c +++ b/src/mame/drivers/namcos1.c @@ -60,12 +60,7 @@ CUS151 protection [1] Memory map ---------- Main, Sub CPU: -Address decoding is entirely handled by CUS117, which is a simple MMU providing a -virtual address space 23 bits wide. The chip outputs the various enable lines for -RAM, ROM, etc., and bits 12-21 of the virtual address (therefore bit 22 is handled -only internally). There are 8 banks in the 6809 address space, each one redirectable -to a portion of the virtual address space. The main and sub CPUs are independent, -each one can set up its own banks. +Address decoding is entirely handled by CUS117; see machine/c117.c. Main & sub CPU memory map: @@ -179,7 +174,7 @@ Ernesto Corvi ernesto@imagina.com Updates by: -Vernon C. Brooks, Acho A. Tang, Nicola Salmoria +Vernon C. Brooks, Acho A. Tang, Nicola Salmoria, Alex W. Jackson Notes: @@ -220,7 +215,7 @@ Notes: TODO: -- There is still a big mistery about the first location of tri port ram, which is +- There is still a big mystery about the first location of tri port ram, which is shared among all four CPUs. See namcos1_mcu_patch_w() for the kludge: essentially, this location has to be 0xA6 for the games to work. However, the MCU first sets it to 0xA6, then zeroes it - and there doesn't seem to be any code anywhere for any CPU @@ -290,7 +285,7 @@ are programmed separately and may be 4,8,16,or 32 pixels. Sound: Namco custom 8 channel 16-bit stereo PSG for sound effects -registor array based 2 channel 8-bit DAC for voice +resistor array based 2 channel 8-bit DAC for voice Yamaha YM2151+YM3012 FM chip for background music Controls: @@ -342,29 +337,17 @@ C - uses sub board with support for player 3 and 4 controls #include "cpu/m6809/m6809.h" #include "cpu/m6800/m6800.h" #include "sound/2151intf.h" -#include "sound/dac.h" #include "machine/nvram.h" #include "includes/namcos1.h" /**********************************************************************/ -WRITE8_MEMBER(namcos1_state::namcos1_sub_firq_w) -{ - m_subcpu->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE); -} - WRITE8_MEMBER(namcos1_state::irq_ack_w) { space.device().execute().set_input_line(0, CLEAR_LINE); } -WRITE8_MEMBER(namcos1_state::firq_ack_w) -{ - space.device().execute().set_input_line(M6809_FIRQ_LINE, CLEAR_LINE); -} - - READ8_MEMBER(namcos1_state::dsw_r) { @@ -423,52 +406,36 @@ WRITE8_MEMBER(namcos1_state::namcos1_dac1_w) static ADDRESS_MAP_START( main_map, AS_PROGRAM, 8, namcos1_state ) - AM_RANGE(0x0000, 0x1fff) AM_RAMBANK("bank1") - AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank2") - AM_RANGE(0x4000, 0x5fff) AM_RAMBANK("bank3") - AM_RANGE(0x6000, 0x7fff) AM_RAMBANK("bank4") - AM_RANGE(0x8000, 0x9fff) AM_RAMBANK("bank5") - AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank6") - AM_RANGE(0xc000, 0xdfff) AM_RAMBANK("bank7") - AM_RANGE(0xe000, 0xefff) AM_WRITE(namcos1_bankswitch_w) - AM_RANGE(0xf000, 0xf000) AM_WRITE(namcos1_cpu_control_w) - AM_RANGE(0xf200, 0xf200) AM_WRITE(namcos1_watchdog_w) -// AM_RANGE(0xf400, 0xf400) AM_WRITENOP // unknown - AM_RANGE(0xf600, 0xf600) AM_WRITE(irq_ack_w) - AM_RANGE(0xf800, 0xf800) AM_WRITE(firq_ack_w) - AM_RANGE(0xfa00, 0xfa00) AM_WRITE(namcos1_sub_firq_w) // asserts FIRQ on CPU1 - AM_RANGE(0xfc00, 0xfc01) AM_WRITE(namcos1_subcpu_bank_w) - AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank8") + AM_RANGE(0x0000, 0xffff) AM_DEVREADWRITE("c117", namco_c117_device, main_r, main_w) ADDRESS_MAP_END - static ADDRESS_MAP_START( sub_map, AS_PROGRAM, 8, namcos1_state ) - AM_RANGE(0x0000, 0x1fff) AM_RAMBANK("bank9") - AM_RANGE(0x2000, 0x3fff) AM_RAMBANK("bank10") - AM_RANGE(0x4000, 0x5fff) AM_RAMBANK("bank11") - AM_RANGE(0x6000, 0x7fff) AM_RAMBANK("bank12") - AM_RANGE(0x8000, 0x9fff) AM_RAMBANK("bank13") - AM_RANGE(0xa000, 0xbfff) AM_RAMBANK("bank14") - AM_RANGE(0xc000, 0xdfff) AM_RAMBANK("bank15") - AM_RANGE(0xe000, 0xefff) AM_WRITE(namcos1_bankswitch_w) -// AM_RANGE(0xf000, 0xf000) AM_WRITENOP // IO Chip - AM_RANGE(0xf200, 0xf200) AM_WRITE(namcos1_watchdog_w) -// AM_RANGE(0xf400, 0xf400) AM_WRITENOP // ? - AM_RANGE(0xf600, 0xf600) AM_WRITE(irq_ack_w) - AM_RANGE(0xf800, 0xf800) AM_WRITE(firq_ack_w) - AM_RANGE(0xe000, 0xffff) AM_ROMBANK("bank16") + AM_RANGE(0x0000, 0xffff) AM_DEVREADWRITE("c117", namco_c117_device, sub_r, sub_w) +ADDRESS_MAP_END + +static ADDRESS_MAP_START( virtual_map, AS_PROGRAM, 8, namcos1_state ) + AM_RANGE(0x2c0000, 0x2c1fff) AM_WRITE(namcos1_3dcs_w) + AM_RANGE(0x2e0000, 0x2e7fff) AM_RAM_WRITE(namcos1_paletteram_w) AM_SHARE("paletteram") + AM_RANGE(0x2f0000, 0x2f7fff) AM_RAM_WRITE(namcos1_videoram_w) AM_SHARE("videoram") + AM_RANGE(0x2f8000, 0x2f9fff) AM_READWRITE(no_key_r, no_key_w) + AM_RANGE(0x2fc000, 0x2fcfff) AM_RAM_WRITE(namcos1_spriteram_w) AM_SHARE("spriteram") + AM_RANGE(0x2fd000, 0x2fd01f) AM_RAM AM_SHARE("pfcontrol") AM_MIRROR(0xfe0) + AM_RANGE(0x2fe000, 0x2fe3ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) AM_MIRROR(0xc00) /* PSG ( Shared ) */ + AM_RANGE(0x2ff000, 0x2ff7ff) AM_RAM AM_SHARE("triram") AM_MIRROR(0x800) + AM_RANGE(0x300000, 0x307fff) AM_RAM + AM_RANGE(0x400000, 0x7fffff) AM_ROM AM_REGION("user1", 0) ADDRESS_MAP_END static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, namcos1_state ) - AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("bank17") /* Banked ROMs */ + AM_RANGE(0x0000, 0x3fff) AM_ROMBANK("soundbank") /* Banked ROMs */ AM_RANGE(0x4000, 0x4001) AM_DEVREAD("ymsnd", ym2151_device, status_r) AM_RANGE(0x4000, 0x4001) AM_DEVREADWRITE("ymsnd", ym2151_device, read, write) AM_RANGE(0x5000, 0x53ff) AM_DEVREADWRITE("namco", namco_cus30_device, namcos1_cus30_r, namcos1_cus30_w) AM_MIRROR(0x400) /* PSG ( Shared ) */ - AM_RANGE(0x7000, 0x77ff) AM_RAMBANK("bank18") /* TRIRAM (shared) */ + AM_RANGE(0x7000, 0x77ff) AM_RAM AM_SHARE("triram") AM_RANGE(0x8000, 0x9fff) AM_RAM /* Sound RAM 3 */ AM_RANGE(0xc000, 0xc001) AM_WRITE(namcos1_sound_bankswitch_w) /* ROM bank selector */ - AM_RANGE(0xd001, 0xd001) AM_WRITE(namcos1_watchdog_w) + AM_RANGE(0xd001, 0xd001) AM_DEVWRITE("c117", namco_c117_device, sound_watchdog_w) AM_RANGE(0xe000, 0xe000) AM_WRITE(irq_ack_w) AM_RANGE(0xc000, 0xffff) AM_ROM ADDRESS_MAP_END @@ -480,9 +447,8 @@ static ADDRESS_MAP_START( mcu_map, AS_PROGRAM, 8, namcos1_state ) AM_RANGE(0x1000, 0x1003) AM_READ(dsw_r) AM_RANGE(0x1400, 0x1400) AM_READ_PORT("CONTROL0") AM_RANGE(0x1401, 0x1401) AM_READ_PORT("CONTROL1") - AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("bank20") /* banked ROM */ - AM_RANGE(0xc000, 0xc000) AM_WRITE(namcos1_mcu_patch_w) /* kludge! see notes */ - AM_RANGE(0xc000, 0xc7ff) AM_RAMBANK("bank19") /* TRIRAM (shared) */ + AM_RANGE(0x4000, 0xbfff) AM_ROMBANK("mcubank") /* banked ROM */ + AM_RANGE(0xc000, 0xc7ff) AM_RAM AM_SHARE("triram") AM_RANGE(0xc800, 0xcfff) AM_RAM AM_SHARE("nvram") /* EEPROM */ AM_RANGE(0xd000, 0xd000) AM_WRITE(namcos1_dac0_w) AM_RANGE(0xd400, 0xd400) AM_WRITE(namcos1_dac1_w) @@ -1082,6 +1048,11 @@ static MACHINE_CONFIG_START( ns1, namcos1_state ) MCFG_CPU_IO_MAP(mcu_port_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", namcos1_state, irq0_line_assert) + MCFG_DEVICE_ADD("c117", NAMCO_C117, 0) + MCFG_DEVICE_PROGRAM_MAP(virtual_map) + MCFG_CUS117_CPUS("maincpu", "subcpu") + MCFG_CUS117_SUBRES_CB(WRITELINE(namcos1_state, subres_w)) + // heavy sync required to prevent CPUs from fighting for video RAM access and going into deadlocks MCFG_QUANTUM_TIME(attotime::from_hz(38400)) diff --git a/src/mame/includes/namcos1.h b/src/mame/includes/namcos1.h index 853b9b15546..764119c18d0 100644 --- a/src/mame/includes/namcos1.h +++ b/src/mame/includes/namcos1.h @@ -1,50 +1,48 @@ +#include "machine/c117.h" #include "sound/dac.h" #include "sound/namco.h" -#define NAMCOS1_MAX_BANK 0x400 - -/* Bank handler definitions */ -struct bankhandler -{ - read8_delegate bank_handler_r; - write8_delegate bank_handler_w; - int bank_offset; - UINT8 *bank_pointer; -}; - class namcos1_state : public driver_device { public: namcos1_state(const machine_config &mconfig, device_type type, const char *tag) - : driver_device(mconfig, type, tag) , + : driver_device(mconfig, type, tag), m_maincpu(*this, "maincpu"), - m_audiocpu(*this, "audiocpu"), m_subcpu(*this, "subcpu"), + m_audiocpu(*this, "audiocpu"), m_mcu(*this, "mcu"), - m_cus30(*this, "namco"), + m_c117(*this, "c117"), m_dac(*this, "dac"), m_gfxdecode(*this, "gfxdecode"), - m_palette(*this, "palette") { } + m_palette(*this, "palette"), + m_paletteram(*this, "paletteram"), + m_videoram(*this, "videoram"), + m_spriteram(*this, "spriteram"), + m_playfield_control(*this, "pfcontrol"), + m_triram(*this, "triram"), + m_rom(*this, "user1") { } required_device m_maincpu; - required_device m_audiocpu; required_device m_subcpu; + required_device m_audiocpu; required_device m_mcu; - required_device m_cus30; + required_device m_c117; required_device m_dac; required_device m_gfxdecode; required_device m_palette; + required_shared_ptr m_paletteram; + required_shared_ptr m_videoram; + required_shared_ptr m_spriteram; + required_shared_ptr m_playfield_control; + required_shared_ptr m_triram; + + required_memory_region m_rom; + int m_dac0_value; int m_dac1_value; int m_dac0_gain; int m_dac1_gain; - UINT8 *m_paletteram; - UINT8 *m_triram; - UINT8 *m_s1ram; - UINT8 *m_dummyrom; - bankhandler m_bank_element[NAMCOS1_MAX_BANK]; - bankhandler m_active_bank[16]; int m_key_id; int m_key_reg; int m_key_rng; @@ -58,33 +56,25 @@ public: UINT8 m_key[8]; int m_mcu_patch_data; int m_reset; - int m_wdog; - int m_chip[16]; int m_input_count; int m_strobe; int m_strobe_count; int m_stored_input[2]; - UINT8 *m_videoram; UINT8 m_cus116[0x10]; - UINT8 *m_spriteram; - UINT8 m_playfield_control[0x20]; tilemap_t *m_bg_tilemap[6]; UINT8 *m_tilemap_maskdata; int m_copy_sprites; UINT8 m_drawmode_table[16]; - DECLARE_WRITE8_MEMBER(namcos1_sub_firq_w); + DECLARE_DIRECT_UPDATE_MEMBER(direct_handler_main); + DECLARE_DIRECT_UPDATE_MEMBER(direct_handler_sub); + DECLARE_WRITE_LINE_MEMBER(subres_w); DECLARE_WRITE8_MEMBER(irq_ack_w); - DECLARE_WRITE8_MEMBER(firq_ack_w); DECLARE_READ8_MEMBER(dsw_r); DECLARE_WRITE8_MEMBER(namcos1_coin_w); DECLARE_WRITE8_MEMBER(namcos1_dac_gain_w); DECLARE_WRITE8_MEMBER(namcos1_dac0_w); DECLARE_WRITE8_MEMBER(namcos1_dac1_w); DECLARE_WRITE8_MEMBER(namcos1_sound_bankswitch_w); - DECLARE_WRITE8_MEMBER(namcos1_cpu_control_w); - DECLARE_WRITE8_MEMBER(namcos1_watchdog_w); - DECLARE_WRITE8_MEMBER(namcos1_bankswitch_w); - DECLARE_WRITE8_MEMBER(namcos1_subcpu_bank_w); DECLARE_WRITE8_MEMBER(namcos1_mcu_bankswitch_w); DECLARE_WRITE8_MEMBER(namcos1_mcu_patch_w); DECLARE_READ8_MEMBER(quester_paddle_r); @@ -126,45 +116,9 @@ public: void screen_eof_namcos1(screen_device &screen, bool state); void namcos1_update_DACs(); void namcos1_init_DACs(); - DECLARE_READ8_MEMBER( namcos1_videoram_r ); DECLARE_WRITE8_MEMBER( namcos1_videoram_w ); DECLARE_WRITE8_MEMBER( namcos1_paletteram_w ); - DECLARE_READ8_MEMBER( namcos1_spriteram_r ); DECLARE_WRITE8_MEMBER( namcos1_spriteram_w ); - inline UINT8 bank_r(address_space &space, offs_t offset, int bank); - READ8_MEMBER( bank1_r ); - READ8_MEMBER( bank2_r ); - READ8_MEMBER( bank3_r ); - READ8_MEMBER( bank4_r ); - READ8_MEMBER( bank5_r ); - READ8_MEMBER( bank6_r ); - READ8_MEMBER( bank7_r ); - READ8_MEMBER( bank8_r ); - READ8_MEMBER( bank9_r ); - READ8_MEMBER( bank10_r ); - READ8_MEMBER( bank11_r ); - READ8_MEMBER( bank12_r ); - READ8_MEMBER( bank13_r ); - READ8_MEMBER( bank14_r ); - READ8_MEMBER( bank15_r ); - READ8_MEMBER( bank16_r ); - inline void bank_w(address_space &space, offs_t offset, UINT8 data, int bank); - WRITE8_MEMBER( bank1_w ); - WRITE8_MEMBER( bank2_w ); - WRITE8_MEMBER( bank3_w ); - WRITE8_MEMBER( bank4_w ); - WRITE8_MEMBER( bank5_w ); - WRITE8_MEMBER( bank6_w ); - WRITE8_MEMBER( bank7_w ); - WRITE8_MEMBER( bank8_w ); - WRITE8_MEMBER( bank9_w ); - WRITE8_MEMBER( bank10_w ); - WRITE8_MEMBER( bank11_w ); - WRITE8_MEMBER( bank12_w ); - WRITE8_MEMBER( bank13_w ); - WRITE8_MEMBER( bank14_w ); - WRITE8_MEMBER( bank15_w ); - WRITE8_MEMBER( bank16_w ); WRITE8_MEMBER( namcos1_3dcs_w ); READ8_MEMBER( no_key_r ); WRITE8_MEMBER( no_key_w ); @@ -174,31 +128,8 @@ public: WRITE8_MEMBER( key_type2_w ); READ8_MEMBER( key_type3_r ); WRITE8_MEMBER( key_type3_w ); - READ8_MEMBER( soundram_r ); - WRITE8_MEMBER( soundram_w ); - WRITE8_MEMBER( rom_w ); - READ8_MEMBER( unknown_r ); - WRITE8_MEMBER( unknown_w ); - void set_bank(int banknum, const bankhandler *handler); - void namcos1_bankswitch(int cpu, offs_t offset, UINT8 data); - void namcos1_install_bank(int start,int end,read8_delegate hr,write8_delegate hw,int offset,UINT8 *pointer); - void namcos1_build_banks(read8_delegate key_r,write8_delegate key_w); - struct namcos1_specific - { - /* keychip */ - read8_delegate key_r; - write8_delegate key_w; - int key_id; - int key_reg1; - int key_reg2; - int key_reg3; - int key_reg4; - int key_reg5; - int key_reg6; - }; - - void namcos1_driver_init(const struct namcos1_specific *specific ); + void namcos1_driver_init(); private: - inline void bg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram); - inline void fg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram); + inline offs_t direct_handler(int whichcpu, direct_read_data &direct, offs_t address); + inline void get_tile_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram); }; diff --git a/src/mame/machine/c117.c b/src/mame/machine/c117.c new file mode 100644 index 00000000000..5e9f8776897 --- /dev/null +++ b/src/mame/machine/c117.c @@ -0,0 +1,230 @@ +// license:BSD-3-Clause +// copyright-holders:Alex W. Jackson +/* +Namco Custom 117, used in System 1 + +CUS117 is a simple MMU that provides a 23 bit virtual address space for a pair +of M6809 CPUs. The chip outputs the various enable lines for RAM, ROM, video +customs, etc., and bits 12-21 of the virtual address (bit 22 of the virtual +address is handled internally: it selects between ROM and everything else) + +Each CPU's address space is evenly divided into eight 8KB banks, and each of +these banks can be directed to any portion of the virtual address space +(however, the last bank for each CPU is effectively read only, since writes to +E000-FFFF control CUS117 itself) + +The main and sub CPUs share the same address and data bus, but each CPU can +set up its own banks independently. The main CPU can also set the sub CPU's +last bank (E000-FFFF, where the 6809 reset and interrupt vectors reside) + +As well as being an MMU, CUS117 serves as the interrupt controller for the +two 6809s and as the reset generator for the entire system. +*/ + +#include "emu.h" +#include "cpu/m6809/m6809.h" +#include "machine/c117.h" + + +const device_type NAMCO_C117 = &device_creator; + + +//------------------------------------------------- +// namco_c117_device - constructor +//------------------------------------------------- + +namco_c117_device::namco_c117_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : device_t(mconfig, NAMCO_C117, "Namco CUS117", tag, owner, clock, "namco_c117", __FILE__), + device_memory_interface(mconfig, *this), + m_subres_cb(*this), + m_program_config("program", ENDIANNESS_BIG, 8, 23), + m_maincpu_tag(NULL), + m_subcpu_tag(NULL) +{ +} + +//------------------------------------------------- +// set_cpu_tags - set the tags of the two CPUs +// connected to the device +//------------------------------------------------- + +void namco_c117_device::set_cpu_tags(device_t &device, const char *maintag, const char *subtag) +{ + namco_c117_device &c117 = downcast(device); + c117.m_maincpu_tag = maintag; + c117.m_subcpu_tag = subtag; +} + + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void namco_c117_device::device_start() +{ + m_subres_cb.resolve_safe(); + + m_program = &space(AS_PROGRAM); + + cpu_device *maincpu = siblingdevice(m_maincpu_tag); + cpu_device *subcpu = siblingdevice(m_subcpu_tag); + + m_cpuexec[0] = maincpu; + m_cpuexec[1] = subcpu; + m_cpudirect[0] = &maincpu->space(AS_PROGRAM).direct(); + m_cpudirect[1] = &subcpu->space(AS_PROGRAM).direct(); + + memset(&m_offsets, 0, sizeof(m_offsets)); + m_subres = m_wdog = 0; + save_item(NAME(m_offsets)); + save_item(NAME(m_subres)); + save_item(NAME(m_wdog)); +} + + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void namco_c117_device::device_reset() +{ + // default MMU setup for main CPU + m_offsets[0][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt + m_offsets[0][1] = 0x0180 * 0x2000; // bank1 = 0x180(RAM) - evidence: berabohm + m_offsets[0][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7) + + // default MMU setup for sub CPU + m_offsets[1][0] = 0x0180 * 0x2000; // bank0 = 0x180(RAM) - evidence: wldcourt + m_offsets[1][7] = 0x03ff * 0x2000; // bank7 = 0x3ff(PRG7) + + m_cpudirect[0]->force_update(); + m_cpudirect[1]->force_update(); + + m_subres = m_wdog = 0; + m_subres_cb(ASSERT_LINE); + + // reset the main CPU so it picks up the reset vector from the correct bank + m_cpuexec[0]->set_input_line(INPUT_LINE_RESET, PULSE_LINE); +} + + +READ8_MEMBER(namco_c117_device::main_r) +{ + return m_program->read_byte(remap(0, offset)); +} + +READ8_MEMBER(namco_c117_device::sub_r) +{ + return m_program->read_byte(remap(1, offset)); +} + +WRITE8_MEMBER(namco_c117_device::main_w) +{ + if (offset < 0xe000) + m_program->write_byte(remap(0, offset), data); + else + register_w(0, offset, data); +} + +WRITE8_MEMBER(namco_c117_device::sub_w) +{ + if (offset < 0xe000) + m_program->write_byte(remap(1, offset), data); + else + register_w(1, offset, data); +} + +// FIXME: the sound CPU watchdog is probably in CUS121, and definitely isn't in CUS117 +// however, until the watchdog is a device and it's possible to have two independent +// watchdogs in a machine, it's easiest to handle it here +WRITE8_MEMBER(namco_c117_device::sound_watchdog_w) +{ + kick_watchdog(2); +} + + +void namco_c117_device::register_w(int whichcpu, offs_t offset, UINT8 data) +{ + int reg = (offset >> 9) & 0xf; + bool unknown_reg = false; + + switch (reg) + { + case 0: + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + bankswitch(whichcpu, reg, offset & 1, data); + break; + case 8: // F000 - SUBRES (halt/reset everything but main CPU) + if (whichcpu == 0) + { + m_subres = data & 1; + m_subres_cb(m_subres ? CLEAR_LINE : ASSERT_LINE); + } + else + unknown_reg = true; + break; + case 9: // F200 - kick watchdog + kick_watchdog(whichcpu); + break; +// case 10: // F400 - unknown but used +// break; + case 11: // F600 - IRQ ack + m_cpuexec[whichcpu]->set_input_line(M6809_IRQ_LINE, CLEAR_LINE); + break; + case 12: // F800 - FIRQ ack + m_cpuexec[whichcpu]->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE); + break; + case 13: // FA00 - assert FIRQ on sub CPU + if (whichcpu == 0) + m_cpuexec[1]->set_input_line(M6809_FIRQ_LINE, ASSERT_LINE); + else + unknown_reg = true; + break; + case 14: // FC00 - set initial ROM bank for sub CPU + if (whichcpu == 0) + { + m_offsets[1][7] = 0x600000 | (data * 0x2000); + m_cpudirect[1]->force_update(); + } + else + unknown_reg = true; + break; + default: + unknown_reg = true; + } + if (unknown_reg) + logerror("'%s' writing to unknown CUS117 register %04X = %02X\n", (whichcpu ? m_subcpu_tag : m_maincpu_tag), offset, data); +} + +void namco_c117_device::bankswitch(int whichcpu, int whichbank, int a0, UINT8 data) +{ + UINT32 &bank = m_offsets[whichcpu][whichbank]; + + // even writes set a22-a21; odd writes set a20-a13 + if (a0 == 0) + bank = (bank & 0x1fe000) | ((data & 0x03) * 0x200000); + else + bank = (bank & 0x600000) | (data * 0x2000); + + m_cpudirect[whichcpu]->force_update(); +} + +void namco_c117_device::kick_watchdog(int whichcpu) +{ + // FIXME: change to 3 once sound CPU watchdog is separated from this device + static const int ALL_CPU_MASK = 7; + + m_wdog |= (1 << whichcpu); + + if (m_wdog == ALL_CPU_MASK || !m_subres) + { + m_wdog = 0; + machine().watchdog_reset(); + } +} diff --git a/src/mame/machine/c117.h b/src/mame/machine/c117.h new file mode 100644 index 00000000000..de36fa39682 --- /dev/null +++ b/src/mame/machine/c117.h @@ -0,0 +1,84 @@ +// license:BSD-3-Clause +// copyright-holders:Alex W. Jackson + +#pragma once + +#ifndef __C117_H__ +#define __C117_H__ + + +//************************************************************************** +// INTERFACE CONFIGURATION MACROS +//************************************************************************** + +#define MCFG_CUS117_CPUS(_maincpu, _subcpu) \ + namco_c117_device::set_cpu_tags(*device, _maincpu, _subcpu); + +#define MCFG_CUS117_SUBRES_CB(_devcb) \ + devcb = &namco_c117_device::set_subres_cb(*device, DEVCB_##_devcb); + + +//*************************************************************************** +// TYPE DEFINITIONS +//*************************************************************************** + +class namco_c117_device : + public device_t, + public device_memory_interface +{ +public: + //construction/destruction + namco_c117_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // static configuration + static void set_cpu_tags(device_t &device, const char *maintag, const char *subtag); + template static devcb_base &set_subres_cb(device_t &device, _Object object) { return downcast(device).m_subres_cb.set_callback(object); } + + DECLARE_READ8_MEMBER(main_r); + DECLARE_READ8_MEMBER(sub_r); + DECLARE_WRITE8_MEMBER(main_w); + DECLARE_WRITE8_MEMBER(sub_w); + + // FIXME: this doesn't belong here + DECLARE_WRITE8_MEMBER(sound_watchdog_w); + + offs_t remap(int whichcpu, offs_t offset) { return m_offsets[whichcpu][offset>>13] | (offset & 0x1fff); } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; } + +private: + // internal helpers + void register_w(int whichcpu, offs_t offset, UINT8 data); + void bankswitch(int whichcpu, int whichbank, int a0, UINT8 data); + void kick_watchdog(int whichcpu); + + // internal state + UINT32 m_offsets[2][8]; + UINT8 m_subres, m_wdog; + + // callbacks + devcb_write_line m_subres_cb; + + // address space + const address_space_config m_program_config; + address_space * m_program; + + // cpu interfaces + device_execute_interface * m_cpuexec[2]; + direct_read_data * m_cpudirect[2]; + + // configuration + const char * m_maincpu_tag; + const char * m_subcpu_tag; +}; + +// device type definition +extern const device_type NAMCO_C117; + +#endif diff --git a/src/mame/machine/namcos1.c b/src/mame/machine/namcos1.c index 02df6883427..5f82256b36e 100644 --- a/src/mame/machine/namcos1.c +++ b/src/mame/machine/namcos1.c @@ -1,5 +1,4 @@ #include "emu.h" -#include "sound/ym2151.h" #include "includes/namcos1.h" @@ -9,52 +8,6 @@ * * *******************************************************************************/ -/* hardware elements of 1Mbytes physical memory space */ - -UINT8 namcos1_state::bank_r(address_space &space, offs_t offset, int bank) -{ - return m_active_bank[bank].bank_handler_r(space, offset + m_active_bank[bank].bank_offset, 0xff); -} - -READ8_MEMBER( namcos1_state::bank1_r ) { return bank_r(space, offset, 0); } -READ8_MEMBER( namcos1_state::bank2_r ) { return bank_r(space, offset, 1); } -READ8_MEMBER( namcos1_state::bank3_r ) { return bank_r(space, offset, 2); } -READ8_MEMBER( namcos1_state::bank4_r ) { return bank_r(space, offset, 3); } -READ8_MEMBER( namcos1_state::bank5_r ) { return bank_r(space, offset, 4); } -READ8_MEMBER( namcos1_state::bank6_r ) { return bank_r(space, offset, 5); } -READ8_MEMBER( namcos1_state::bank7_r ) { return bank_r(space, offset, 6); } -READ8_MEMBER( namcos1_state::bank8_r ) { return bank_r(space, offset, 7); } -READ8_MEMBER( namcos1_state::bank9_r ) { return bank_r(space, offset, 8); } -READ8_MEMBER( namcos1_state::bank10_r ) { return bank_r(space, offset, 9); } -READ8_MEMBER( namcos1_state::bank11_r ) { return bank_r(space, offset, 10); } -READ8_MEMBER( namcos1_state::bank12_r ) { return bank_r(space, offset, 11); } -READ8_MEMBER( namcos1_state::bank13_r ) { return bank_r(space, offset, 12); } -READ8_MEMBER( namcos1_state::bank14_r ) { return bank_r(space, offset, 13); } -READ8_MEMBER( namcos1_state::bank15_r ) { return bank_r(space, offset, 14); } -READ8_MEMBER( namcos1_state::bank16_r ) { return bank_r(space, offset, 15); } - -void namcos1_state::bank_w(address_space &space, offs_t offset, UINT8 data, int bank) -{ - m_active_bank[bank].bank_handler_w(space, offset + m_active_bank[bank].bank_offset, data, 0xff); -} - -WRITE8_MEMBER( namcos1_state::bank1_w ) { bank_w(space, offset, data, 0); } -WRITE8_MEMBER( namcos1_state::bank2_w ) { bank_w(space, offset, data, 1); } -WRITE8_MEMBER( namcos1_state::bank3_w ) { bank_w(space, offset, data, 2); } -WRITE8_MEMBER( namcos1_state::bank4_w ) { bank_w(space, offset, data, 3); } -WRITE8_MEMBER( namcos1_state::bank5_w ) { bank_w(space, offset, data, 4); } -WRITE8_MEMBER( namcos1_state::bank6_w ) { bank_w(space, offset, data, 5); } -WRITE8_MEMBER( namcos1_state::bank7_w ) { bank_w(space, offset, data, 6); } -WRITE8_MEMBER( namcos1_state::bank8_w ) { bank_w(space, offset, data, 7); } -WRITE8_MEMBER( namcos1_state::bank9_w ) { bank_w(space, offset, data, 8); } -WRITE8_MEMBER( namcos1_state::bank10_w ) { bank_w(space, offset, data, 9); } -WRITE8_MEMBER( namcos1_state::bank11_w ) { bank_w(space, offset, data, 10); } -WRITE8_MEMBER( namcos1_state::bank12_w ) { bank_w(space, offset, data, 11); } -WRITE8_MEMBER( namcos1_state::bank13_w ) { bank_w(space, offset, data, 12); } -WRITE8_MEMBER( namcos1_state::bank14_w ) { bank_w(space, offset, data, 13); } -WRITE8_MEMBER( namcos1_state::bank15_w ) { bank_w(space, offset, data, 14); } -WRITE8_MEMBER( namcos1_state::bank16_w ) { bank_w(space, offset, data, 15); } - WRITE8_MEMBER( namcos1_state::namcos1_3dcs_w ) { if (offset & 1) popmessage("LEFT"); @@ -484,8 +437,6 @@ CPU #0 PC e45a: keychip read 0030 [discarded] READ8_MEMBER( namcos1_state::key_type3_r ) { - int op; - // logerror("CPU %s PC %04x: keychip read %04x\n", space.device().tag(), space.device().safe_pc(), offset); /* I need to handle blastoff's read from 0858. The game previously writes to 0858, @@ -494,7 +445,7 @@ READ8_MEMBER( namcos1_state::key_type3_r ) The schematics don't show A11 being used, so I go for this handling. */ - op = (offset & 0x70) >> 4; + int op = (offset & 0x70) >> 4; if (op == m_key_reg) return m_key_id; if (op == m_key_rng) return machine().rand(); @@ -527,7 +478,7 @@ WRITE8_MEMBER(namcos1_state::namcos1_sound_bankswitch_w) UINT8 *rom = memregion("audiocpu")->base() + 0xc000; int bank = (data & 0x70) >> 4; - membank("bank17")->set_base(rom + 0x4000 * bank); + membank("soundbank")->set_base(rom + 0x4000 * bank); } @@ -538,206 +489,46 @@ WRITE8_MEMBER(namcos1_state::namcos1_sound_bankswitch_w) * * *******************************************************************************/ +// These direct handlers are merely for speed - taking two trips +// through the memory system for every opcode fetch is rather slow -WRITE8_MEMBER(namcos1_state::namcos1_cpu_control_w) +DIRECT_UPDATE_MEMBER(namcos1_state::direct_handler_main) +{ + return direct_handler(0, direct, address); +} + +DIRECT_UPDATE_MEMBER(namcos1_state::direct_handler_sub) +{ + return direct_handler(1, direct, address); +} + +inline offs_t namcos1_state::direct_handler(int whichcpu, direct_read_data &direct, offs_t address) +{ + offs_t remapped_address = m_c117->remap(whichcpu, address); + + // if not in ROM, return + if (remapped_address < 0x400000) return address; + + // calculate the base of the 8KB ROM page + remapped_address &= 0x3fe000; + + direct.explicit_configure(address & 0xe000, address | 0x1fff, 0x1fff, &m_rom->base()[remapped_address]); + return ~0; +} + + +WRITE_LINE_MEMBER(namcos1_state::subres_w) { // logerror("reset control pc=%04x %02x\n",space.device().safe_pc(),data); - if ((data & 1) ^ m_reset) + if (state != m_reset) { m_mcu_patch_data = 0; - m_reset = data & 1; + m_reset = state; } - m_subcpu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE); - m_audiocpu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE); - m_mcu->set_input_line(INPUT_LINE_RESET, (data & 1) ? CLEAR_LINE : ASSERT_LINE); -} - - - -WRITE8_MEMBER(namcos1_state::namcos1_watchdog_w) -{ - if (&space.device() == m_maincpu) - m_wdog |= 1; - else if (&space.device() == m_subcpu) - m_wdog |= 2; - else if (&space.device() == m_audiocpu) - m_wdog |= 4; - - if (m_wdog == 7 || !m_reset) - { - m_wdog = 0; - watchdog_reset_w(space,0,0); - } -} - - - -READ8_MEMBER( namcos1_state::soundram_r ) -{ - if (offset < 0x1000) - { - offset &= 0x3ff; - - /* CUS 30 */ - - return machine().device("namco")->namcos1_cus30_r(space,offset); - } - else - { - offset &= 0x7ff; - - /* shared ram */ - return m_triram[offset]; - } -} - -WRITE8_MEMBER( namcos1_state::soundram_w ) -{ - if (offset < 0x1000) - { - offset &= 0x3ff; - - /* CUS 30 */ - - machine().device("namco")->namcos1_cus30_w(space,offset,data); - } - else - { - offset &= 0x7ff; - - /* shared ram */ - m_triram[offset] = data; - return; - } -} - -/* ROM handlers */ - -WRITE8_MEMBER( namcos1_state::rom_w ) -{ - logerror("CPU %s PC %04x: warning - write %02x to rom address %04x\n", space.device().tag(), space.device().safe_pc(), data, offset); -} - -/* error handlers */ -READ8_MEMBER( namcos1_state::unknown_r ) -{ - logerror("CPU %s PC %04x: warning - read from unknown chip\n", space.device().tag(), space.device().safe_pc() ); -// popmessage("CPU %s PC %04x: read from unknown chip", space.device().tag(), space.device().safe_pc() ); - return 0; -} - -WRITE8_MEMBER( namcos1_state::unknown_w ) -{ - logerror("CPU %s PC %04x: warning - wrote to unknown chip\n", space.device().tag(), space.device().safe_pc() ); -// popmessage("CPU %s PC %04x: wrote to unknown chip", space.device().tag(), space.device().safe_pc() ); -} - -/* Main bankswitching routine */ -void namcos1_state::set_bank(int banknum, const bankhandler *handler) -{ - static const char *const banktags[] = { - "bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7", "bank8", - "bank9", "bank10", "bank11", "bank12", "bank13", "bank14", "bank15", "bank16" - }; - - static const struct { read8_delegate func; } io_bank_handler_r[16] = - { - { read8_delegate(FUNC(namcos1_state::bank1_r),this) }, { read8_delegate(FUNC(namcos1_state::bank2_r),this) }, { read8_delegate(FUNC(namcos1_state::bank3_r),this) }, { read8_delegate(FUNC(namcos1_state::bank4_r),this) }, - { read8_delegate(FUNC(namcos1_state::bank5_r),this) }, { read8_delegate(FUNC(namcos1_state::bank6_r),this) }, { read8_delegate(FUNC(namcos1_state::bank7_r),this) }, { read8_delegate(FUNC(namcos1_state::bank8_r),this) }, - { read8_delegate(FUNC(namcos1_state::bank9_r),this) }, { read8_delegate(FUNC(namcos1_state::bank10_r),this) }, { read8_delegate(FUNC(namcos1_state::bank11_r),this) }, { read8_delegate(FUNC(namcos1_state::bank12_r),this) }, - { read8_delegate(FUNC(namcos1_state::bank13_r),this) }, { read8_delegate(FUNC(namcos1_state::bank14_r),this) }, { read8_delegate(FUNC(namcos1_state::bank15_r),this) }, { read8_delegate(FUNC(namcos1_state::bank16_r),this) } - }; - - static const struct { write8_delegate func; } io_bank_handler_w[16] = - { - { write8_delegate(FUNC(namcos1_state::bank1_w),this) }, { write8_delegate(FUNC(namcos1_state::bank2_w),this) }, { write8_delegate(FUNC(namcos1_state::bank3_w),this) }, { write8_delegate(FUNC(namcos1_state::bank4_w),this) }, - { write8_delegate(FUNC(namcos1_state::bank5_w),this) }, { write8_delegate(FUNC(namcos1_state::bank6_w),this) }, { write8_delegate(FUNC(namcos1_state::bank7_w),this) }, { write8_delegate(FUNC(namcos1_state::bank8_w),this) }, - { write8_delegate(FUNC(namcos1_state::bank9_w),this) }, { write8_delegate(FUNC(namcos1_state::bank10_w),this) }, { write8_delegate(FUNC(namcos1_state::bank11_w),this) }, { write8_delegate(FUNC(namcos1_state::bank12_w),this) }, - { write8_delegate(FUNC(namcos1_state::bank13_w),this) }, { write8_delegate(FUNC(namcos1_state::bank14_w),this) }, { write8_delegate(FUNC(namcos1_state::bank15_w),this) }, { write8_delegate(FUNC(namcos1_state::bank16_w),this) } - }; - - address_space &space = (((banknum & 8) == 0) ? m_maincpu : m_subcpu)->space(AS_PROGRAM); - int bankstart = (banknum & 7) * 0x2000; - - /* for BANK handlers , memory direct and OP-code base */ - if (handler->bank_pointer) - membank(banktags[banknum])->set_base(handler->bank_pointer); - - /* read handlers */ - if (handler->bank_handler_r.isnull()) - { - if (!m_active_bank[banknum].bank_handler_r.isnull()) - space.install_read_bank(bankstart, bankstart + 0x1fff, banktags[banknum]); - } - else - { - if (m_active_bank[banknum].bank_handler_r.isnull()) - space.install_read_handler(bankstart, bankstart + 0x1fff, io_bank_handler_r[banknum].func); - } - - /* write handlers (except for the 0xe000-0xffff range) */ - if (bankstart != 0xe000) - { - if (handler->bank_handler_w.isnull()) - { - if (!m_active_bank[banknum].bank_handler_w.isnull()) - space.install_write_bank(bankstart, bankstart + 0x1fff, banktags[banknum]); - } - else - { - if (m_active_bank[banknum].bank_handler_r.isnull()) - space.install_write_handler(bankstart, bankstart + 0x1fff, io_bank_handler_w[banknum].func); - } - } - - /* Remember this bank handler */ - m_active_bank[banknum] = *handler; -} - -void namcos1_state::namcos1_bankswitch(int cpu, offs_t offset, UINT8 data) -{ - int bank = (cpu*8) + (( offset >> 9) & 0x07); - int old = m_chip[bank]; - - if (offset & 1) - { - m_chip[bank] &= 0x0300; - m_chip[bank] |= (data & 0xff); - } - else - { - m_chip[bank] &= 0x00ff; - m_chip[bank] |= (data & 0x03) << 8; - } - - /* set_bank is slow, so only call it if uninitialized(unmapped) or changed */ - if (m_active_bank[bank].bank_handler_r == read8_delegate(FUNC(namcos1_state::unknown_r),this) || m_chip[bank] != old) - set_bank(bank, &m_bank_element[m_chip[bank]]); - - /* unmapped bank warning */ - if( m_active_bank[bank].bank_handler_r == read8_delegate(FUNC(namcos1_state::unknown_r),this)) - { - logerror("%s:warning unknown chip selected bank %x=$%04x\n", machine().describe_context(), bank , m_chip[bank] ); -// if (m_chip) popmessage("%s:unknown chip selected bank %x=$%04x", cpu , machine.describe_context(), bank , m_chip[bank] ); - } -} - -WRITE8_MEMBER(namcos1_state::namcos1_bankswitch_w) -{ -// logerror("cpu %s: namcos1_bankswitch_w offset %04x data %02x\n", device().tag(), offset, data); - - namcos1_bankswitch((&space.device() == m_maincpu) ? 0 : 1, offset, data); -} - -/* Sub cpu set start bank port */ -WRITE8_MEMBER(namcos1_state::namcos1_subcpu_bank_w) -{ -// logerror("namcos1_subcpu_bank_w offset %04x data %02x\n",offset,data); - - /* Prepare code for CPU 1 */ - namcos1_bankswitch( 1, 0x0e00, 0x03 ); - namcos1_bankswitch( 1, 0x0e01, data ); + m_subcpu->set_input_line(INPUT_LINE_RESET, state); + m_audiocpu->set_input_line(INPUT_LINE_RESET, state); + m_mcu->set_input_line(INPUT_LINE_RESET, state); } /******************************************************************************* @@ -746,127 +537,16 @@ WRITE8_MEMBER(namcos1_state::namcos1_subcpu_bank_w) * * *******************************************************************************/ -void namcos1_state::namcos1_install_bank(int start, int end,read8_delegate hr, write8_delegate hw, int offset, UINT8 *pointer) -{ - for (int i = start; i <= end; i++) - { - m_bank_element[i].bank_handler_r = hr; - m_bank_element[i].bank_handler_w = hw; - m_bank_element[i].bank_offset = offset; - m_bank_element[i].bank_pointer = pointer; - - offset += 0x2000; - - if (pointer) - pointer += 0x2000; - } -} - - - -void namcos1_state::namcos1_build_banks(read8_delegate key_r, write8_delegate key_w) -{ - int i; - - /**** kludge alert ****/ - m_dummyrom = auto_alloc_array(machine(), UINT8, 0x2000); - - /* when the games want to reset because the test switch has been flipped (or - because the protection checks failed!) they just set the top bits of bank #7 - to 0, effectively crashing and waiting for the watchdog to kick in. - To avoid crashes in MAME, I prepare a dummy ROM containing just BRA -2 so - the program doesn't start executing code in unmapped areas. - Conveniently, the opcode for BRA -2 is 20 FE, and FE 20 FE is LDU $20FE, - so misaligned entry points get immediatly corrected. */ - for (i = 0;i < 0x2000;i+=2) - { - m_dummyrom[i] = 0x20; - m_dummyrom[i+1] = 0xfe; - } - /* also provide a valid IRQ vector */ - m_dummyrom[0x1ff8] = 0xff; - m_dummyrom[0x1ff9] = 0x00; - - /* clear all banks to unknown area */ - for(i = 0;i < NAMCOS1_MAX_BANK;i++) - namcos1_install_bank(i,i,read8_delegate(),write8_delegate(FUNC(namcos1_state::unknown_w),this),0,m_dummyrom); - /**** end of kludge alert ****/ - - - /* 3D glasses */ - namcos1_install_bank(0x160,0x160,read8_delegate(),write8_delegate(FUNC(namcos1_state::namcos1_3dcs_w),this),0,0); - /* RAM 6 banks - palette */ - namcos1_install_bank(0x170,0x173,read8_delegate(),write8_delegate(FUNC(namcos1_state::namcos1_paletteram_w),this),0,m_paletteram); - /* RAM 5 banks - videoram */ - namcos1_install_bank(0x178,0x17b,read8_delegate(FUNC(namcos1_state::namcos1_videoram_r),this),write8_delegate(FUNC(namcos1_state::namcos1_videoram_w),this),0,0); - /* key chip bank */ - namcos1_install_bank(0x17c,0x17c,key_r,key_w,0,0); - /* RAM 7 banks - display control, playfields, sprites */ - namcos1_install_bank(0x17e,0x17e,read8_delegate(FUNC(namcos1_state::namcos1_spriteram_r),this),write8_delegate(FUNC(namcos1_state::namcos1_spriteram_w),this),0,0); - /* RAM 1 shared ram, PSG device */ - namcos1_install_bank(0x17f,0x17f,read8_delegate(FUNC(namcos1_state::soundram_r),this),write8_delegate(FUNC(namcos1_state::soundram_w),this),0,0); - /* RAM 3 banks */ - namcos1_install_bank(0x180,0x183,read8_delegate(),write8_delegate(),0,m_s1ram); - - /* PRG0-PRG7 */ - UINT8 *rom = machine().root_device().memregion("user1")->base(); - - namcos1_install_bank(0x200,0x3ff,read8_delegate(),write8_delegate(FUNC(namcos1_state::rom_w),this),0,rom); - - /* bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected) */ - for (i = 0x380000;i < 0x400000;i++) - { - if ((i & 0x010000) == 0) - { - UINT8 t = rom[i]; - rom[i] = rom[i + 0x010000]; - rom[i + 0x010000] = t; - } - } -} - void namcos1_state::machine_reset() { - memset(m_chip, 0, sizeof(m_chip)); - - /* Point all of our bankhandlers to the error handlers */ - static const bankhandler unknown_handler = { read8_delegate(FUNC(namcos1_state::unknown_r),this), write8_delegate(FUNC(namcos1_state::unknown_w),this), 0, NULL }; - - for (int bank = 0; bank < 2*8 ; bank++) - set_bank(bank, &unknown_handler); - - /* Default MMU setup for Cpu 0 */ - namcos1_bankswitch(0, 0x0000, 0x01 ); /* bank0 = 0x180(RAM) - evidence: wldcourt */ - namcos1_bankswitch(0, 0x0001, 0x80 ); - namcos1_bankswitch(0, 0x0200, 0x01 ); /* bank1 = 0x180(RAM) - evidence: berabohm */ - namcos1_bankswitch(0, 0x0201, 0x80 ); - - namcos1_bankswitch(0, 0x0e00, 0x03 ); /* bank7 = 0x3ff(PRG7) */ - namcos1_bankswitch(0, 0x0e01, 0xff ); - - /* Default MMU setup for Cpu 1 */ - namcos1_bankswitch(1, 0x0000, 0x01 ); /* bank0 = 0x180(RAM) - evidence: wldcourt */ - namcos1_bankswitch(1, 0x0001, 0x80 ); - - namcos1_bankswitch(1, 0x0e00, 0x03); /* bank7 = 0x3ff(PRG7) */ - namcos1_bankswitch(1, 0x0e01, 0xff); - - /* reset Cpu 0 and stop all other CPUs */ - m_maincpu->reset(); - m_subcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); - m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); - m_mcu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE); - /* mcu patch data clear */ m_mcu_patch_data = 0; - m_reset = 0; namcos1_init_DACs(); memset(m_key, 0, sizeof(m_key)); m_key_quotient = 0; m_key_reminder = 0; m_key_numerator_high_word = 0; - m_wdog = 0; } @@ -903,7 +583,7 @@ WRITE8_MEMBER(namcos1_state::namcos1_mcu_bankswitch_w) /* bit 0-1 : address line A15-A16 */ addr += (data & 3) * 0x8000; - membank("bank20")->set_base(memregion("mcu")->base() + addr); + membank("mcubank")->set_base(memregion("mcu")->base() + addr); } @@ -935,42 +615,35 @@ WRITE8_MEMBER(namcos1_state::namcos1_mcu_patch_w) * driver specific initialize routine * * * *******************************************************************************/ -void namcos1_state::namcos1_driver_init(const struct namcos1_specific *specific ) +void namcos1_state::namcos1_driver_init() { - static const struct namcos1_specific no_key = + UINT8 *rom = m_rom->base(); + + // bit 16 of the address is inverted for PRG7 (and bits 17,18 just not connected) + for (int i = 0x380000;i < 0x400000;i++) { - read8_delegate(FUNC(namcos1_state::no_key_r),this), write8_delegate(FUNC(namcos1_state::no_key_w),this) - }; + if ((i & 0x010000) == 0) + { + UINT8 t = rom[i]; + rom[i] = rom[i + 0x010000]; + rom[i + 0x010000] = t; + } + } - if (!specific) specific = &no_key; + m_maincpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(namcos1_state::direct_handler_main), this)); + m_subcpu->space(AS_PROGRAM).set_direct_update_handler(direct_update_delegate(FUNC(namcos1_state::direct_handler_sub), this)); - /* keychip id */ - m_key_id = specific->key_id; - /* for key type 3 */ - m_key_reg = specific->key_reg1; - m_key_rng = specific->key_reg2; - m_key_swap4_arg = specific->key_reg3; - m_key_swap4 = specific->key_reg4; - m_key_bottom4 = specific->key_reg5; - m_key_top4 = specific->key_reg6; + // kludge! see notes + m_mcu->space(AS_PROGRAM).install_write_handler(0xc000, 0xc000, write8_delegate(FUNC(namcos1_state::namcos1_mcu_patch_w), this)); - /* S1 RAM pointer set */ - m_s1ram = auto_alloc_array_clear(machine(), UINT8, 0x8000); - m_triram = auto_alloc_array_clear(machine(), UINT8, 0x800); - m_paletteram = auto_alloc_array_clear(machine(), UINT8, 0x8000); - - /* Register volatile user memory for save state */ - save_pointer(NAME(m_s1ram), 0x8000); - save_pointer(NAME(m_triram), 0x800); - save_pointer(NAME(m_paletteram), 0x8000); - - /* Point mcu & sound shared RAM to destination */ - membank("bank18")->set_base(m_triram); - membank("bank19")->set_base(m_triram); - - /* build bank elements */ - namcos1_build_banks(specific->key_r,specific->key_w); - memset(m_active_bank, 0, sizeof(m_active_bank)); + // these are overridden as needed in the specific DRIVER_INIT_MEMBERs + m_key_id = 0; + m_key_reg = 0; + m_key_rng = 0; + m_key_swap4_arg = 0; + m_key_swap4 = 0; + m_key_bottom4 = 0; + m_key_top4 = 0; } @@ -979,7 +652,7 @@ void namcos1_state::namcos1_driver_init(const struct namcos1_specific *specific *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,shadowld) { - namcos1_driver_init(NULL); + namcos1_driver_init(); } /******************************************************************************* @@ -987,11 +660,11 @@ DRIVER_INIT_MEMBER(namcos1_state,shadowld) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,dspirit) { - static const struct namcos1_specific dspirit_specific= - { - read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x36 - }; - namcos1_driver_init(&dspirit_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type1_r),this), + write8_delegate(FUNC(namcos1_state::key_type1_w),this)); + m_key_id = 0x36; } /******************************************************************************* @@ -999,11 +672,11 @@ DRIVER_INIT_MEMBER(namcos1_state,dspirit) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,wldcourt) { - static const struct namcos1_specific worldcourt_specific= - { - read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x35 - }; - namcos1_driver_init(&worldcourt_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type1_r),this), + write8_delegate(FUNC(namcos1_state::key_type1_w),this)); + m_key_id = 0x35; } /******************************************************************************* @@ -1011,11 +684,11 @@ DRIVER_INIT_MEMBER(namcos1_state,wldcourt) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,blazer) { - static const struct namcos1_specific blazer_specific= - { - read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x13 - }; - namcos1_driver_init(&blazer_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type1_r),this), + write8_delegate(FUNC(namcos1_state::key_type1_w),this)); + m_key_id = 0x13; } /******************************************************************************* @@ -1023,11 +696,11 @@ DRIVER_INIT_MEMBER(namcos1_state,blazer) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,puzlclub) { - static const struct namcos1_specific puzlclub_specific= - { - read8_delegate(FUNC(namcos1_state::key_type1_r),this), write8_delegate(FUNC(namcos1_state::key_type1_w),this), 0x35 - }; - namcos1_driver_init(&puzlclub_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type1_r),this), + write8_delegate(FUNC(namcos1_state::key_type1_w),this)); + m_key_id = 0x35; } /******************************************************************************* @@ -1035,11 +708,11 @@ DRIVER_INIT_MEMBER(namcos1_state,puzlclub) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,pacmania) { - static const struct namcos1_specific pacmania_specific= - { - read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x12 - }; - namcos1_driver_init(&pacmania_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type2_r),this), + write8_delegate(FUNC(namcos1_state::key_type2_w),this)); + m_key_id = 0x12; } /******************************************************************************* @@ -1047,11 +720,11 @@ DRIVER_INIT_MEMBER(namcos1_state,pacmania) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,alice) { - static const struct namcos1_specific alice_specific= - { - read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x25 - }; - namcos1_driver_init(&alice_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type2_r),this), + write8_delegate(FUNC(namcos1_state::key_type2_w),this)); + m_key_id = 0x25; } /******************************************************************************* @@ -1059,11 +732,11 @@ DRIVER_INIT_MEMBER(namcos1_state,alice) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,galaga88) { - static const struct namcos1_specific galaga88_specific= - { - read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x31 - }; - namcos1_driver_init(&galaga88_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type2_r),this), + write8_delegate(FUNC(namcos1_state::key_type2_w),this)); + m_key_id = 0x31; } /******************************************************************************* @@ -1071,11 +744,11 @@ DRIVER_INIT_MEMBER(namcos1_state,galaga88) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,ws) { - static const struct namcos1_specific ws_specific= - { - read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x07 - }; - namcos1_driver_init(&ws_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type2_r),this), + write8_delegate(FUNC(namcos1_state::key_type2_w),this)); + m_key_id = 0x07; } /******************************************************************************* @@ -1083,36 +756,11 @@ DRIVER_INIT_MEMBER(namcos1_state,ws) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,bakutotu) { - static const struct namcos1_specific bakutotu_specific= - { - read8_delegate(FUNC(namcos1_state::key_type2_r),this), write8_delegate(FUNC(namcos1_state::key_type2_w),this), 0x22 - }; - namcos1_driver_init(&bakutotu_specific); - -#if 0 - // resolves CPU deadlocks caused by sloppy coding(see driver\namcos1.c) - { - static const UINT8 target[8] = {0x34,0x37,0x35,0x37,0x96,0x00,0x2e,0xed}; - UINT8 *rombase, *srcptr, *endptr, *scanptr; - - rombase = memregion("user1")->base(); - srcptr = rombase + 0x1e000; - endptr = srcptr + 0xa000; - - while ( (scanptr = memchr(srcptr, 0x34, endptr-srcptr)) ) - { - if (!memcmp(scanptr, target, 8)) - { - scanptr[7] = 0xfc; - srcptr = scanptr + 8; - - logerror ("faulty loop patched at %06x\n", scanptr-rombase+7); - } - else - srcptr = scanptr + 1; - } - } -#endif + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type2_r),this), + write8_delegate(FUNC(namcos1_state::key_type2_w),this)); + m_key_id = 0x22; } /******************************************************************************* @@ -1120,12 +768,17 @@ DRIVER_INIT_MEMBER(namcos1_state,bakutotu) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,splatter) { - static const struct namcos1_specific splatter_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 181, 3, 4,-1,-1,-1,-1 - }; - - namcos1_driver_init(&splatter_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 181; + m_key_reg = 3; + m_key_rng = 4; + m_key_swap4_arg = -1; + m_key_swap4 = -1; + m_key_bottom4 = -1; + m_key_top4 = -1; } /******************************************************************************* @@ -1133,11 +786,17 @@ DRIVER_INIT_MEMBER(namcos1_state,splatter) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,rompers) { - static const struct namcos1_specific rompers_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 182, 7,-1,-1,-1,-1,-1 - }; - namcos1_driver_init(&rompers_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 182; + m_key_reg = 7; + m_key_rng = -1; + m_key_swap4_arg = -1; + m_key_swap4 = -1; + m_key_bottom4 = -1; + m_key_top4 = -1; } /******************************************************************************* @@ -1145,11 +804,17 @@ DRIVER_INIT_MEMBER(namcos1_state,rompers) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,blastoff) { - static const struct namcos1_specific blastoff_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 183, 0, 7, 3, 5,-1,-1 - }; - namcos1_driver_init(&blastoff_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 183; + m_key_reg = 0; + m_key_rng = 7; + m_key_swap4_arg = 3; + m_key_swap4 = 5; + m_key_bottom4 = -1; + m_key_top4 = -1; } /******************************************************************************* @@ -1157,11 +822,17 @@ DRIVER_INIT_MEMBER(namcos1_state,blastoff) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,ws89) { - static const struct namcos1_specific ws89_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 184, 2,-1,-1,-1,-1,-1 - }; - namcos1_driver_init(&ws89_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 184; + m_key_reg = 2; + m_key_rng = -1; + m_key_swap4_arg = -1; + m_key_swap4 = -1; + m_key_bottom4 = -1; + m_key_top4 = -1; } /******************************************************************************* @@ -1169,28 +840,28 @@ DRIVER_INIT_MEMBER(namcos1_state,ws89) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,tankfrce) { - static const struct namcos1_specific tankfrce_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 185, 5,-1, 1,-1, 2,-1 - }; - namcos1_driver_init(&tankfrce_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 185; + m_key_reg = 5; + m_key_rng = -1; + m_key_swap4_arg = 1; + m_key_swap4 = -1; + m_key_bottom4 = 2; + m_key_top4 = -1; } - - DRIVER_INIT_MEMBER(namcos1_state,tankfrc4) { + DRIVER_INIT_CALL(tankfrce); + m_input_count = 0; m_strobe_count = 0; m_stored_input[0] = 0; m_stored_input[1] = 0; - static const struct namcos1_specific tankfrce_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 185, 5,-1, 1,-1, 2,-1 - }; - namcos1_driver_init(&tankfrce_specific); - m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::faceoff_inputs_r), this)); } @@ -1199,11 +870,17 @@ DRIVER_INIT_MEMBER(namcos1_state,tankfrc4) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,dangseed) { - static const struct namcos1_specific dangseed_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 308, 6,-1, 5,-1, 0, 4 - }; - namcos1_driver_init(&dangseed_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 308; + m_key_reg = 6; + m_key_rng = -1; + m_key_swap4_arg = 5; + m_key_swap4 = -1; + m_key_bottom4 = 0; + m_key_top4 = 4; } /******************************************************************************* @@ -1211,11 +888,17 @@ DRIVER_INIT_MEMBER(namcos1_state,dangseed) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,pistoldm) { - static const struct namcos1_specific pistoldm_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 309, 1, 2, 0,-1, 4,-1 - }; - namcos1_driver_init(&pistoldm_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 309; + m_key_reg = 1; + m_key_rng = 2; + m_key_swap4_arg = 0; + m_key_swap4 = -1; + m_key_bottom4 = 4; + m_key_top4 = -1; } /******************************************************************************* @@ -1223,11 +906,17 @@ DRIVER_INIT_MEMBER(namcos1_state,pistoldm) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,ws90) { - static const struct namcos1_specific ws90_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 310, 4,-1, 7,-1, 3,-1 - }; - namcos1_driver_init(&ws90_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 310; + m_key_reg = 4; + m_key_rng = -1; + m_key_swap4_arg = 7; + m_key_swap4 = -1; + m_key_bottom4 = 3; + m_key_top4 = -1; } /******************************************************************************* @@ -1235,11 +924,17 @@ DRIVER_INIT_MEMBER(namcos1_state,ws90) *******************************************************************************/ DRIVER_INIT_MEMBER(namcos1_state,soukobdx) { - static const struct namcos1_specific soukobdx_specific= - { - read8_delegate(FUNC(namcos1_state::key_type3_r),this), write8_delegate(FUNC(namcos1_state::key_type3_w),this), 311, 2, 3/*?*/, 0,-1, 4,-1 - }; - namcos1_driver_init(&soukobdx_specific); + namcos1_driver_init(); + m_c117->space(AS_PROGRAM).install_readwrite_handler(0x2f8000, 0x2f9fff, + read8_delegate(FUNC(namcos1_state::key_type3_r),this), + write8_delegate(FUNC(namcos1_state::key_type3_w),this)); + m_key_id = 311; + m_key_reg = 2; + m_key_rng = 3; /*?*/ + m_key_swap4_arg = 0; + m_key_swap4 = -1; + m_key_bottom4 = 4; + m_key_top4 = -1; } @@ -1280,7 +975,7 @@ READ8_MEMBER( namcos1_state::quester_paddle_r ) DRIVER_INIT_MEMBER(namcos1_state,quester) { m_strobe = 0; - namcos1_driver_init(NULL); + namcos1_driver_init(); m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::quester_paddle_r), this)); } @@ -1370,7 +1065,7 @@ DRIVER_INIT_MEMBER(namcos1_state,berabohm) m_input_count = 0; m_strobe = 0; m_strobe_count = 0; - namcos1_driver_init(NULL); + namcos1_driver_init(); m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::berabohm_buttons_r), this)); } @@ -1446,6 +1141,6 @@ DRIVER_INIT_MEMBER(namcos1_state,faceoff) m_stored_input[0] = 0; m_stored_input[1] = 0; - namcos1_driver_init(NULL); + namcos1_driver_init(); m_mcu->space(AS_PROGRAM).install_read_handler(0x1400, 0x1401, read8_delegate(FUNC(namcos1_state::faceoff_inputs_r), this)); } diff --git a/src/mame/mame.mak b/src/mame/mame.mak index d67ede0ef09..e7bc7f6ed67 100644 --- a/src/mame/mame.mak +++ b/src/mame/mame.mak @@ -1507,6 +1507,7 @@ $(MAMEOBJ)/namco.a: \ $(DRIVERS)/toypop.o $(VIDEO)/toypop.o \ $(DRIVERS)/turrett.o $(AUDIO)/turrett.o $(VIDEO)/turrett.o \ $(DRIVERS)/warpwarp.o $(AUDIO)/geebee.o $(AUDIO)/warpwarp.o $(VIDEO)/warpwarp.o \ + $(MACHINE)/c117.o \ $(MACHINE)/namcoio.o \ $(MACHINE)/namco06.o \ $(MACHINE)/namco50.o \ diff --git a/src/mame/video/namcos1.c b/src/mame/video/namcos1.c index b30ffc29db5..300c988b113 100644 --- a/src/mame/video/namcos1.c +++ b/src/mame/video/namcos1.c @@ -50,17 +50,7 @@ Namco System 1 Video Hardware ***************************************************************************/ -inline void namcos1_state::bg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram) -{ - int code; - - tile_index <<= 1; - code = info_vram[tile_index + 1] + ((info_vram[tile_index] & 0x3f) << 8); - SET_TILE_INFO_MEMBER(0,code,0,0); - tileinfo.mask_data = &m_tilemap_maskdata[code << 3]; -} - -inline void namcos1_state::fg_get_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram) +inline void namcos1_state::get_tile_info(tile_data &tileinfo,int tile_index,UINT8 *info_vram) { int code; @@ -72,32 +62,32 @@ inline void namcos1_state::fg_get_info(tile_data &tileinfo,int tile_index,UINT8 TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info0) { - bg_get_info(tileinfo,tile_index,&m_videoram[0x0000]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x0000]); } TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info1) { - bg_get_info(tileinfo,tile_index,&m_videoram[0x2000]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x2000]); } TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info2) { - bg_get_info(tileinfo,tile_index,&m_videoram[0x4000]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x4000]); } TILE_GET_INFO_MEMBER(namcos1_state::bg_get_info3) { - bg_get_info(tileinfo,tile_index,&m_videoram[0x6000]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x6000]); } TILE_GET_INFO_MEMBER(namcos1_state::fg_get_info4) { - fg_get_info(tileinfo,tile_index,&m_videoram[0x7010]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x7010]); } TILE_GET_INFO_MEMBER(namcos1_state::fg_get_info5) { - fg_get_info(tileinfo,tile_index,&m_videoram[0x7810]); + get_tile_info(tileinfo,tile_index,&m_videoram[0x7810]); } @@ -114,10 +104,6 @@ void namcos1_state::video_start() m_tilemap_maskdata = (UINT8 *)memregion("gfx1")->base(); - /* allocate videoram */ - m_videoram = auto_alloc_array_clear(machine(), UINT8, 0x8000); - m_spriteram = auto_alloc_array_clear(machine(), UINT8, 0x1000); - /* initialize playfields */ m_bg_tilemap[0] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcos1_state::bg_get_info0),this),TILEMAP_SCAN_ROWS,8,8,64,64); m_bg_tilemap[1] = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(namcos1_state::bg_get_info1),this),TILEMAP_SCAN_ROWS,8,8,64,64); @@ -140,10 +126,7 @@ void namcos1_state::video_start() m_bg_tilemap[5]->set_scrolldy(16, 16); /* register videoram to the save state system (post-allocation) */ - save_pointer(NAME(m_videoram), 0x8000); save_item(NAME(m_cus116)); - save_pointer(NAME(m_spriteram), 0x1000); - save_item(NAME(m_playfield_control)); /* set table for sprite color == 0x7f */ for (i = 0;i < 15;i++) @@ -175,11 +158,6 @@ void namcos1_state::video_start() ***************************************************************************/ -READ8_MEMBER( namcos1_state::namcos1_videoram_r ) -{ - return m_videoram[offset]; -} - WRITE8_MEMBER( namcos1_state::namcos1_videoram_w ) { m_videoram[offset] = data; @@ -235,33 +213,15 @@ WRITE8_MEMBER( namcos1_state::namcos1_paletteram_w ) - -READ8_MEMBER( namcos1_state::namcos1_spriteram_r ) -{ - /* 0000-07ff work ram */ - /* 0800-0fff sprite ram */ - if (offset < 0x1000) - return m_spriteram[offset]; - /* 1xxx playfield control ram */ - else - return m_playfield_control[offset & 0x1f]; -} - WRITE8_MEMBER( namcos1_state::namcos1_spriteram_w ) { /* 0000-07ff work ram */ /* 0800-0fff sprite ram */ - if (offset < 0x1000) - { - m_spriteram[offset] = data; + m_spriteram[offset] = data; - /* a write to this offset tells the sprite chip to buffer the sprite list */ - if (offset == 0x0ff2) - m_copy_sprites = 1; - } - /* 1xxx playfield control ram */ - else - m_playfield_control[offset & 0x1f] = data; + /* a write to this offset tells the sprite chip to buffer the sprite list */ + if (offset == 0x0ff2) + m_copy_sprites = 1; }