mirror of
https://github.com/holub/mame
synced 2025-04-16 05:24:54 +03:00
Minor changes to various drivers (#8880)
* Minor changes to various drivers (todo, comments, text strings). * ec1847: Moved to pc.cpp, it's a generic OEM clone. * Use proper name for serial/parallel ports card in ec1840 and ec1841. * superga2: Moved to arcade section, updated emulation status.
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@ -5133,6 +5133,7 @@ files {
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MAME_DIR .. "src/mame/drivers/summit.cpp",
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MAME_DIR .. "src/mame/drivers/sumt8035.cpp",
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MAME_DIR .. "src/mame/drivers/supercrd.cpp",
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MAME_DIR .. "src/mame/drivers/superga2.cpp",
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MAME_DIR .. "src/mame/drivers/supertnk.cpp",
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MAME_DIR .. "src/mame/drivers/tapatune.cpp",
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MAME_DIR .. "src/mame/drivers/tattack.cpp",
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@ -1850,7 +1850,6 @@ files {
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MAME_DIR .. "src/mame/machine/macscsi.cpp",
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MAME_DIR .. "src/mame/machine/macscsi.h",
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MAME_DIR .. "src/mame/drivers/iphone2g.cpp",
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MAME_DIR .. "src/mame/drivers/superga2.cpp",
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}
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createMESSProjects(_target, _subtarget, "applied")
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@ -59,7 +59,7 @@
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#define HPHIL_DHR 0xFE // Device Hard Reset
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/*
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* init sequnce (p. 4-13)
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* init sequence (p. 4-13)
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*
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* DHR
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* IFC
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@ -1345,7 +1345,7 @@ void isa8_ega_device::pc_ega8_3c0_w(offs_t offset, uint8_t data)
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m_attribute.index_write ^= 0x01;
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break;
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/* Misccellaneous Output */
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/* Miscellaneous Output */
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case 2:
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m_misc_output = data;
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install_banks();
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@ -4,6 +4,9 @@
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* Gravis Ultrasound ISA card
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*
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* Started: 28/01/2012
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*
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* to do: xref with lowsrc.doc from GUS SDK
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* - 256K DMA and 16-bit sample playback boundaries
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*/
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@ -720,7 +723,7 @@ void gf1_device::global_reg_data_w(offs_t offset, uint8_t data)
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* bit 2 - roll over condition (generate IRQ, and not stop playing voice, no looping)
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* bit 3 - enable looping
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* bit 4 - enable bi-directional looping
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* bit 5 - rnable IRQ at end of ramp */
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* bit 5 - enable IRQ at end of ramp */
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if(offset == 1)
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{
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m_voice[m_current_voice].vol_ramp_ctrl = data & 0x7f;
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@ -16,7 +16,7 @@
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http://www.seasip.info/VintagePC/pgc.html
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To do:
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- pass IBM diagnostics (currently fail with code 3905)
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- pass IBM diagnostics (currently fail with code 3905 - 'Cold start cycle power error')
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- CGA emulator
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- what's up with irq 3 (= vblank irq)? (causes soft reset)
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- "test pin of the microprocessor samples the hsync pulse"
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@ -65,13 +65,11 @@ void ec184x_isa8_cards(device_slot_interface &device)
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{
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device.option_add("ec1840.0002", ISA8_EC1840_0002); // MDA with downloadable font
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device.option_add("ec1840.0003", ISA8_FDC_XT);
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device.option_add("ec1840.0004", ISA8_LPT);
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device.option_add("ec1841.0002", ISA8_EC1841_0002); // CGA with downloadable font
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device.option_add("ec1841.0003", ISA8_EC1841_0003); // FDC + mouse port
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device.option_add("ec1841.0004", ISA8_LPT);
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/*
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device.option_add("ec1841.0004", ISA8_EC1841_0004); // BSC-like serial ports + parallel port
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device.option_add("ec1841.0010", ISA8_EC1841_0010); // 8089-based HDC
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*/
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// device.option_add("ec1840.0004", ISA8_EC1840_0004); // BSC-like serial ports + parallel port
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// device.option_add("ec1841.0010", ISA8_EC1841_0010); // 8089-based HDC
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device.option_add("mda", ISA8_MDA);
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device.option_add("hdc", ISA8_HDC_EC1841);
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device.option_add("pccom", ISA8_COM);
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@ -17,8 +17,8 @@
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CMOS 26C562 68C562
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----------------------------------
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For more info see:
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page 511: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1986_Signetics_Microprocessor.pdf
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page 514: http://bitsavers.informatik.uni-stuttgart.de/pdf/signetics/_dataBooks/1994_Signetics_Data_Communications.pdf
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page 511: http://bitsavers.informatik.uni-stuttgart.de/components/signetics/_dataBooks/1986_Signetics_Microprocessor.pdf
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page 514: http://bitsavers.informatik.uni-stuttgart.de/components/signetics/_dataBooks/1994_Signetics_Data_Communications.pdf
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Designs known of including one or more DUSCCs
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------------------------------------------------
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@ -268,9 +268,9 @@ void duscc_device::device_reset()
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into three bits which are inserted into bits [2:0] or [4:2] of the interrupt vector register. This forms the content of the IVRM during
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an interrupt acknowledge cycle. Unmodified and modified vectors can read directly through specified registers. Two of the conditions
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are the inclusive OR of several other maskable conditions:
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- Extemal or CIT special condition: Delta DCD, Delta CTS or CIT zero count (ICTSR[6:4j).
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- Rxrrx error or special condition: any condition in the Receiver Status Register (RSR[7:0J) or a transmitter or DPLL condition in
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the Transmitter and Receiver Status Register (TRSR[7:3J).
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- External or CIT special condition: Delta DCD, Delta CTS or CIT zero count (ICTSR[6:4]).
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- Rxrrx error or special condition: any condition in the Receiver Status Register (RSR[7:0]) or a transmitter or DPLL condition in
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the Transmitter and Receiver Status Register (TRSR[7:3]).
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The TxRDY and RxRDY conditions are defined by OMR[4] and OMR[3], respectively. Also associated with the interrupt system are
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the Interrupt Enable Register (IER), one bit in the Countermmer Control Register (CTCR), and the Interrupt Control Register (lCR).
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@ -465,9 +465,9 @@ uint8_t duscc_device::modify_vector(uint8_t vec, int index, uint8_t src)
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1. Interrupt Enable Register (IERA/B). - checked by trigger_interrupt
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2. Receiver Status Register (RSRA/B).
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3. Transmitter and Receiver Status Register (TRSRA/B).
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4. Input and Counter/timer Status Register (ICTSRA/B).
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5. interrupt Vector Register (IVR) and Modified Interrupt Vector Register (IVRM).
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6. Interrupt control register (lCR).
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4. Input and Counter/Timer Status Register (ICTSRA/B).
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5. Interrupt Vector Register (IVR) and Modified Interrupt Vector Register (IVRM).
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6. Interrupt control register (ICR).
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7. General status register (GSR)
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*/
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@ -483,7 +483,7 @@ void duscc_device::trigger_interrupt(int index, int state)
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LOGINT("%s %s:%c %02x \n",FUNCNAME, tag(), 'A' + index, state);
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/* The Interrup Controll Register (ICR) bits, must be set for the correspondning channel */
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/* The Interrupt Control Register (ICR) bits, must be set for the correspondning channel */
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// ICR Check is probably by the caller but we check again to be sure
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if ((m_icr & (index == CHANNEL_A ? REG_ICR_CHA : REG_ICR_CHB)) == 0)
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{
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@ -814,21 +814,24 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
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}
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/* The DUSCC 16 bit Timer
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Counter/Timer Control and Value Registers
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There are five registers in this set consisting of the following:
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1. Counterltimer control register (CTCRAlB).
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2. Counterltimer preset Highland Low registers (CTPRHAlB, CTPRLAlB).
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3. Counter/bmer (current value) High and Low registers (CTHAlB, CTLAlB)
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The control register contains the operational information for the counterltimer. The preset registers contain the count which is
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loaded into the counterltimer circuits. The third group contains the current value of the counterltimer as it operates.
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*/
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/* Counter/Timer Control Register (CTCRA/CTCRB)
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1. Counter/Timer control register (CTCRA/B).
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2. Counter/Timer preset Highland Low registers (CTPRHA/B, CTPRLA/B).
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3. Counter/Timer (current value) High and Low registers (CTHA/B, CTLA/B)
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The control register contains the operational information for the counter/timer. The preset registers contain the count which is
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loaded into the counter/timer circuits. The third group contains the current value of the counterltimer as it operates.
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Counter/Timer Control Register (CTCRA/CTCRB)
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[7] Zero Detect Interrupt - This bit determines whether the assertion of the CIT ZERO COUNT status bit (ICTSR[6)) causes an
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interrupt to be generated if set to 1 and the Master interrupt control bit (ICR[0:1]) is set
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[6] Zero Detect Control - his bit determines the action of the counter upon reaching zero count
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0 - The counter/timer is preset to the value contained in the counterltimer preset registers (CTPRL, CTPRH) at the next clock edge.
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1 - The counterltimer continues counting without preset. The value at the next clock edge will be H'FFFF'.
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[5] CounterlTimer Output Control - This bit selects the output waveform when the counterltimer is selected to be output on TRxC or RTxC.
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0 - The counter/timer is preset to the value contained in the counter/timer preset registers (CTPRL, CTPRH) at the next clock edge.
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1 - The counter/timer continues counting without preset. The value at the next clock edge will be H'FFFF'.
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[5] Counter/Timer Output Control - This bit selects the output waveform when the counter/timer is selected to be output on TRxC or RTxC.
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0 - The output toggles each time the CIT reaches zero count. The output is cleared to Low by either of the preset counterltimer commands.
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1 - The output is a single clock positive width pulse each time the CIT reaches zero count. (The duration of this pulse is one clock period.)
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[4:3] Clock Select - This field selects whether the clock selected by [2:0J is prescaled prior to being applied to the input of the CIT.
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@ -844,8 +847,8 @@ void duscc_channel::device_timer(emu_timer &timer, device_timer_id id, int param
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start of counting until the RxD input goes Low. It continues counting until the RxD input goes High, then stops and sets
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the CIT zero count status bit. The CPU can use the value in the CIT to determine the bit rate of the incoming data.
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The clock is the crystal oscillator or system clock input divided by four.
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100 Source is the 32X BRG output selected by RTR[3:0J of own channel.
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101 Source is the 32X BRG output selected by TTR[3:0J of own channel.
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100 Source is the 32X BRG output selected by RTR[3:0] of own channel.
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101 Source is the 32X BRG output selected by TTR[3:0] of own channel.
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110 Source is the internal signal which loads received characters from the receive shift register into the receiver
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FIFO. When operating in this mode, the FIFOed EOM status bit (RSR[7)) shall be set when the character which
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causes the count to go to zero is loaded into the receive FIFO.
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@ -1818,7 +1821,7 @@ void duscc_channel::do_dusccreg_rtr_w(uint8_t data)
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to the transmit shift register. If not reset by the CPU, TxRDY remains asserted until the FIFO is full, at which time
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it is automatically negated.
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1 FIFO empty. The channel's TxRDY status bit is asserted when a character transfer from the transmit FIFO to the
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transmit shift register causes the FI FO to become empty. If not reset by the CPU, TxRDY remains asserted until the
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transmit shift register causes the FIFO to become empty. If not reset by the CPU, TxRDY remains asserted until the
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FIFO is full, at which time it is negated.
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If the TxRDY status bit is reset by the CPU, it will remain negated regardless of the current state of the transmit
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FIFO, until it is asserted again due to the occurrence of one of the above conditions.
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@ -2082,9 +2085,9 @@ void duscc_channel::do_dusccreg_txfifo_w(uint8_t data)
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}
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/* Receiver Status Register (RSRA, RSRB)
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This register informs the CPU of receiver status. Bits indicated as 'not used';n a particular mode will read as zero. The logical OR of
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This register informs the CPU of receiver status. Bits indicated as 'not used' in a particular mode will read as zero. The logical OR of
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these bits is presented in GSR[2] or GSR[6] (ORed with the bits of TRSR) for Channels A and B, respectively. Unless otherwise
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indicated, asserted status bits are reset only be performing a write operation to the status register with the bits to be reset being ones in
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indicated, asserted status bits are reset only by performing a write operation to the status register with the bits to be reset being ones in
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the accompanying data word, or when the RESETN input is asserted, or when a 'reset receiver' command is issued.
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Certain status bits are specified as being FIFOed. This means that they occupy positions in a status FIFO that correspond to the data
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FIFO. As the data is brought to the top of the FIFO (the position read when the RxFIFO is read), the FIFOed status bits are logically
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@ -2116,15 +2119,15 @@ void duscc_channel::do_dusccreg_ictsr_w(uint8_t data)
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/* The GSR register provides a 'quick look' at the overall status of both channels of the DUSCC. A write to this register with ls at the
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corresponding bit pOSitions causes TxRDY (bits 5 and 1) and/or RxRDY (bits 4 and 0) to be reset. The other status bits can be reset
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only by resetting the individual status bits that they point to.
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[7] Channel 8 External or Coutnerrrimer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
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[7] Channel 8 External or Counter/Timer Status - This bit indicates that one of the following status bits is asserted: ICTSRB[6:4].
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[6] Channel B Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRB[7:0], TRSRB[7:3].
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[5] Channel 8 Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel B
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transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4j. This bit can be asserted only
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when the transmitter is enabled. Reselling the transmitter negates TxRDY.
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[4] Channel 8 Receiver Ready - The assertion of this bit indicates that one or more characters are available in the Channel B receiver
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FIFO to be read by the CPU. See deSCription of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
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FIFO to be read by the CPU. See description of OMR[3]. RxRDY is initially reset (negated) by a chip reset or when a 'reset Channel B
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receiver' command is invoked.
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[3] Channel A External or Countermmer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
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[3] Channel A External or Counter/Timer Status - This bit indicates that one of the following status bits is asserted: ICTSRA[6:4].
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[2] Channel A Receiver or Transmitter Status - This bit indicates that one of the following status bits is asserted: RSRA(7:0], TRSRA(7:3].
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[1) Channel A Transmitter Ready - The assertion of this bit indicates that one or more characters may be loaded into the Channel A
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transmitter FIFO to be serialized by the transmit shift register. See description of OMR[4]. This bit can be asserted only
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@ -44,9 +44,8 @@ public:
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, m_ram(*this, RAM_TAG)
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{ }
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void ec1841(machine_config &config);
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void ec1847(machine_config &config);
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void ec1840(machine_config &config);
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void ec1841(machine_config &config);
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void init_ec1840();
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void init_ec1841();
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@ -60,8 +59,6 @@ private:
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void ec1840_map(address_map &map);
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void ec1841_io(address_map &map);
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void ec1841_map(address_map &map);
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void ec1847_io(address_map &map);
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void ec1847_map(address_map &map);
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required_device<cpu_device> m_maincpu;
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required_device<ram_device> m_ram;
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@ -197,12 +194,6 @@ void ec184x_state::ec1841_map(address_map &map)
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map(0xf0000, 0xfffff).rom().region("bios", 0);
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}
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void ec184x_state::ec1847_map(address_map &map)
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{
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map.unmap_value_high();
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map(0xe0000, 0xfffff).rom().region("bios", 0);
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}
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void ec184x_state::ec1840_io(address_map &map)
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{
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map.unmap_value_high();
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@ -216,13 +207,6 @@ void ec184x_state::ec1841_io(address_map &map)
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map(0x02b0, 0x02b3).rw(FUNC(ec184x_state::memboard_r), FUNC(ec184x_state::memboard_w));
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}
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void ec184x_state::ec1847_io(address_map &map)
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{
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map.unmap_value_high();
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map(0x0000, 0x00ff).m("mb", FUNC(ibm5160_mb_device::map));
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// map(0x0210, 0x021f).ram(); // internal (non-standard?) bus extender
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}
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// XXX verify everything
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void ec184x_state::ec1840(machine_config &config)
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@ -240,12 +224,12 @@ void ec184x_state::ec1840(machine_config &config)
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mb.kbddata_callback().set("kbd", FUNC(pc_kbdc_device::data_write_from_mb));
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// FIXME: determine ISA bus clock
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// 7-slot backplane, at least two slots are always taken by CPU and memory cards
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ISA8_SLOT(config, "isa1", 0, "mb:isa", ec184x_isa8_cards, "ec1840.0002", false);
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ISA8_SLOT(config, "isa2", 0, "mb:isa", ec184x_isa8_cards, "ec1840.0003", false);
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ISA8_SLOT(config, "isa3", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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ISA8_SLOT(config, "isa3", 0, "mb:isa", ec184x_isa8_cards, "ec1840.0004", false);
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ISA8_SLOT(config, "isa4", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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ISA8_SLOT(config, "isa5", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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ISA8_SLOT(config, "isa6", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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SOFTWARE_LIST(config, "flop_list").set_original("ec1841");
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@ -275,7 +259,7 @@ void ec184x_state::ec1841(machine_config &config)
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// FIXME: determine ISA bus clock
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ISA8_SLOT(config, "isa1", 0, "mb:isa", ec184x_isa8_cards, "ec1841.0002", false); // cga
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ISA8_SLOT(config, "isa2", 0, "mb:isa", ec184x_isa8_cards, "ec1841.0003", false); // fdc (IRQ6) + mouse port (IRQ2..5)
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ISA8_SLOT(config, "isa3", 0, "mb:isa", ec184x_isa8_cards, "ec1841.0004", false); // lpt (IRQ7||5) [+ serial (IRQx)]
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ISA8_SLOT(config, "isa3", 0, "mb:isa", ec184x_isa8_cards, "ec1840.0004", false); // lpt (IRQ7||5) [+ serial (IRQx)]
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ISA8_SLOT(config, "isa4", 0, "mb:isa", ec184x_isa8_cards, "hdc", false);
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ISA8_SLOT(config, "isa5", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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ISA8_SLOT(config, "isa6", 0, "mb:isa", ec184x_isa8_cards, nullptr, false);
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@ -289,36 +273,6 @@ void ec184x_state::ec1841(machine_config &config)
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RAM(config, m_ram).set_default_size("640K").set_extra_options("512K,1024K,1576K,2048K");
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}
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// XXX verify everything
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void ec184x_state::ec1847(machine_config &config)
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{
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I8086(config, m_maincpu, 4772720);
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m_maincpu->set_addrmap(AS_PROGRAM, &ec184x_state::ec1847_map);
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m_maincpu->set_addrmap(AS_IO, &ec184x_state::ec1847_io);
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m_maincpu->set_irq_acknowledge_callback("mb:pic8259", FUNC(pic8259_device::inta_cb));
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ibm5160_mb_device &mb(IBM5160_MOTHERBOARD(config, "mb"));
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mb.set_cputag(m_maincpu);
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mb.int_callback().set_inputline(m_maincpu, 0);
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mb.nmi_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
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mb.kbdclk_callback().set("kbd", FUNC(pc_kbdc_device::clock_write_from_mb));
|
||||
mb.kbddata_callback().set("kbd", FUNC(pc_kbdc_device::data_write_from_mb));
|
||||
|
||||
// FIXME: determine ISA bus clock
|
||||
ISA8_SLOT(config, "isa1", 0, "mb:isa", pc_isa8_cards, "hercules", false); // cga, ega and vga(?) are options too
|
||||
ISA8_SLOT(config, "isa2", 0, "mb:isa", pc_isa8_cards, "fdc_xt", false);
|
||||
ISA8_SLOT(config, "isa3", 0, "mb:isa", pc_isa8_cards, nullptr, false); // native variant (wd1010 + z80) not emulated
|
||||
ISA8_SLOT(config, "isa4", 0, "mb:isa", pc_isa8_cards, nullptr, false); // native serial (2x8251) not emulated
|
||||
ISA8_SLOT(config, "isa5", 0, "mb:isa", pc_isa8_cards, nullptr, false);
|
||||
ISA8_SLOT(config, "isa6", 0, "mb:isa", pc_isa8_cards, nullptr, false);
|
||||
|
||||
pc_kbdc_device &kbd(PC_KBDC(config, "kbd", pc_xt_keyboards, STR_KBD_KEYTRONIC_PC3270));
|
||||
kbd.out_clock_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_clock_w));
|
||||
kbd.out_data_cb().set("mb", FUNC(ibm5160_mb_device::keyboard_data_w));
|
||||
|
||||
RAM(config, m_ram).set_default_size("640K");
|
||||
}
|
||||
|
||||
ROM_START( ec1840 )
|
||||
ROM_REGION16_LE(0x10000,"bios", 0)
|
||||
ROM_DEFAULT_BIOS("v4")
|
||||
@ -384,19 +338,7 @@ ROM_START( ec1845 )
|
||||
ROMX_LOAD("184507.bin", 0xf001, 0x0800, CRC(75122203) SHA1(7b0fbdf1315230633e39574ac7360163bc7361e1), ROM_SKIP(1))
|
||||
ROM_END
|
||||
|
||||
ROM_START( ec1847 )
|
||||
ROM_REGION16_LE(0x20000,"bios", 0)
|
||||
ROM_SYSTEM_BIOS(0, "vxxx", "EC-1847.0x")
|
||||
ROMX_LOAD("308_d47_2764.bin", 0x08000, 0x2000, CRC(f06924f2) SHA1(83a5dedf1c06f875c598f087bbc087524bc9bfa3), ROM_BIOS(0))
|
||||
ROMX_LOAD("188m_d47_2764.bin", 0x14000, 0x2000, CRC(bc8742c7) SHA1(3af09d14e891e976b7a9a2a6e1af63f0eabe5426), ROM_BIOS(0))
|
||||
ROMX_LOAD("188m_d48_2764.bin", 0x1e000, 0x2000, CRC(7d290e95) SHA1(e73e6c8e19477fce5de3f95b89693dc6ad6781ab), ROM_BIOS(0))
|
||||
|
||||
ROM_REGION(0x2000,"gfx1", ROMREGION_ERASE00)
|
||||
ROM_LOAD("317_d28_2732.bin", 0x00000, 0x1000, CRC(8939599b) SHA1(53d02460cf93596882a96758ef4bac5fa1ce55b2)) // monochrome font
|
||||
ROM_END
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1986, ec1840, ibm5150, 0, ec1840, 0, ec184x_state, init_ec1840, "<unknown>", "EC-1840", 0 )
|
||||
COMP( 1987, ec1841, ibm5150, 0, ec1841, 0, ec184x_state, init_ec1841, "<unknown>", "EC-1841", 0 )
|
||||
COMP( 1989, ec1845, ibm5150, 0, ec1841, 0, ec184x_state, init_ec1841, "<unknown>", "EC-1845", MACHINE_NOT_WORKING )
|
||||
COMP( 1990, ec1847, ibm5150, 0, ec1847, 0, ec184x_state, empty_init, "<unknown>", "EC-1847", MACHINE_NOT_WORKING )
|
||||
|
||||
@ -75,6 +75,7 @@ public:
|
||||
void earthst(machine_config &config);
|
||||
void vpcii(machine_config &config);
|
||||
void fraking(machine_config &config);
|
||||
void ec1847(machine_config &config);
|
||||
|
||||
void init_bondwell();
|
||||
|
||||
@ -1738,6 +1739,26 @@ ROM_START( nms9100 )
|
||||
ROMX_LOAD("philipsxt.bin", 0x8000, 0x8000, CRC(2f3135e7) SHA1(d2fc4c06cf09e2c5a62017f0977b084be8bf9bbd), ROM_BIOS(2))
|
||||
ROM_END
|
||||
|
||||
/**************************************************************** EC-1847 ***
|
||||
Desktop?
|
||||
*****************************************************************************/
|
||||
|
||||
void pc_state::ec1847(machine_config &config)
|
||||
{
|
||||
pccga(config);
|
||||
// subdevice<isa8_slot_device>("isa1")->set_default_option("hercules");
|
||||
}
|
||||
|
||||
ROM_START( ec1847 )
|
||||
ROM_REGION(0x10000, "bios", 0)
|
||||
ROM_LOAD("308_d47_2764.bin", 0x8000, 0x2000, CRC(f06924f2) SHA1(83a5dedf1c06f875c598f087bbc087524bc9bfa3)) // hdc
|
||||
ROM_LOAD("188m_d47_2764.bin", 0x4000, 0x2000, CRC(bc8742c7) SHA1(3af09d14e891e976b7a9a2a6e1af63f0eabe5426))
|
||||
ROM_LOAD("188m_d48_2764.bin", 0xe000, 0x2000, CRC(7d290e95) SHA1(e73e6c8e19477fce5de3f95b89693dc6ad6781ab))
|
||||
|
||||
ROM_REGION(0x2000, "gfx1", ROMREGION_ERASE00)
|
||||
ROM_LOAD("317_d28_2732.bin", 0x00000, 0x1000, CRC(8939599b) SHA1(53d02460cf93596882a96758ef4bac5fa1ce55b2)) // monochrome font
|
||||
ROM_END
|
||||
|
||||
/************************************************* AEG Olympia Olystar 20F ***
|
||||
Form Factor: Desktop
|
||||
uses an Acer 710IIN motherboard, BIOS-Version 4.06
|
||||
@ -2317,6 +2338,7 @@ COMP( 198?, dtkerso, ibm5150, 0, pccga, pccga, pc_state,
|
||||
COMP( 1983, eagle1600, ibm5150, 0, eagle1600, pccga, pc_state, empty_init, "Eagle", "Eagle 1600" , MACHINE_NOT_WORKING )
|
||||
COMP( 1983, eaglespirit, ibm5150, 0, pccga, pccga, pc_state, empty_init, "Eagle", "Eagle PC Spirit", MACHINE_NOT_WORKING )
|
||||
COMP( 198?, eaglepc2, ibm5150, 0, pccga, pccga, pc_state, empty_init, "Eagle", "PC-2", MACHINE_NOT_WORKING )
|
||||
COMP( 1990, ec1847, ibm5150, 0, ec1847, pccga, pc_state, empty_init, "<unknown>", "EC-1847", MACHINE_NOT_WORKING )
|
||||
COMP( 1985, eppc, ibm5150, 0, pccga, pccga, pc_state, empty_init, "Ericsson Information System", "Ericsson Portable PC", MACHINE_NOT_WORKING )
|
||||
COMP( 1989, fraking, ibm5150, 0, modernxt, pccga, pc_state, empty_init, "Frael", "King", MACHINE_NOT_WORKING )
|
||||
COMP( 198?, hyo88t, ibm5150, 0, pccga, pccga, pc_state, empty_init, "Hyosung", "Topstar 88T", MACHINE_NOT_WORKING )
|
||||
|
||||
@ -6,60 +6,60 @@
|
||||
|
||||
Unibus models
|
||||
==================
|
||||
PDP-11/20 and PDP-11/15 ? The original, non-microprogrammed processor;
|
||||
PDP-11/20 and PDP-11/15 - The original, non-microprogrammed processor;
|
||||
designed by Jim O'Loughlin. Floating point was supported by
|
||||
peripheral options using various data formats.
|
||||
PDP-11/35 and PDP-11/40 ? A microprogrammed successor to the PDP-11/20;
|
||||
PDP-11/35 and PDP-11/40 - A microprogrammed successor to the PDP-11/20;
|
||||
the design team was led by Jim O'Loughlin.
|
||||
PDP-11/45, PDP-11/50, and PDP-11/55 ? A much faster microprogrammed processor
|
||||
that could use up to 256 kB of semiconductor memory instead of or in
|
||||
addition to core memory. First model to support an optional FP11
|
||||
floating-point coprocessor, which established the format used in
|
||||
later models.
|
||||
PDP-11/70 ? The 11/45 architecture expanded to allow 4 MB of physical memory
|
||||
PDP-11/70 - The 11/45 architecture expanded to allow 4 MB of physical memory
|
||||
segregated onto a private memory bus, 2 kB of cache memory, and much
|
||||
faster I/O devices connected via the Massbus.[9]
|
||||
PDP-11/05 and PDP-11/10 ? A cost-reduced successor to the PDP-11/20.
|
||||
PDP-11/34 and PDP-11/04 ? Cost-reduced follow-on products to the 11/35
|
||||
PDP-11/05 and PDP-11/10 - A cost-reduced successor to the PDP-11/20.
|
||||
PDP-11/34 and PDP-11/04 - Cost-reduced follow-on products to the 11/35
|
||||
and 11/05; the PDP-11/34 concept was created by Bob Armstrong.
|
||||
The 11/34 supported up to 256 kB of Unibus memory. The PDP-11/34a
|
||||
supported a fast floating-point option, and the 11/34c supported a
|
||||
cache memory option.
|
||||
PDP-11/60 ? A PDP-11 with user-writable microcontrol store; this was
|
||||
PDP-11/60 - A PDP-11 with user-writable microcontrol store; this was
|
||||
designed by another team led by Jim O'Loughlin.
|
||||
PDP-11/44 ? Replacement for the 11/45 and 11/70 that supported optional cache
|
||||
PDP-11/44 - Replacement for the 11/45 and 11/70 that supported optional cache
|
||||
memory and floating-point processor, and included a sophisticated serial
|
||||
console interface and support for 4 MB of physical memory. The design
|
||||
team was managed by John Sofio.
|
||||
PDP-11/24 ? First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set
|
||||
PDP-11/24 - First VLSI PDP-11 for Unibus, using the "Fonz-11" (F11) chip set
|
||||
with a Unibus adapter.
|
||||
PDP-11/84 ? Using the VLSI "Jaws-11" (J11) chip set with a Unibus adapter.
|
||||
PDP-11/94 ? J11-based, faster than 11/84.
|
||||
PDP-11/84 - Using the VLSI "Jaws-11" (J11) chip set with a Unibus adapter.
|
||||
PDP-11/94 - J11-based, faster than 11/84.
|
||||
|
||||
Q-bus models
|
||||
==============
|
||||
PDP-11/03 (also known as the LSI-11/03) ? The first LSI PDP-11, this system
|
||||
PDP-11/03 (also known as the LSI-11/03) - The first LSI PDP-11, this system
|
||||
used a chipset from Western Digital and supported 60 kB of memory.
|
||||
PDP-11/23 ? Second generation of LSI (F-11). Early units supported
|
||||
PDP-11/23 - Second generation of LSI (F-11). Early units supported
|
||||
only 248 kB of memory.
|
||||
PDP-11/23+/MicroPDP-11/23 ? Improved 11/23 with more functions on the
|
||||
PDP-11/23+/MicroPDP-11/23 - Improved 11/23 with more functions on the
|
||||
(larger) processor card.
|
||||
MicroPDP-11/73 ? The third generation LSI-11, this system used the
|
||||
MicroPDP-11/73 - The third generation LSI-11, this system used the
|
||||
faster "Jaws-11" (J-11) chip set and supported up to 4 MB of memory.
|
||||
MicroPDP-11/53 ? Slower 11/73 with on-board memory.
|
||||
MicroPDP-11/83 ? Faster 11/73 with PMI (private memory interconnect).
|
||||
MicroPDP-11/93 ? Faster 11/83; final DEC Q-Bus PDP-11 model.
|
||||
MicroPDP-11/53 - Slower 11/73 with on-board memory.
|
||||
MicroPDP-11/83 - Faster 11/73 with PMI (private memory interconnect).
|
||||
MicroPDP-11/93 - Faster 11/83; final DEC Q-Bus PDP-11 model.
|
||||
KXJ11 - QBUS card (M7616) with PDP-11 based peripheral processor and
|
||||
DMA controller. Based on a J11 CPU equipped with 512 kB of RAM,
|
||||
64 kB of ROM, and parallel and serial interfaces.
|
||||
Mentec M100 ? Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz,
|
||||
Mentec M100 - Mentec redesign of the 11/93, with J-11 chipset at 19.66 MHz,
|
||||
four on-board serial ports, 1-4 MB of on-board memory, and optional FPU.
|
||||
Mentec M11 ? Processor upgrade board; microcode implementation of PDP-11
|
||||
Mentec M11 - Processor upgrade board; microcode implementation of PDP-11
|
||||
instruction set by Mentec, using the TI 8832 ALU and TI 8818
|
||||
microsequencer from Texas Instruments.
|
||||
Mentec M1 ? Processor upgrade board; microcode implementation of
|
||||
Mentec M1 - Processor upgrade board; microcode implementation of
|
||||
PDP-11 instruction set by Mentec, using Atmel 0.35 ?m ASIC.[10]
|
||||
Quickware QED-993 ? High performance PDP-11/93 processor upgrade board.
|
||||
Quickware QED-993 - High performance PDP-11/93 processor upgrade board.
|
||||
DECserver 500 and 550 LAT terminal servers DSRVS-BA using the KDJ11-SB chipset
|
||||
|
||||
All PDP-11's execept the first one (11/15 and 11/20) are microprogrammed.
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
to do:
|
||||
- cassette i/o and softlist
|
||||
- verify palette
|
||||
- use palette rom
|
||||
- monochrome output
|
||||
- trap: does memory always get written or it's up to NMI ISR to complete writes?
|
||||
- keyboard layout for earliest revision (v89r0)
|
||||
|
||||
@ -9,8 +9,6 @@
|
||||
Notes:
|
||||
- keyboard connected to sio channel a
|
||||
- sio channel a clock output connected to ctc trigger 0
|
||||
- memory map not 100% clear
|
||||
- rt1715w: SCP3 boot loops while executing PROFILE.SUB
|
||||
|
||||
Docs:
|
||||
- http://www.robotrontechnik.de/html/computer/pc1715w.htm
|
||||
|
||||
@ -11,8 +11,9 @@
|
||||
|
||||
Info: http://agatcomp.ru/Pravetz/SuperGames.shtml
|
||||
|
||||
To do
|
||||
To do:
|
||||
- verify palette, pixel and cpu clocks
|
||||
- proper bootstrap (is there another ROM?)
|
||||
|
||||
************************************************************************/
|
||||
|
||||
@ -49,7 +50,7 @@ public:
|
||||
m_softlatch(*this, "softlatch")
|
||||
{ }
|
||||
|
||||
static constexpr feature_type imperfect_features() { return feature::PALETTE | feature::CONTROLS; }
|
||||
static constexpr feature_type imperfect_features() { return feature::PALETTE; }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<screen_device> m_screen;
|
||||
|
||||
@ -26,7 +26,8 @@
|
||||
- backup ram (stores config.sys)
|
||||
- HardRAM (static RAM board)
|
||||
- native keyboard (MCU dump missing)
|
||||
- font selector (CRTC register 0x12; DIP switches PJ20, PJ21)
|
||||
- font selector (system register 0x5A; DIP switches PJ20, PJ21)
|
||||
- display contrast and type (CRTC register 0x12)
|
||||
|
||||
Useful links:
|
||||
- board photo: http://s8.hostingkartinok.com/uploads/images/2016/05/579e9d152bc772d9c16bc8ac611eb97f.jpg
|
||||
|
||||
@ -12770,7 +12770,6 @@ easykara
|
||||
ec1840 //
|
||||
ec1841 //
|
||||
ec1845 //
|
||||
ec1847 //
|
||||
|
||||
@source:ec65.cpp
|
||||
ec65 //
|
||||
@ -33816,6 +33815,7 @@ comport // Compaq Portable
|
||||
coppc21 // Corona PPC-21 portable
|
||||
coppc400 // Cordata PPC-400 portable
|
||||
dgone // 1984 Data General/One
|
||||
ec1847 //
|
||||
eagle1600 //
|
||||
dtkerso // 198? PC-XT clones with a DTK/ERSO BIOS
|
||||
eaglespirit // Eagle PC Spirit
|
||||
|
||||
@ -1012,7 +1012,6 @@ sun3x.cpp
|
||||
sun4.cpp
|
||||
super6.cpp
|
||||
super80.cpp
|
||||
superga2.cpp
|
||||
superslave.cpp
|
||||
supracan.cpp
|
||||
sv8000.cpp
|
||||
|
||||
@ -902,7 +902,7 @@ bool imgtool_validitychecks(void)
|
||||
if ((!module->createimage_optguide && !module->createimage_optspec.empty())
|
||||
|| (module->createimage_optguide && module->createimage_optspec.empty()))
|
||||
{
|
||||
util::stream_format(std::wcerr, L"imgtool module %s does has partially incomplete creation options\n", wstring_from_utf8(module->name));
|
||||
util::stream_format(std::wcerr, L"imgtool module %s has partially incomplete creation options\n", wstring_from_utf8(module->name));
|
||||
error = true;
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user