From 540f1eefb48b00bda16eafcaa735a7ef1f8faa39 Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Wed, 10 Dec 2008 17:50:50 +0000 Subject: [PATCH] Pointer-ified the lr35902 core. --- src/emu/cpu/lr35902/lr35902.c | 318 ++++++------ src/emu/cpu/lr35902/lr35902.h | 6 +- src/emu/cpu/lr35902/opc_cb.h | 586 +++++++++++----------- src/emu/cpu/lr35902/opc_main.h | 858 ++++++++++++++++----------------- 4 files changed, 880 insertions(+), 888 deletions(-) diff --git a/src/emu/cpu/lr35902/lr35902.c b/src/emu/cpu/lr35902/lr35902.c index 22e4f8650a9..59c4fe30135 100644 --- a/src/emu/cpu/lr35902/lr35902.c +++ b/src/emu/cpu/lr35902/lr35902.c @@ -45,9 +45,9 @@ #define FLAG_H 0x20 #define FLAG_C 0x10 -#define CYCLES_PASSED(X) lr35902_ICount -= ((X) / (Regs.w.gb_speed)); \ - if ( Regs.w.timer_fired_func ) { \ - Regs.w.timer_fired_func( X ); \ +#define CYCLES_PASSED(X) cpustate->w.icount -= ((X) / (cpustate->w.gb_speed)); \ + if ( cpustate->w.timer_fired_func ) { \ + cpustate->w.timer_fired_func( cpustate->w.device, X ); \ } typedef struct { @@ -66,8 +66,9 @@ typedef struct { cpu_irq_callback irq_callback; const device_config *device; const address_space *program; + int icount; /* Timer stuff */ - void (*timer_fired_func)(int cycles); + lr35902_timer_fired_func timer_fired_func; /* Fetch & execute related */ int execution_state; UINT8 op; @@ -105,14 +106,14 @@ typedef struct { } lr35902_8BitRegs; #endif -typedef union { + +typedef union _lr35902_state lr35902_state; +union _lr35902_state { lr35902_16BitRegs w; lr35902_8BitRegs b; -} lr35902_regs; +}; -typedef int (*OpcodeEmulator) (void); - -static lr35902_regs Regs; +typedef int (*OpcodeEmulator) (lr35902_state *cpustate); #define IME 0x01 #define HALTED 0x02 @@ -121,25 +122,22 @@ static lr35902_regs Regs; /* Memory functions */ /****************************************************************************/ -#define mem_ReadByte(A) ((UINT8)memory_read_byte_8le(Regs.w.program,A)) -#define mem_WriteByte(A,V) (memory_write_byte_8le(Regs.w.program,A,V)) +#define mem_ReadByte(cs,A) ((UINT8)memory_read_byte_8le((cs)->w.program,A)) +#define mem_WriteByte(cs,A,V) (memory_write_byte_8le((cs)->w.program,A,V)) -INLINE UINT16 mem_ReadWord (UINT32 address) +INLINE UINT16 mem_ReadWord (lr35902_state *cpustate, UINT32 address) { - UINT16 value = (UINT16) mem_ReadByte ((address + 1) & 0xffff) << 8; - value |= mem_ReadByte (address); + UINT16 value = (UINT16) mem_ReadByte (cpustate, (address + 1) & 0xffff) << 8; + value |= mem_ReadByte (cpustate, address); return value; } -INLINE void mem_WriteWord (UINT32 address, UINT16 value) +INLINE void mem_WriteWord (lr35902_state *cpustate, UINT32 address, UINT16 value) { - mem_WriteByte (address, value & 0xFF); - mem_WriteByte ((address + 1) & 0xffff, value >> 8); + mem_WriteByte (cpustate, address, value & 0xFF); + mem_WriteByte (cpustate, (address + 1) & 0xffff, value >> 8); } -/* Nr of cycles to run */ -static int lr35902_ICount; - static const int Cycles[256] = { 4,12, 8, 8, 4, 4, 8, 4,20, 8, 8, 8, 4, 4, 8, 4, @@ -182,65 +180,69 @@ static const int CyclesCB[256] = static CPU_INIT( lr35902 ) { - Regs.w.config = (const lr35902_cpu_core *) device->static_config; - Regs.w.irq_callback = irqcallback; - Regs.w.device = device; - Regs.w.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + lr35902_state *cpustate = device->token; + + cpustate->w.config = (const lr35902_cpu_core *) device->static_config; + cpustate->w.irq_callback = irqcallback; + cpustate->w.device = device; + cpustate->w.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); } /*** Reset lr353902 registers: ******************************/ /*** This function can be used to reset the register ***/ -/*** file before starting execution with lr35902_execute()***/ +/*** file before starting execution with lr35902_execute(cpustate)***/ /*** It sets the registers to their initial values. ***/ /************************************************************/ static CPU_RESET( lr35902 ) { - Regs.w.AF = 0x0000; - Regs.w.BC = 0x0000; - Regs.w.DE = 0x0000; - Regs.w.HL = 0x0000; - Regs.w.SP = 0x0000; - Regs.w.PC = 0x0000; - Regs.w.timer_fired_func = NULL; - Regs.w.features = LR35902_FEATURE_HALT_BUG; - if (Regs.w.config) + lr35902_state *cpustate = device->token; + + cpustate->w.AF = 0x0000; + cpustate->w.BC = 0x0000; + cpustate->w.DE = 0x0000; + cpustate->w.HL = 0x0000; + cpustate->w.SP = 0x0000; + cpustate->w.PC = 0x0000; + cpustate->w.timer_fired_func = NULL; + cpustate->w.features = LR35902_FEATURE_HALT_BUG; + if (cpustate->w.config) { - if ( Regs.w.config->regs ) { - Regs.w.AF = Regs.w.config->regs[0]; - Regs.w.BC = Regs.w.config->regs[1]; - Regs.w.DE = Regs.w.config->regs[2]; - Regs.w.HL = Regs.w.config->regs[3]; - Regs.w.SP = Regs.w.config->regs[4]; - Regs.w.PC = Regs.w.config->regs[5]; + if ( cpustate->w.config->regs ) { + cpustate->w.AF = cpustate->w.config->regs[0]; + cpustate->w.BC = cpustate->w.config->regs[1]; + cpustate->w.DE = cpustate->w.config->regs[2]; + cpustate->w.HL = cpustate->w.config->regs[3]; + cpustate->w.SP = cpustate->w.config->regs[4]; + cpustate->w.PC = cpustate->w.config->regs[5]; } - Regs.w.timer_fired_func = Regs.w.config->timer_fired_func; - Regs.w.features = Regs.w.config->features; + cpustate->w.timer_fired_func = cpustate->w.config->timer_fired_func; + cpustate->w.features = cpustate->w.config->features; } - Regs.w.enable = 0; - Regs.w.IE = 0; - Regs.w.IF = 0; + cpustate->w.enable = 0; + cpustate->w.IE = 0; + cpustate->w.IF = 0; - Regs.w.execution_state = 0; - Regs.w.doHALTbug = 0; - Regs.w.ei_delay = 0; - Regs.w.gb_speed_change_pending = 0; - Regs.w.gb_speed = 1; + cpustate->w.execution_state = 0; + cpustate->w.doHALTbug = 0; + cpustate->w.ei_delay = 0; + cpustate->w.gb_speed_change_pending = 0; + cpustate->w.gb_speed = 1; } -INLINE void lr35902_ProcessInterrupts (void) +INLINE void lr35902_ProcessInterrupts (lr35902_state *cpustate) { - UINT8 irq = Regs.w.IE & Regs.w.IF; + UINT8 irq = cpustate->w.IE & cpustate->w.IF; /* Interrupts should be taken after the first instruction after an EI instruction */ - if (Regs.w.ei_delay) { - Regs.w.ei_delay = 0; + if (cpustate->w.ei_delay) { + cpustate->w.ei_delay = 0; return; } /* logerror("Attempting to process LR35902 Interrupt IRQ $%02X\n", irq); - logerror("Attempting to process LR35902 Interrupt IE $%02X\n", Regs.w.IE); - logerror("Attempting to process LR35902 Interrupt IF $%02X\n", Regs.w.IF); + logerror("Attempting to process LR35902 Interrupt IE $%02X\n", cpustate->w.IE); + logerror("Attempting to process LR35902 Interrupt IF $%02X\n", cpustate->w.IF); */ if (irq) { @@ -253,17 +255,17 @@ INLINE void lr35902_ProcessInterrupts (void) { if( irq & (1<w.enable & HALTED) { - Regs.w.enable &= ~HALTED; - Regs.w.IF &= ~(1 << irqline); - Regs.w.PC++; - if ( Regs.w.features & LR35902_FEATURE_HALT_BUG ) { - if ( ! Regs.w.enable & IME ) { + cpustate->w.enable &= ~HALTED; + cpustate->w.IF &= ~(1 << irqline); + cpustate->w.PC++; + if ( cpustate->w.features & LR35902_FEATURE_HALT_BUG ) { + if ( ! cpustate->w.enable & IME ) { /* Old cpu core (dmg/mgb/sgb) */ /* check if the HALT bug should be performed */ - if ( Regs.w.haltIFstatus ) { - Regs.w.doHALTbug = 1; + if ( cpustate->w.haltIFstatus ) { + cpustate->w.doHALTbug = 1; } } } else { @@ -275,16 +277,16 @@ INLINE void lr35902_ProcessInterrupts (void) } } } - if ( Regs.w.enable & IME ) { - if ( Regs.w.irq_callback ) - (*Regs.w.irq_callback)(Regs.w.device, irqline); - Regs.w.enable &= ~IME; - Regs.w.IF &= ~(1 << irqline); + if ( cpustate->w.enable & IME ) { + if ( cpustate->w.irq_callback ) + (*cpustate->w.irq_callback)(cpustate->w.device, irqline); + cpustate->w.enable &= ~IME; + cpustate->w.IF &= ~(1 << irqline); CYCLES_PASSED( 20 ); - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x40 + irqline * 8; - /*logerror("LR35902 Interrupt PC $%04X\n", Regs.w.PC );*/ + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x40 + irqline * 8; + /*logerror("LR35902 Interrupt PC $%04X\n", cpustate->w.PC );*/ return; } } @@ -298,100 +300,86 @@ INLINE void lr35902_ProcessInterrupts (void) /************************************************************/ static CPU_EXECUTE( lr35902 ) { - lr35902_ICount = cycles; + lr35902_state *cpustate = device->token; + + cpustate->w.icount = cycles; do { - if ( Regs.w.execution_state ) { + if ( cpustate->w.execution_state ) { UINT8 x; /* Execute instruction */ - switch( Regs.w.op ) { + switch( cpustate->w.op ) { #include "opc_main.h" } } else { /* Fetch and count cycles */ - lr35902_ProcessInterrupts (); - debugger_instruction_hook(device, Regs.w.PC); - if ( Regs.w.enable & HALTED ) { + lr35902_ProcessInterrupts (cpustate); + debugger_instruction_hook(device, cpustate->w.PC); + if ( cpustate->w.enable & HALTED ) { CYCLES_PASSED( Cycles[0x76] ); - Regs.w.execution_state = 1; + cpustate->w.execution_state = 1; } else { - Regs.w.op = mem_ReadByte (Regs.w.PC++); - if ( Regs.w.doHALTbug ) { - Regs.w.PC--; - Regs.w.doHALTbug = 0; + cpustate->w.op = mem_ReadByte (cpustate, cpustate->w.PC++); + if ( cpustate->w.doHALTbug ) { + cpustate->w.PC--; + cpustate->w.doHALTbug = 0; } - CYCLES_PASSED( Cycles[Regs.w.op] ); + CYCLES_PASSED( Cycles[cpustate->w.op] ); } } - Regs.w.execution_state ^= 1; - } while (lr35902_ICount > 0); + cpustate->w.execution_state ^= 1; + } while (cpustate->w.icount > 0); - return cycles - lr35902_ICount; + return cycles - cpustate->w.icount; } static CPU_BURN( lr35902 ) { + lr35902_state *cpustate = device->token; + if( cycles > 0 ) { /* NOP takes 4 cycles per instruction */ int n = (cycles + 3) / 4; - lr35902_ICount -= 4 * n; + cpustate->w.icount -= 4 * n; } } -/****************************************************************************/ -/* Set all registers to given values */ -/****************************************************************************/ -static CPU_SET_CONTEXT( lr35902 ) -{ - if( src ) - Regs = *(lr35902_regs *)src; -} - -/****************************************************************************/ -/* Get all registers in given buffer */ -/****************************************************************************/ -static CPU_GET_CONTEXT( lr35902 ) -{ - if( dst ) - *(lr35902_regs *)dst = Regs; -} - - - -static void lr35902_set_irq_line (int irqline, int state) +static void lr35902_set_irq_line (lr35902_state *cpustate, int irqline, int state) { /*logerror("setting irq line 0x%02x state 0x%08x\n", irqline, state);*/ - //if( Regs.w.irq_state == state ) + //if( cpustate->w.irq_state == state ) // return; - Regs.w.irq_state = state; + cpustate->w.irq_state = state; if( state == ASSERT_LINE ) { - Regs.w.IF |= (0x01 << irqline); - /*logerror("LR35902 assert irq line %d ($%02X)\n", irqline, Regs.w.IF);*/ + cpustate->w.IF |= (0x01 << irqline); + /*logerror("LR35902 assert irq line %d ($%02X)\n", irqline, cpustate->w.IF);*/ } else { - Regs.w.IF &= ~(0x01 << irqline); - /*logerror("LR35902 clear irq line %d ($%02X)\n", irqline, Regs.w.IF);*/ + cpustate->w.IF &= ~(0x01 << irqline); + /*logerror("LR35902 clear irq line %d ($%02X)\n", irqline, cpustate->w.IF);*/ } } #ifdef UNUSED_FUNCTION -static void lr35902_clear_pending_interrupts (void) +static void lr35902_clear_pending_interrupts (lr35902_state *cpustate) { - Regs.w.IF = 0; + cpustate->w.IF = 0; } #endif static CPU_SET_INFO( lr35902 ) { + lr35902_state *cpustate = device->token; + switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ @@ -399,29 +387,31 @@ static CPU_SET_INFO( lr35902 ) case CPUINFO_INT_INPUT_STATE + 1: case CPUINFO_INT_INPUT_STATE + 2: case CPUINFO_INT_INPUT_STATE + 3: - case CPUINFO_INT_INPUT_STATE + 4: lr35902_set_irq_line(state-CPUINFO_INT_INPUT_STATE, info->i); break; + case CPUINFO_INT_INPUT_STATE + 4: lr35902_set_irq_line(cpustate, state-CPUINFO_INT_INPUT_STATE, info->i); break; - case CPUINFO_INT_SP: Regs.w.SP = info->i; break; - case CPUINFO_INT_PC: Regs.w.PC = info->i; break; + case CPUINFO_INT_SP: cpustate->w.SP = info->i; break; + case CPUINFO_INT_PC: cpustate->w.PC = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_PC: Regs.w.PC = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_SP: Regs.w.SP = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_AF: Regs.w.AF = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_BC: Regs.w.BC = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_DE: Regs.w.DE = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_HL: Regs.w.HL = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_IE: Regs.w.IE = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_IF: Regs.w.IF = info->i; break; - case CPUINFO_INT_REGISTER + LR35902_SPEED: Regs.w.gb_speed_change_pending = info->i & 0x01; break; + case CPUINFO_INT_REGISTER + LR35902_PC: cpustate->w.PC = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_SP: cpustate->w.SP = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_AF: cpustate->w.AF = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_BC: cpustate->w.BC = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_DE: cpustate->w.DE = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_HL: cpustate->w.HL = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_IE: cpustate->w.IE = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_IF: cpustate->w.IF = info->i; break; + case CPUINFO_INT_REGISTER + LR35902_SPEED: cpustate->w.gb_speed_change_pending = info->i & 0x01; break; } } CPU_GET_INFO( lr35902 ) { + lr35902_state *cpustate = (device != NULL) ? device->token : NULL; + switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(Regs); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(lr35902_state); break; case CPUINFO_INT_INPUT_LINES: info->i = 5; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0xff; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; @@ -442,36 +432,36 @@ CPU_GET_INFO( lr35902 ) case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 16; break; case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break; - case CPUINFO_INT_SP: info->i = Regs.w.SP; break; - case CPUINFO_INT_PC: info->i = Regs.w.PC; break; + case CPUINFO_INT_SP: info->i = cpustate->w.SP; break; + case CPUINFO_INT_PC: info->i = cpustate->w.PC; break; case CPUINFO_INT_PREVIOUSPC: info->i = 0; /* TODO??? */ break; case CPUINFO_INT_INPUT_STATE + 0: case CPUINFO_INT_INPUT_STATE + 1: case CPUINFO_INT_INPUT_STATE + 2: case CPUINFO_INT_INPUT_STATE + 3: - case CPUINFO_INT_INPUT_STATE + 4: info->i = Regs.w.IF & (1 << (state-CPUINFO_INT_INPUT_STATE)); break; + case CPUINFO_INT_INPUT_STATE + 4: info->i = cpustate->w.IF & (1 << (state-CPUINFO_INT_INPUT_STATE)); break; - case CPUINFO_INT_REGISTER + LR35902_PC: info->i = Regs.w.PC; break; - case CPUINFO_INT_REGISTER + LR35902_SP: info->i = Regs.w.SP; break; - case CPUINFO_INT_REGISTER + LR35902_AF: info->i = Regs.w.AF; break; - case CPUINFO_INT_REGISTER + LR35902_BC: info->i = Regs.w.BC; break; - case CPUINFO_INT_REGISTER + LR35902_DE: info->i = Regs.w.DE; break; - case CPUINFO_INT_REGISTER + LR35902_HL: info->i = Regs.w.HL; break; - case CPUINFO_INT_REGISTER + LR35902_IE: info->i = Regs.w.IE; break; - case CPUINFO_INT_REGISTER + LR35902_IF: info->i = Regs.w.IF; break; - case CPUINFO_INT_REGISTER + LR35902_SPEED: info->i = 0x7E | ( ( Regs.w.gb_speed - 1 ) << 7 ) | Regs.w.gb_speed_change_pending; break; + case CPUINFO_INT_REGISTER + LR35902_PC: info->i = cpustate->w.PC; break; + case CPUINFO_INT_REGISTER + LR35902_SP: info->i = cpustate->w.SP; break; + case CPUINFO_INT_REGISTER + LR35902_AF: info->i = cpustate->w.AF; break; + case CPUINFO_INT_REGISTER + LR35902_BC: info->i = cpustate->w.BC; break; + case CPUINFO_INT_REGISTER + LR35902_DE: info->i = cpustate->w.DE; break; + case CPUINFO_INT_REGISTER + LR35902_HL: info->i = cpustate->w.HL; break; + case CPUINFO_INT_REGISTER + LR35902_IE: info->i = cpustate->w.IE; break; + case CPUINFO_INT_REGISTER + LR35902_IF: info->i = cpustate->w.IF; break; + case CPUINFO_INT_REGISTER + LR35902_SPEED: info->i = 0x7E | ( ( cpustate->w.gb_speed - 1 ) << 7 ) | cpustate->w.gb_speed_change_pending; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(lr35902); break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(lr35902); break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(lr35902); break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(lr35902); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(lr35902); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(lr35902); break; case CPUINFO_PTR_BURN: info->burn = CPU_BURN_NAME(lr35902); break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(lr35902); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &lr35902_ICount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->w.icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s, "LR35902"); break; @@ -482,24 +472,24 @@ CPU_GET_INFO( lr35902 ) case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", - Regs.b.F & 0x80 ? 'Z':'.', - Regs.b.F & 0x40 ? 'N':'.', - Regs.b.F & 0x20 ? 'H':'.', - Regs.b.F & 0x10 ? 'C':'.', - Regs.b.F & 0x08 ? '3':'.', - Regs.b.F & 0x04 ? '2':'.', - Regs.b.F & 0x02 ? '1':'.', - Regs.b.F & 0x01 ? '0':'.'); + cpustate->b.F & 0x80 ? 'Z':'.', + cpustate->b.F & 0x40 ? 'N':'.', + cpustate->b.F & 0x20 ? 'H':'.', + cpustate->b.F & 0x10 ? 'C':'.', + cpustate->b.F & 0x08 ? '3':'.', + cpustate->b.F & 0x04 ? '2':'.', + cpustate->b.F & 0x02 ? '1':'.', + cpustate->b.F & 0x01 ? '0':'.'); break; - case CPUINFO_STR_REGISTER + LR35902_PC: sprintf(info->s, "PC:%04X", Regs.w.PC); break; - case CPUINFO_STR_REGISTER + LR35902_SP: sprintf(info->s, "SP:%04X", Regs.w.SP); break; - case CPUINFO_STR_REGISTER + LR35902_AF: sprintf(info->s, "AF:%04X", Regs.w.AF); break; - case CPUINFO_STR_REGISTER + LR35902_BC: sprintf(info->s, "BC:%04X", Regs.w.BC); break; - case CPUINFO_STR_REGISTER + LR35902_DE: sprintf(info->s, "DE:%04X", Regs.w.DE); break; - case CPUINFO_STR_REGISTER + LR35902_HL: sprintf(info->s, "HL:%04X", Regs.w.HL); break; - case CPUINFO_STR_REGISTER + LR35902_IRQ_STATE: sprintf(info->s, "IRQ:%X", Regs.w.enable & IME ); break; - case CPUINFO_STR_REGISTER + LR35902_IE: sprintf(info->s, "IE:%02X", Regs.w.IE); break; - case CPUINFO_STR_REGISTER + LR35902_IF: sprintf(info->s, "IF:%02X", Regs.w.IF); break; + case CPUINFO_STR_REGISTER + LR35902_PC: sprintf(info->s, "PC:%04X", cpustate->w.PC); break; + case CPUINFO_STR_REGISTER + LR35902_SP: sprintf(info->s, "SP:%04X", cpustate->w.SP); break; + case CPUINFO_STR_REGISTER + LR35902_AF: sprintf(info->s, "AF:%04X", cpustate->w.AF); break; + case CPUINFO_STR_REGISTER + LR35902_BC: sprintf(info->s, "BC:%04X", cpustate->w.BC); break; + case CPUINFO_STR_REGISTER + LR35902_DE: sprintf(info->s, "DE:%04X", cpustate->w.DE); break; + case CPUINFO_STR_REGISTER + LR35902_HL: sprintf(info->s, "HL:%04X", cpustate->w.HL); break; + case CPUINFO_STR_REGISTER + LR35902_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->w.enable & IME ); break; + case CPUINFO_STR_REGISTER + LR35902_IE: sprintf(info->s, "IE:%02X", cpustate->w.IE); break; + case CPUINFO_STR_REGISTER + LR35902_IF: sprintf(info->s, "IF:%02X", cpustate->w.IF); break; } } diff --git a/src/emu/cpu/lr35902/lr35902.h b/src/emu/cpu/lr35902/lr35902.h index ae35f59f0c6..9fde7856e3a 100644 --- a/src/emu/cpu/lr35902/lr35902.h +++ b/src/emu/cpu/lr35902/lr35902.h @@ -5,12 +5,14 @@ #include "cpuintrf.h" +typedef void (*lr35902_timer_fired_func)(const device_config *device, int cycles); + typedef struct _lr35902_cpu_core lr35902_cpu_core; struct _lr35902_cpu_core { const UINT16 *regs; - UINT8 features; - void (*timer_fired_func)(int cycles); + UINT8 features; + lr35902_timer_fired_func timer_fired_func; }; enum diff --git a/src/emu/cpu/lr35902/opc_cb.h b/src/emu/cpu/lr35902/opc_cb.h index 4f85e6a8fb7..080aeb5478b 100644 --- a/src/emu/cpu/lr35902/opc_cb.h +++ b/src/emu/cpu/lr35902/opc_cb.h @@ -8,17 +8,17 @@ f=0; \ if( (x)==0 ) \ f|=FLAG_Z; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define RL_8BIT(x) \ { \ register UINT8 r; \ r=((x)&0x80)?FLAG_C:0; \ - (x)=(UINT8)(((x)<<1)|((Regs.b.F&FLAG_C)?1:0)); \ + (x)=(UINT8)(((x)<<1)|((cpustate->b.F&FLAG_C)?1:0)); \ if( (x)==0 ) \ r|=FLAG_Z; \ - Regs.b.F=r; \ + cpustate->b.F=r; \ } #define RRC_8BIT(x) \ @@ -31,17 +31,17 @@ f=0; \ if( (x)==0 ) \ f|=FLAG_Z; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define RR_8BIT(x) \ { \ register UINT8 r; \ r=((x)&1)?FLAG_C:0; \ - (x)=(UINT8)(((x)>>1)|((Regs.b.F&FLAG_C)?0x80:0)); \ + (x)=(UINT8)(((x)>>1)|((cpustate->b.F&FLAG_C)?0x80:0)); \ if( (x)==0 ) \ r|=FLAG_Z; \ - Regs.b.F=r; \ + cpustate->b.F=r; \ } #define SLA_8BIT(x) \ @@ -54,7 +54,7 @@ (x)<<=1; \ if( (x)==0 ) \ f|=FLAG_Z; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define SRA_8BIT(x) \ @@ -67,15 +67,15 @@ (x)=(UINT8)(((char)(x))>>1); \ if( (x)==0 ) \ f|=FLAG_Z; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define SWAP_8BIT(x) \ (x)=(UINT8)(((x)>>4)|((x)<<4)); \ if( (x)==0 ) \ - Regs.b.F=FLAG_Z; \ + cpustate->b.F=FLAG_Z; \ else \ - Regs.b.F=0; + cpustate->b.F=0; #define SRL_8BIT(x) \ @@ -88,14 +88,14 @@ (x)>>=1; \ if( (x)==0 ) \ f|=FLAG_Z; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define BIT_8BIT(n,x) \ if( (x)&(1<<(n)) ) \ - Regs.b.F=(UINT8)(FLAG_H|(Regs.b.F&FLAG_C)); \ + cpustate->b.F=(UINT8)(FLAG_H|(cpustate->b.F&FLAG_C)); \ else \ - Regs.b.F=(UINT8)(FLAG_Z|FLAG_H|(Regs.b.F&FLAG_C)); + cpustate->b.F=(UINT8)(FLAG_Z|FLAG_H|(cpustate->b.F&FLAG_C)); #define RES_8BIT(n,x) (x)&=~(1<<(n)); @@ -105,1336 +105,1336 @@ case 0x00: /* RLC B */ - RLC_8BIT (Regs.b.B) + RLC_8BIT (cpustate->b.B) break; case 0x01: /* RLC C */ - RLC_8BIT (Regs.b.C) + RLC_8BIT (cpustate->b.C) break; case 0x02: /* RLC D */ - RLC_8BIT (Regs.b.D) + RLC_8BIT (cpustate->b.D) break; case 0x03: /* RLC E */ - RLC_8BIT (Regs.b.E) + RLC_8BIT (cpustate->b.E) break; case 0x04: /* RLC H */ - RLC_8BIT (Regs.b.H) + RLC_8BIT (cpustate->b.H) break; case 0x05: /* RLC L */ - RLC_8BIT (Regs.b.L) + RLC_8BIT (cpustate->b.L) break; case 0x06: /* RLC (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RLC_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x07: /* RLC A */ - RLC_8BIT (Regs.b.A) + RLC_8BIT (cpustate->b.A) break; case 0x08: /* RRC B */ - RRC_8BIT (Regs.b.B) + RRC_8BIT (cpustate->b.B) break; case 0x09: /* RRC C */ - RRC_8BIT (Regs.b.C) + RRC_8BIT (cpustate->b.C) break; case 0x0A: /* RRC D */ - RRC_8BIT (Regs.b.D) + RRC_8BIT (cpustate->b.D) break; case 0x0B: /* RRC E */ - RRC_8BIT (Regs.b.E) + RRC_8BIT (cpustate->b.E) break; case 0x0C: /* RRC H */ - RRC_8BIT (Regs.b.H) + RRC_8BIT (cpustate->b.H) break; case 0x0D: /* RRC L */ - RRC_8BIT (Regs.b.L) + RRC_8BIT (cpustate->b.L) break; case 0x0E: /* RRC (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RRC_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x0F: /* RRC A */ - RRC_8BIT (Regs.b.A) + RRC_8BIT (cpustate->b.A) break; case 0x10: /* RL B */ - RL_8BIT (Regs.b.B) + RL_8BIT (cpustate->b.B) break; case 0x11: /* RL C */ - RL_8BIT (Regs.b.C) + RL_8BIT (cpustate->b.C) break; case 0x12: /* RL D */ - RL_8BIT (Regs.b.D) + RL_8BIT (cpustate->b.D) break; case 0x13: /* RL E */ - RL_8BIT (Regs.b.E) + RL_8BIT (cpustate->b.E) break; case 0x14: /* RL H */ - RL_8BIT (Regs.b.H) + RL_8BIT (cpustate->b.H) break; case 0x15: /* RL L */ - RL_8BIT (Regs.b.L) + RL_8BIT (cpustate->b.L) break; case 0x16: /* RL (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RL_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x17: /* RL A */ - RL_8BIT (Regs.b.A) + RL_8BIT (cpustate->b.A) break; case 0x18: /* RR B */ - RR_8BIT (Regs.b.B) + RR_8BIT (cpustate->b.B) break; case 0x19: /* RR C */ - RR_8BIT (Regs.b.C) + RR_8BIT (cpustate->b.C) break; case 0x1A: /* RR D */ - RR_8BIT (Regs.b.D) + RR_8BIT (cpustate->b.D) break; case 0x1B: /* RR E */ - RR_8BIT (Regs.b.E) + RR_8BIT (cpustate->b.E) break; case 0x1C: /* RR H */ - RR_8BIT (Regs.b.H) + RR_8BIT (cpustate->b.H) break; case 0x1D: /* RR L */ - RR_8BIT (Regs.b.L) + RR_8BIT (cpustate->b.L) break; case 0x1E: /* RR (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RR_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x1F: /* RR A */ - RR_8BIT (Regs.b.A) + RR_8BIT (cpustate->b.A) break; case 0x20: /* SLA B */ - SLA_8BIT (Regs.b.B) + SLA_8BIT (cpustate->b.B) break; case 0x21: /* SLA C */ - SLA_8BIT (Regs.b.C) + SLA_8BIT (cpustate->b.C) break; case 0x22: /* SLA D */ - SLA_8BIT (Regs.b.D) + SLA_8BIT (cpustate->b.D) break; case 0x23: /* SLA E */ - SLA_8BIT (Regs.b.E) + SLA_8BIT (cpustate->b.E) break; case 0x24: /* SLA H */ - SLA_8BIT (Regs.b.H) + SLA_8BIT (cpustate->b.H) break; case 0x25: /* SLA L */ - SLA_8BIT (Regs.b.L) + SLA_8BIT (cpustate->b.L) break; case 0x26: /* SLA (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SLA_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x27: /* SLA A */ - SLA_8BIT (Regs.b.A) + SLA_8BIT (cpustate->b.A) break; case 0x28: /* SRA B */ - SRA_8BIT (Regs.b.B) + SRA_8BIT (cpustate->b.B) break; case 0x29: /* SRA C */ - SRA_8BIT (Regs.b.C) + SRA_8BIT (cpustate->b.C) break; case 0x2A: /* SRA D */ - SRA_8BIT (Regs.b.D) + SRA_8BIT (cpustate->b.D) break; case 0x2B: /* SRA E */ - SRA_8BIT (Regs.b.E) + SRA_8BIT (cpustate->b.E) break; case 0x2C: /* SRA H */ - SRA_8BIT (Regs.b.H) + SRA_8BIT (cpustate->b.H) break; case 0x2D: /* SRA L */ - SRA_8BIT (Regs.b.L) + SRA_8BIT (cpustate->b.L) break; case 0x2E: /* SRA (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SRA_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x2F: /* SRA A */ - SRA_8BIT (Regs.b.A) + SRA_8BIT (cpustate->b.A) break; case 0x30: /* SWAP B */ - SWAP_8BIT (Regs.b.B) + SWAP_8BIT (cpustate->b.B) break; case 0x31: /* SWAP C */ - SWAP_8BIT (Regs.b.C) + SWAP_8BIT (cpustate->b.C) break; case 0x32: /* SWAP D */ - SWAP_8BIT (Regs.b.D) + SWAP_8BIT (cpustate->b.D) break; case 0x33: /* SWAP E */ - SWAP_8BIT (Regs.b.E) + SWAP_8BIT (cpustate->b.E) break; case 0x34: /* SWAP H */ - SWAP_8BIT (Regs.b.H) + SWAP_8BIT (cpustate->b.H) break; case 0x35: /* SWAP L */ - SWAP_8BIT (Regs.b.L) + SWAP_8BIT (cpustate->b.L) break; case 0x36: /* SWAP (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SWAP_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x37: /* SWAP A */ - SWAP_8BIT (Regs.b.A) + SWAP_8BIT (cpustate->b.A) break; case 0x38: /* SRL B */ - SRL_8BIT (Regs.b.B) + SRL_8BIT (cpustate->b.B) break; case 0x39: /* SRL C */ - SRL_8BIT (Regs.b.C) + SRL_8BIT (cpustate->b.C) break; case 0x3A: /* SRL D */ - SRL_8BIT (Regs.b.D) + SRL_8BIT (cpustate->b.D) break; case 0x3B: /* SRL E */ - SRL_8BIT (Regs.b.E) + SRL_8BIT (cpustate->b.E) break; case 0x3C: /* SRL H */ - SRL_8BIT (Regs.b.H) + SRL_8BIT (cpustate->b.H) break; case 0x3D: /* SRL L */ - SRL_8BIT (Regs.b.L) + SRL_8BIT (cpustate->b.L) break; case 0x3E: /* SRL (HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SRL_8BIT (x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x3F: /* SRL A */ - SRL_8BIT (Regs.b.A) + SRL_8BIT (cpustate->b.A) break; case 0x40: /* BIT 0,B */ - BIT_8BIT (0, Regs.b.B) + BIT_8BIT (0, cpustate->b.B) break; case 0x41: /* BIT 0,C */ - BIT_8BIT (0, Regs.b.C) + BIT_8BIT (0, cpustate->b.C) break; case 0x42: /* BIT 0,D */ - BIT_8BIT (0, Regs.b.D) + BIT_8BIT (0, cpustate->b.D) break; case 0x43: /* BIT 0,E */ - BIT_8BIT (0, Regs.b.E) + BIT_8BIT (0, cpustate->b.E) break; case 0x44: /* BIT 0,H */ - BIT_8BIT (0, Regs.b.H) + BIT_8BIT (0, cpustate->b.H) break; case 0x45: /* BIT 0,L */ - BIT_8BIT (0, Regs.b.L) + BIT_8BIT (0, cpustate->b.L) break; case 0x46: /* BIT 0,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (0, x) break; case 0x47: /* BIT 0,A */ - BIT_8BIT (0, Regs.b.A) + BIT_8BIT (0, cpustate->b.A) break; case 0x48: /* BIT 1,B */ - BIT_8BIT (1, Regs.b.B) + BIT_8BIT (1, cpustate->b.B) break; case 0x49: /* BIT 1,C */ - BIT_8BIT (1, Regs.b.C) + BIT_8BIT (1, cpustate->b.C) break; case 0x4A: /* BIT 1,D */ - BIT_8BIT (1, Regs.b.D) + BIT_8BIT (1, cpustate->b.D) break; case 0x4B: /* BIT 1,E */ - BIT_8BIT (1, Regs.b.E) + BIT_8BIT (1, cpustate->b.E) break; case 0x4C: /* BIT 1,H */ - BIT_8BIT (1, Regs.b.H) + BIT_8BIT (1, cpustate->b.H) break; case 0x4D: /* BIT 1,L */ - BIT_8BIT (1, Regs.b.L) + BIT_8BIT (1, cpustate->b.L) break; case 0x4E: /* BIT 1,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (1, x) break; case 0x4F: /* BIT 1,A */ - BIT_8BIT (1, Regs.b.A) + BIT_8BIT (1, cpustate->b.A) break; case 0x50: /* BIT 2,B */ - BIT_8BIT (2, Regs.b.B) + BIT_8BIT (2, cpustate->b.B) break; case 0x51: /* BIT 2,C */ - BIT_8BIT (2, Regs.b.C) + BIT_8BIT (2, cpustate->b.C) break; case 0x52: /* BIT 2,D */ - BIT_8BIT (2, Regs.b.D) + BIT_8BIT (2, cpustate->b.D) break; case 0x53: /* BIT 2,E */ - BIT_8BIT (2, Regs.b.E) + BIT_8BIT (2, cpustate->b.E) break; case 0x54: /* BIT 2,H */ - BIT_8BIT (2, Regs.b.H) + BIT_8BIT (2, cpustate->b.H) break; case 0x55: /* BIT 2,L */ - BIT_8BIT (2, Regs.b.L) + BIT_8BIT (2, cpustate->b.L) break; case 0x56: /* BIT 2,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (2, x) break; case 0x57: /* BIT 2,A */ - BIT_8BIT (2, Regs.b.A) + BIT_8BIT (2, cpustate->b.A) break; case 0x58: /* BIT 3,B */ - BIT_8BIT (3, Regs.b.B) + BIT_8BIT (3, cpustate->b.B) break; case 0x59: /* BIT 3,C */ - BIT_8BIT (3, Regs.b.C) + BIT_8BIT (3, cpustate->b.C) break; case 0x5A: /* BIT 3,D */ - BIT_8BIT (3, Regs.b.D) + BIT_8BIT (3, cpustate->b.D) break; case 0x5B: /* BIT 3,E */ - BIT_8BIT (3, Regs.b.E) + BIT_8BIT (3, cpustate->b.E) break; case 0x5C: /* BIT 3,H */ - BIT_8BIT (3, Regs.b.H) + BIT_8BIT (3, cpustate->b.H) break; case 0x5D: /* BIT 3,L */ - BIT_8BIT (3, Regs.b.L) + BIT_8BIT (3, cpustate->b.L) break; case 0x5E: /* BIT 3,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (3, x) break; case 0x5F: /* BIT 3,A */ - BIT_8BIT (3, Regs.b.A) + BIT_8BIT (3, cpustate->b.A) break; case 0x60: /* BIT 4,B */ - BIT_8BIT (4, Regs.b.B) + BIT_8BIT (4, cpustate->b.B) break; case 0x61: /* BIT 4,C */ - BIT_8BIT (4, Regs.b.C) + BIT_8BIT (4, cpustate->b.C) break; case 0x62: /* BIT 4,D */ - BIT_8BIT (4, Regs.b.D) + BIT_8BIT (4, cpustate->b.D) break; case 0x63: /* BIT 4,E */ - BIT_8BIT (4, Regs.b.E) + BIT_8BIT (4, cpustate->b.E) break; case 0x64: /* BIT 4,H */ - BIT_8BIT (4, Regs.b.H) + BIT_8BIT (4, cpustate->b.H) break; case 0x65: /* BIT 4,L */ - BIT_8BIT (4, Regs.b.L) + BIT_8BIT (4, cpustate->b.L) break; case 0x66: /* BIT 4,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (4, x) break; case 0x67: /* BIT 4,A */ - BIT_8BIT (4, Regs.b.A) + BIT_8BIT (4, cpustate->b.A) break; case 0x68: /* BIT 5,B */ - BIT_8BIT (5, Regs.b.B) + BIT_8BIT (5, cpustate->b.B) break; case 0x69: /* BIT 5,C */ - BIT_8BIT (5, Regs.b.C) + BIT_8BIT (5, cpustate->b.C) break; case 0x6A: /* BIT 5,D */ - BIT_8BIT (5, Regs.b.D) + BIT_8BIT (5, cpustate->b.D) break; case 0x6B: /* BIT 5,E */ - BIT_8BIT (5, Regs.b.E) + BIT_8BIT (5, cpustate->b.E) break; case 0x6C: /* BIT 5,H */ - BIT_8BIT (5, Regs.b.H) + BIT_8BIT (5, cpustate->b.H) break; case 0x6D: /* BIT 5,L */ - BIT_8BIT (5, Regs.b.L) + BIT_8BIT (5, cpustate->b.L) break; case 0x6E: /* BIT 5,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (5, x) break; case 0x6F: /* BIT 5,A */ - BIT_8BIT (5, Regs.b.A) + BIT_8BIT (5, cpustate->b.A) break; case 0x70: /* BIT 6,B */ - BIT_8BIT (6, Regs.b.B) + BIT_8BIT (6, cpustate->b.B) break; case 0x71: /* BIT 6,C */ - BIT_8BIT (6, Regs.b.C) + BIT_8BIT (6, cpustate->b.C) break; case 0x72: /* BIT 6,D */ - BIT_8BIT (6, Regs.b.D) + BIT_8BIT (6, cpustate->b.D) break; case 0x73: /* BIT 6,E */ - BIT_8BIT (6, Regs.b.E) + BIT_8BIT (6, cpustate->b.E) break; case 0x74: /* BIT 6,H */ - BIT_8BIT (6, Regs.b.H) + BIT_8BIT (6, cpustate->b.H) break; case 0x75: /* BIT 6,L */ - BIT_8BIT (6, Regs.b.L) + BIT_8BIT (6, cpustate->b.L) break; case 0x76: /* BIT 6,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (6, x) break; case 0x77: /* BIT 6,A */ - BIT_8BIT (6, Regs.b.A) + BIT_8BIT (6, cpustate->b.A) break; case 0x78: /* BIT 7,B */ - BIT_8BIT (7, Regs.b.B) + BIT_8BIT (7, cpustate->b.B) break; case 0x79: /* BIT 7,C */ - BIT_8BIT (7, Regs.b.C) + BIT_8BIT (7, cpustate->b.C) break; case 0x7A: /* BIT 7,D */ - BIT_8BIT (7, Regs.b.D) + BIT_8BIT (7, cpustate->b.D) break; case 0x7B: /* BIT 7,E */ - BIT_8BIT (7, Regs.b.E) + BIT_8BIT (7, cpustate->b.E) break; case 0x7C: /* BIT 7,H */ - BIT_8BIT (7, Regs.b.H) + BIT_8BIT (7, cpustate->b.H) break; case 0x7D: /* BIT 7,L */ - BIT_8BIT (7, Regs.b.L) + BIT_8BIT (7, cpustate->b.L) break; case 0x7E: /* BIT 7,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); BIT_8BIT (7, x) break; case 0x7F: /* BIT 7,A */ - BIT_8BIT (7, Regs.b.A) + BIT_8BIT (7, cpustate->b.A) break; case 0x80: /* RES 0,B */ - RES_8BIT (0, Regs.b.B) + RES_8BIT (0, cpustate->b.B) break; case 0x81: /* RES 0,C */ - RES_8BIT (0, Regs.b.C) + RES_8BIT (0, cpustate->b.C) break; case 0x82: /* RES 0,D */ - RES_8BIT (0, Regs.b.D) + RES_8BIT (0, cpustate->b.D) break; case 0x83: /* RES 0,E */ - RES_8BIT (0, Regs.b.E) + RES_8BIT (0, cpustate->b.E) break; case 0x84: /* RES 0,H */ - RES_8BIT (0, Regs.b.H) + RES_8BIT (0, cpustate->b.H) break; case 0x85: /* RES 0,L */ - RES_8BIT (0, Regs.b.L) + RES_8BIT (0, cpustate->b.L) break; case 0x86: /* RES 0,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (0, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x87: /* RES 0,A */ - RES_8BIT (0, Regs.b.A) + RES_8BIT (0, cpustate->b.A) break; case 0x88: /* RES 1,B */ - RES_8BIT (1, Regs.b.B) + RES_8BIT (1, cpustate->b.B) break; case 0x89: /* RES 1,C */ - RES_8BIT (1, Regs.b.C) + RES_8BIT (1, cpustate->b.C) break; case 0x8A: /* RES 1,D */ - RES_8BIT (1, Regs.b.D) + RES_8BIT (1, cpustate->b.D) break; case 0x8B: /* RES 1,E */ - RES_8BIT (1, Regs.b.E) + RES_8BIT (1, cpustate->b.E) break; case 0x8C: /* RES 1,H */ - RES_8BIT (1, Regs.b.H) + RES_8BIT (1, cpustate->b.H) break; case 0x8D: /* RES 1,L */ - RES_8BIT (1, Regs.b.L) + RES_8BIT (1, cpustate->b.L) break; case 0x8E: /* RES 1,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (1, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x8F: /* RES 1,A */ - RES_8BIT (1, Regs.b.A) + RES_8BIT (1, cpustate->b.A) break; case 0x90: /* RES 2,B */ - RES_8BIT (2, Regs.b.B) + RES_8BIT (2, cpustate->b.B) break; case 0x91: /* RES 2,C */ - RES_8BIT (2, Regs.b.C) + RES_8BIT (2, cpustate->b.C) break; case 0x92: /* RES 2,D */ - RES_8BIT (2, Regs.b.D) + RES_8BIT (2, cpustate->b.D) break; case 0x93: /* RES 2,E */ - RES_8BIT (2, Regs.b.E) + RES_8BIT (2, cpustate->b.E) break; case 0x94: /* RES 2,H */ - RES_8BIT (2, Regs.b.H) + RES_8BIT (2, cpustate->b.H) break; case 0x95: /* RES 2,L */ - RES_8BIT (2, Regs.b.L) + RES_8BIT (2, cpustate->b.L) break; case 0x96: /* RES 2,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (2, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x97: /* RES 2,A */ - RES_8BIT (2, Regs.b.A) + RES_8BIT (2, cpustate->b.A) break; case 0x98: /* RES 3,B */ - RES_8BIT (3, Regs.b.B) + RES_8BIT (3, cpustate->b.B) break; case 0x99: /* RES 3,C */ - RES_8BIT (3, Regs.b.C) + RES_8BIT (3, cpustate->b.C) break; case 0x9A: /* RES 3,D */ - RES_8BIT (3, Regs.b.D) + RES_8BIT (3, cpustate->b.D) break; case 0x9B: /* RES 3,E */ - RES_8BIT (3, Regs.b.E) + RES_8BIT (3, cpustate->b.E) break; case 0x9C: /* RES 3,H */ - RES_8BIT (3, Regs.b.H) + RES_8BIT (3, cpustate->b.H) break; case 0x9D: /* RES 3,L */ - RES_8BIT (3, Regs.b.L) + RES_8BIT (3, cpustate->b.L) break; case 0x9E: /* RES 3,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (3, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0x9F: /* RES 3,A */ - RES_8BIT (3, Regs.b.A) + RES_8BIT (3, cpustate->b.A) break; case 0xA0: /* RES 4,B */ - RES_8BIT (4, Regs.b.B) + RES_8BIT (4, cpustate->b.B) break; case 0xA1: /* RES 4,C */ - RES_8BIT (4, Regs.b.C) + RES_8BIT (4, cpustate->b.C) break; case 0xA2: /* RES 4,D */ - RES_8BIT (4, Regs.b.D) + RES_8BIT (4, cpustate->b.D) break; case 0xA3: /* RES 4,E */ - RES_8BIT (4, Regs.b.E) + RES_8BIT (4, cpustate->b.E) break; case 0xA4: /* RES 4,H */ - RES_8BIT (4, Regs.b.H) + RES_8BIT (4, cpustate->b.H) break; case 0xA5: /* RES 4,L */ - RES_8BIT (4, Regs.b.L) + RES_8BIT (4, cpustate->b.L) break; case 0xA6: /* RES 4,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (4, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xA7: /* RES 4,A */ - RES_8BIT (4, Regs.b.A) + RES_8BIT (4, cpustate->b.A) break; case 0xA8: /* RES 5,B */ - RES_8BIT (5, Regs.b.B) + RES_8BIT (5, cpustate->b.B) break; case 0xA9: /* RES 5,C */ - RES_8BIT (5, Regs.b.C) + RES_8BIT (5, cpustate->b.C) break; case 0xAA: /* RES 5,D */ - RES_8BIT (5, Regs.b.D) + RES_8BIT (5, cpustate->b.D) break; case 0xAB: /* RES 5,E */ - RES_8BIT (5, Regs.b.E) + RES_8BIT (5, cpustate->b.E) break; case 0xAC: /* RES 5,H */ - RES_8BIT (5, Regs.b.H) + RES_8BIT (5, cpustate->b.H) break; case 0xAD: /* RES 5,L */ - RES_8BIT (5, Regs.b.L) + RES_8BIT (5, cpustate->b.L) break; case 0xAE: /* RES 5,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (5, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xAF: /* RES 5,A */ - RES_8BIT (5, Regs.b.A) + RES_8BIT (5, cpustate->b.A) break; case 0xB0: /* RES 6,B */ - RES_8BIT (6, Regs.b.B) + RES_8BIT (6, cpustate->b.B) break; case 0xB1: /* RES 6,C */ - RES_8BIT (6, Regs.b.C) + RES_8BIT (6, cpustate->b.C) break; case 0xB2: /* RES 6,D */ - RES_8BIT (6, Regs.b.D) + RES_8BIT (6, cpustate->b.D) break; case 0xB3: /* RES 6,E */ - RES_8BIT (6, Regs.b.E) + RES_8BIT (6, cpustate->b.E) break; case 0xB4: /* RES 6,H */ - RES_8BIT (6, Regs.b.H) + RES_8BIT (6, cpustate->b.H) break; case 0xB5: /* RES 6,L */ - RES_8BIT (6, Regs.b.L) + RES_8BIT (6, cpustate->b.L) break; case 0xB6: /* RES 6,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (6, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xB7: /* RES 6,A */ - RES_8BIT (6, Regs.b.A) + RES_8BIT (6, cpustate->b.A) break; case 0xB8: /* RES 7,B */ - RES_8BIT (7, Regs.b.B) + RES_8BIT (7, cpustate->b.B) break; case 0xB9: /* RES 7,C */ - RES_8BIT (7, Regs.b.C) + RES_8BIT (7, cpustate->b.C) break; case 0xBA: /* RES 7,D */ - RES_8BIT (7, Regs.b.D) + RES_8BIT (7, cpustate->b.D) break; case 0xBB: /* RES 7,E */ - RES_8BIT (7, Regs.b.E) + RES_8BIT (7, cpustate->b.E) break; case 0xBC: /* RES 7,H */ - RES_8BIT (7, Regs.b.H) + RES_8BIT (7, cpustate->b.H) break; case 0xBD: /* RES 7,L */ - RES_8BIT (7, Regs.b.L) + RES_8BIT (7, cpustate->b.L) break; case 0xBE: /* RES 7,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); RES_8BIT (7, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xBF: /* RES 7,A */ - RES_8BIT (7, Regs.b.A) + RES_8BIT (7, cpustate->b.A) break; case 0xC0: /* SET 0,B */ - SET_8BIT (0, Regs.b.B) + SET_8BIT (0, cpustate->b.B) break; case 0xC1: /* SET 0,C */ - SET_8BIT (0, Regs.b.C) + SET_8BIT (0, cpustate->b.C) break; case 0xC2: /* SET 0,D */ - SET_8BIT (0, Regs.b.D) + SET_8BIT (0, cpustate->b.D) break; case 0xC3: /* SET 0,E */ - SET_8BIT (0, Regs.b.E) + SET_8BIT (0, cpustate->b.E) break; case 0xC4: /* SET 0,H */ - SET_8BIT (0, Regs.b.H) + SET_8BIT (0, cpustate->b.H) break; case 0xC5: /* SET 0,L */ - SET_8BIT (0, Regs.b.L) + SET_8BIT (0, cpustate->b.L) break; case 0xC6: /* SET 0,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (0, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xC7: /* SET 0,A */ - SET_8BIT (0, Regs.b.A) + SET_8BIT (0, cpustate->b.A) break; case 0xC8: /* SET 1,B */ - SET_8BIT (1, Regs.b.B) + SET_8BIT (1, cpustate->b.B) break; case 0xC9: /* SET 1,C */ - SET_8BIT (1, Regs.b.C) + SET_8BIT (1, cpustate->b.C) break; case 0xCA: /* SET 1,D */ - SET_8BIT (1, Regs.b.D) + SET_8BIT (1, cpustate->b.D) break; case 0xCB: /* SET 1,E */ - SET_8BIT (1, Regs.b.E) + SET_8BIT (1, cpustate->b.E) break; case 0xCC: /* SET 1,H */ - SET_8BIT (1, Regs.b.H) + SET_8BIT (1, cpustate->b.H) break; case 0xCD: /* SET 1,L */ - SET_8BIT (1, Regs.b.L) + SET_8BIT (1, cpustate->b.L) break; case 0xCE: /* SET 1,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (1, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xCF: /* SET 1,A */ - SET_8BIT (1, Regs.b.A) + SET_8BIT (1, cpustate->b.A) break; case 0xD0: /* SET 2,B */ - SET_8BIT (2, Regs.b.B) + SET_8BIT (2, cpustate->b.B) break; case 0xD1: /* SET 2,C */ - SET_8BIT (2, Regs.b.C) + SET_8BIT (2, cpustate->b.C) break; case 0xD2: /* SET 2,D */ - SET_8BIT (2, Regs.b.D) + SET_8BIT (2, cpustate->b.D) break; case 0xD3: /* SET 2,E */ - SET_8BIT (2, Regs.b.E) + SET_8BIT (2, cpustate->b.E) break; case 0xD4: /* SET 2,H */ - SET_8BIT (2, Regs.b.H) + SET_8BIT (2, cpustate->b.H) break; case 0xD5: /* SET 2,L */ - SET_8BIT (2, Regs.b.L) + SET_8BIT (2, cpustate->b.L) break; case 0xD6: /* SET 2,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (2, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xD7: /* SET 2,A */ - SET_8BIT (2, Regs.b.A) + SET_8BIT (2, cpustate->b.A) break; case 0xD8: /* SET 3,B */ - SET_8BIT (3, Regs.b.B) + SET_8BIT (3, cpustate->b.B) break; case 0xD9: /* SET 3,C */ - SET_8BIT (3, Regs.b.C) + SET_8BIT (3, cpustate->b.C) break; case 0xDA: /* SET 3,D */ - SET_8BIT (3, Regs.b.D) + SET_8BIT (3, cpustate->b.D) break; case 0xDB: /* SET 3,E */ - SET_8BIT (3, Regs.b.E) + SET_8BIT (3, cpustate->b.E) break; case 0xDC: /* SET 3,H */ - SET_8BIT (3, Regs.b.H) + SET_8BIT (3, cpustate->b.H) break; case 0xDD: /* SET 3,L */ - SET_8BIT (3, Regs.b.L) + SET_8BIT (3, cpustate->b.L) break; case 0xDE: /* SET 3,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (3, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xDF: /* SET 3,A */ - SET_8BIT (3, Regs.b.A) + SET_8BIT (3, cpustate->b.A) break; case 0xE0: /* SET 4,B */ - SET_8BIT (4, Regs.b.B) + SET_8BIT (4, cpustate->b.B) break; case 0xE1: /* SET 4,C */ - SET_8BIT (4, Regs.b.C) + SET_8BIT (4, cpustate->b.C) break; case 0xE2: /* SET 4,D */ - SET_8BIT (4, Regs.b.D) + SET_8BIT (4, cpustate->b.D) break; case 0xE3: /* SET 4,E */ - SET_8BIT (4, Regs.b.E) + SET_8BIT (4, cpustate->b.E) break; case 0xE4: /* SET 4,H */ - SET_8BIT (4, Regs.b.H) + SET_8BIT (4, cpustate->b.H) break; case 0xE5: /* SET 4,L */ - SET_8BIT (4, Regs.b.L) + SET_8BIT (4, cpustate->b.L) break; case 0xE6: /* SET 4,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (4, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xE7: /* SET 4,A */ - SET_8BIT (4, Regs.b.A) + SET_8BIT (4, cpustate->b.A) break; case 0xE8: /* SET 5,B */ - SET_8BIT (5, Regs.b.B) + SET_8BIT (5, cpustate->b.B) break; case 0xE9: /* SET 5,C */ - SET_8BIT (5, Regs.b.C) + SET_8BIT (5, cpustate->b.C) break; case 0xEA: /* SET 5,D */ - SET_8BIT (5, Regs.b.D) + SET_8BIT (5, cpustate->b.D) break; case 0xEB: /* SET 5,E */ - SET_8BIT (5, Regs.b.E) + SET_8BIT (5, cpustate->b.E) break; case 0xEC: /* SET 5,H */ - SET_8BIT (5, Regs.b.H) + SET_8BIT (5, cpustate->b.H) break; case 0xED: /* SET 5,L */ - SET_8BIT (5, Regs.b.L) + SET_8BIT (5, cpustate->b.L) break; case 0xEE: /* SET 5,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (5, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xEF: /* SET 5,A */ - SET_8BIT (5, Regs.b.A) + SET_8BIT (5, cpustate->b.A) break; case 0xF0: /* SET 6,B */ - SET_8BIT (6, Regs.b.B) + SET_8BIT (6, cpustate->b.B) break; case 0xF1: /* SET 6,C */ - SET_8BIT (6, Regs.b.C) + SET_8BIT (6, cpustate->b.C) break; case 0xF2: /* SET 6,D */ - SET_8BIT (6, Regs.b.D) + SET_8BIT (6, cpustate->b.D) break; case 0xF3: /* SET 6,E */ - SET_8BIT (6, Regs.b.E) + SET_8BIT (6, cpustate->b.E) break; case 0xF4: /* SET 6,H */ - SET_8BIT (6, Regs.b.H) + SET_8BIT (6, cpustate->b.H) break; case 0xF5: /* SET 6,L */ - SET_8BIT (6, Regs.b.L) + SET_8BIT (6, cpustate->b.L) break; case 0xF6: /* SET 6,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (6, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xF7: /* SET 6,A */ - SET_8BIT (6, Regs.b.A) + SET_8BIT (6, cpustate->b.A) break; case 0xF8: /* SET 7,B */ - SET_8BIT (7, Regs.b.B) + SET_8BIT (7, cpustate->b.B) break; case 0xF9: /* SET 7,C */ - SET_8BIT (7, Regs.b.C) + SET_8BIT (7, cpustate->b.C) break; case 0xFA: /* SET 7,D */ - SET_8BIT (7, Regs.b.D) + SET_8BIT (7, cpustate->b.D) break; case 0xFB: /* SET 7,E */ - SET_8BIT (7, Regs.b.E) + SET_8BIT (7, cpustate->b.E) break; case 0xFC: /* SET 7,H */ - SET_8BIT (7, Regs.b.H) + SET_8BIT (7, cpustate->b.H) break; case 0xFD: /* SET 7,L */ - SET_8BIT (7, Regs.b.L) + SET_8BIT (7, cpustate->b.L) break; case 0xFE: /* SET 7,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SET_8BIT (7, x) - mem_WriteByte (Regs.w.HL, x); + mem_WriteByte (cpustate, cpustate->w.HL, x); break; case 0xFF: /* SET 7,A */ - SET_8BIT (7, Regs.b.A) + SET_8BIT (7, cpustate->b.A) break; diff --git a/src/emu/cpu/lr35902/opc_main.h b/src/emu/cpu/lr35902/opc_main.h index 5a00ca4ef8f..28a1885be21 100644 --- a/src/emu/cpu/lr35902/opc_main.h +++ b/src/emu/cpu/lr35902/opc_main.h @@ -3,10 +3,10 @@ register UINT8 r,f; \ x++; \ r=(x); \ - f=(UINT8)(Regs.b.F&FLAG_C); \ + f=(UINT8)(cpustate->b.F&FLAG_C); \ if( r==0 ) f|=FLAG_Z; \ if( (r&0xF)==0 ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define DEC_8BIT(x) \ @@ -14,51 +14,51 @@ register UINT8 r,f; \ x--; \ r=(x); \ - f=(UINT8)((Regs.b.F&FLAG_C)|FLAG_N); \ + f=(UINT8)((cpustate->b.F&FLAG_C)|FLAG_N); \ if( r==0 ) f|=FLAG_Z; \ if( (r&0xF)==0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define ADD_HL_RR(x) \ { \ register UINT32 r1,r2; \ register UINT8 f; \ - r1=Regs.w.HL+(x); \ - r2=(Regs.w.HL&0xFFF)+((x)&0xFFF); \ - f=(UINT8)(Regs.b.F&FLAG_Z); \ + r1=cpustate->w.HL+(x); \ + r2=(cpustate->w.HL&0xFFF)+((x)&0xFFF); \ + f=(UINT8)(cpustate->b.F&FLAG_Z); \ if( r1>0xFFFF ) f|=FLAG_C; \ if( r2>0x0FFF ) f|=FLAG_H; \ - Regs.w.HL=(UINT16)r1; \ - Regs.b.F=f; \ + cpustate->w.HL=(UINT16)r1; \ + cpustate->b.F=f; \ } #define ADD_A_X(x) \ { \ register UINT16 r1,r2; \ register UINT8 f; \ - r1=(UINT16)((Regs.b.A&0xF)+((x)&0xF)); \ - r2=(UINT16)(Regs.b.A+(x)); \ - Regs.b.A=(UINT8)r2; \ + r1=(UINT16)((cpustate->b.A&0xF)+((x)&0xF)); \ + r2=(UINT16)(cpustate->b.A+(x)); \ + cpustate->b.A=(UINT8)r2; \ if( ((UINT8)r2)==0 ) f=FLAG_Z; \ else f=0; \ if( r2>0xFF ) f|=FLAG_C; \ if( r1>0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define SUB_A_X(x) \ { \ register UINT16 r1,r2; \ register UINT8 f; \ - r1=(UINT16)((Regs.b.A&0xF)-((x)&0xF)); \ - r2=(UINT16)(Regs.b.A-(x)); \ - Regs.b.A=(UINT8)r2; \ + r1=(UINT16)((cpustate->b.A&0xF)-((x)&0xF)); \ + r2=(UINT16)(cpustate->b.A-(x)); \ + cpustate->b.A=(UINT8)r2; \ if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \ else f=FLAG_N; \ if( r2>0xFF ) f|=FLAG_C; \ if( r1>0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } /* @@ -66,15 +66,15 @@ { \ register UINT16 r; \ register UINT8 f; \ - r=(UINT16)(Regs.b.A-(x)); \ + r=(UINT16)(cpustate->b.A-(x)); \ if( ((UINT8)r)==0 ) \ f=FLAG_N|FLAG_Z; \ else \ f=FLAG_N; \ f|=(UINT8)((r>>8)&FLAG_C); \ - if( (r^Regs.b.A^(x))&0x10 ) \ + if( (r^cpustate->b.A^(x))&0x10 ) \ f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } */ @@ -82,423 +82,423 @@ { \ register UINT16 r1,r2; \ register UINT8 f; \ - r1=(UINT16)((Regs.b.A&0xF)-((x)&0xF)); \ - r2=(UINT16)(Regs.b.A-(x)); \ + r1=(UINT16)((cpustate->b.A&0xF)-((x)&0xF)); \ + r2=(UINT16)(cpustate->b.A-(x)); \ if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \ else f=FLAG_N; \ if( r2>0xFF ) f|=FLAG_C; \ if( r1>0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define SBC_A_X(x) \ { \ register UINT16 r1,r2; \ register UINT8 f; \ - r1=(UINT16)((Regs.b.A&0xF)-((x)&0xF)-((Regs.b.F&FLAG_C)?1:0)); \ - r2=(UINT16)(Regs.b.A-(x)-((Regs.b.F&FLAG_C)?1:0)); \ - Regs.b.A=(UINT8)r2; \ + r1=(UINT16)((cpustate->b.A&0xF)-((x)&0xF)-((cpustate->b.F&FLAG_C)?1:0)); \ + r2=(UINT16)(cpustate->b.A-(x)-((cpustate->b.F&FLAG_C)?1:0)); \ + cpustate->b.A=(UINT8)r2; \ if( ((UINT8)r2)==0 ) f=FLAG_N|FLAG_Z; \ else f=FLAG_N; \ if( r2>0xFF ) f|=FLAG_C; \ if( r1>0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define ADC_A_X(x) \ { \ register UINT16 r1,r2; \ register UINT8 f; \ - r1=(UINT16)((Regs.b.A&0xF)+((x)&0xF)+((Regs.b.F&FLAG_C)?1:0)); \ - r2=(UINT16)(Regs.b.A+(x)+((Regs.b.F&FLAG_C)?1:0)); \ - if( (Regs.b.A=(UINT8)r2)==0 ) f=FLAG_Z; \ + r1=(UINT16)((cpustate->b.A&0xF)+((x)&0xF)+((cpustate->b.F&FLAG_C)?1:0)); \ + r2=(UINT16)(cpustate->b.A+(x)+((cpustate->b.F&FLAG_C)?1:0)); \ + if( (cpustate->b.A=(UINT8)r2)==0 ) f=FLAG_Z; \ else f=0; \ if( r2>0xFF ) f|=FLAG_C; \ if( r1>0xF ) f|=FLAG_H; \ - Regs.b.F=f; \ + cpustate->b.F=f; \ } #define AND_A_X(x) \ - if( (Regs.b.A&=(x))==0 ) \ - Regs.b.F=FLAG_H|FLAG_Z; \ + if( (cpustate->b.A&=(x))==0 ) \ + cpustate->b.F=FLAG_H|FLAG_Z; \ else \ - Regs.b.F=FLAG_H; + cpustate->b.F=FLAG_H; #define XOR_A_X(x) \ - if( (Regs.b.A^=(x))==0 ) \ - Regs.b.F=FLAG_Z; \ + if( (cpustate->b.A^=(x))==0 ) \ + cpustate->b.F=FLAG_Z; \ else \ - Regs.b.F=0; + cpustate->b.F=0; #define OR_A_X(x) \ - if( (Regs.b.A|=(x))==0 ) \ - Regs.b.F=FLAG_Z; \ + if( (cpustate->b.A|=(x))==0 ) \ + cpustate->b.F=FLAG_Z; \ else \ - Regs.b.F=0; + cpustate->b.F=0; case 0x00: /* NOP */ break; case 0x01: /* LD BC,n16 */ - Regs.w.BC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + cpustate->w.BC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; break; case 0x02: /* LD (BC),A */ - mem_WriteByte (Regs.w.BC, Regs.b.A); + mem_WriteByte (cpustate, cpustate->w.BC, cpustate->b.A); break; case 0x03: /* INC BC */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.B == 0xFE) + if (cpustate->b.B == 0xFE) { trash_sprites (state); } #endif - Regs.w.BC += 1; + cpustate->w.BC += 1; break; case 0x04: /* INC B */ - INC_8BIT (Regs.b.B) + INC_8BIT (cpustate->b.B) break; case 0x05: /* DEC B */ - DEC_8BIT (Regs.b.B) + DEC_8BIT (cpustate->b.B) break; case 0x06: /* LD B,n8 */ - Regs.b.B = mem_ReadByte (Regs.w.PC++); + cpustate->b.B = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x07: /* RLCA */ - Regs.b.A = (UINT8) ((Regs.b.A << 1) | (Regs.b.A >> 7)); - if (Regs.b.A & 1) + cpustate->b.A = (UINT8) ((cpustate->b.A << 1) | (cpustate->b.A >> 7)); + if (cpustate->b.A & 1) { - Regs.b.F = FLAG_C; + cpustate->b.F = FLAG_C; } else { - Regs.b.F = 0; + cpustate->b.F = 0; } break; case 0x08: /* LD (n16),SP */ - mem_WriteWord (mem_ReadWord (Regs.w.PC), Regs.w.SP); - Regs.w.PC += 2; + mem_WriteWord (cpustate, mem_ReadWord (cpustate, cpustate->w.PC), cpustate->w.SP); + cpustate->w.PC += 2; break; case 0x09: /* ADD HL,BC */ - ADD_HL_RR (Regs.w.BC) + ADD_HL_RR (cpustate->w.BC) break; case 0x0A: /* LD A,(BC) */ - Regs.b.A = mem_ReadByte (Regs.w.BC); + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.BC); break; case 0x0B: /* DEC BC */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.B == 0xFE) + if (cpustate->b.B == 0xFE) { trash_sprites (state); } #endif - Regs.w.BC -= 1; + cpustate->w.BC -= 1; break; case 0x0C: /* INC C */ - INC_8BIT (Regs.b.C) + INC_8BIT (cpustate->b.C) break; case 0x0D: /* DEC C */ - DEC_8BIT (Regs.b.C) + DEC_8BIT (cpustate->b.C) break; case 0x0E: /* LD C,n8 */ - Regs.b.C = mem_ReadByte (Regs.w.PC++); + cpustate->b.C = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x0F: /* RRCA */ - Regs.b.A = (UINT8) ((Regs.b.A >> 1) | (Regs.b.A << 7)); - Regs.b.F = 0; - if (Regs.b.A & 0x80) + cpustate->b.A = (UINT8) ((cpustate->b.A >> 1) | (cpustate->b.A << 7)); + cpustate->b.F = 0; + if (cpustate->b.A & 0x80) { - Regs.b.F |= FLAG_C; + cpustate->b.F |= FLAG_C; } break; case 0x10: /* STOP */ - if ( Regs.w.gb_speed_change_pending ) { - Regs.w.gb_speed = ( Regs.w.gb_speed == 1 ) ? 2 : 1; + if ( cpustate->w.gb_speed_change_pending ) { + cpustate->w.gb_speed = ( cpustate->w.gb_speed == 1 ) ? 2 : 1; } - Regs.w.gb_speed_change_pending = 0; + cpustate->w.gb_speed_change_pending = 0; break; case 0x11: /* LD DE,n16 */ - Regs.w.DE = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + cpustate->w.DE = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; break; case 0x12: /* LD (DE),A */ - mem_WriteByte (Regs.w.DE, Regs.b.A); + mem_WriteByte (cpustate, cpustate->w.DE, cpustate->b.A); break; case 0x13: /* INC DE */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.D == 0xFE) + if (cpustate->b.D == 0xFE) { trash_sprites (state); } #endif - Regs.w.DE += 1; + cpustate->w.DE += 1; break; case 0x14: /* INC D */ - INC_8BIT (Regs.b.D) + INC_8BIT (cpustate->b.D) break; case 0x15: /* DEC D */ - DEC_8BIT (Regs.b.D) + DEC_8BIT (cpustate->b.D) break; case 0x16: /* LD D,n8 */ - Regs.b.D = mem_ReadByte (Regs.w.PC++); + cpustate->b.D = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x17: /* RLA */ - x = (Regs.b.A & 0x80) ? FLAG_C : 0; + x = (cpustate->b.A & 0x80) ? FLAG_C : 0; - Regs.b.A = (UINT8) ((Regs.b.A << 1) | ((Regs.b.F & FLAG_C) ? 1 : 0)); - Regs.b.F = x; + cpustate->b.A = (UINT8) ((cpustate->b.A << 1) | ((cpustate->b.F & FLAG_C) ? 1 : 0)); + cpustate->b.F = x; break; case 0x18: /* JR n8 */ { INT8 offset; - offset = mem_ReadByte (Regs.w.PC++); - Regs.w.PC += offset; + offset = mem_ReadByte (cpustate, cpustate->w.PC++); + cpustate->w.PC += offset; } break; case 0x19: /* ADD HL,DE */ - ADD_HL_RR (Regs.w.DE) + ADD_HL_RR (cpustate->w.DE) break; case 0x1A: /* LD A,(DE) */ - Regs.b.A = mem_ReadByte (Regs.w.DE); + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.DE); break; case 0x1B: /* DEC DE */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.D == 0xFE) + if (cpustate->b.D == 0xFE) { trash_sprites (state); } #endif - Regs.w.DE -= 1; + cpustate->w.DE -= 1; break; case 0x1C: /* INC E */ - INC_8BIT (Regs.b.E) + INC_8BIT (cpustate->b.E) break; case 0x1D: /* DEC E */ - DEC_8BIT (Regs.b.E) + DEC_8BIT (cpustate->b.E) break; case 0x1E: /* LD E,n8 */ - Regs.b.E = mem_ReadByte (Regs.w.PC++); + cpustate->b.E = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x1F: /* RRA */ - x = (Regs.b.A & 1) ? FLAG_C : 0; + x = (cpustate->b.A & 1) ? FLAG_C : 0; - Regs.b.A = (UINT8) ((Regs.b.A >> 1) | ((Regs.b.F & FLAG_C) ? 0x80 : 0)); - Regs.b.F = x; + cpustate->b.A = (UINT8) ((cpustate->b.A >> 1) | ((cpustate->b.F & FLAG_C) ? 0x80 : 0)); + cpustate->b.F = x; break; case 0x20: /* JR NZ,n8 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { - Regs.w.PC++; + cpustate->w.PC++; } else { INT8 offset; - offset = mem_ReadByte (Regs.w.PC++); - Regs.w.PC += offset; + offset = mem_ReadByte (cpustate, cpustate->w.PC++); + cpustate->w.PC += offset; CYCLES_PASSED( 4 ); } break; case 0x21: /* LD HL,n16 */ - Regs.w.HL = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + cpustate->w.HL = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; break; case 0x22: /* LD (HL+),A */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - mem_WriteByte (Regs.w.HL, Regs.b.A); - Regs.w.HL += 1; + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.A); + cpustate->w.HL += 1; break; case 0x23: /* INC HL */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - Regs.w.HL += 1; + cpustate->w.HL += 1; break; case 0x24: /* INC H */ - INC_8BIT (Regs.b.H); + INC_8BIT (cpustate->b.H); break; case 0x25: /* DEC H */ - DEC_8BIT (Regs.b.H); + DEC_8BIT (cpustate->b.H); break; case 0x26: /* LD H,n8 */ - Regs.b.H = mem_ReadByte (Regs.w.PC++); + cpustate->b.H = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x27: /* DAA */ { - int tmp = Regs.b.A; + int tmp = cpustate->b.A; - if ( ! ( Regs.b.F & FLAG_N ) ) { - if ( ( Regs.b.F & FLAG_H ) || ( tmp & 0x0F ) > 9 ) + if ( ! ( cpustate->b.F & FLAG_N ) ) { + if ( ( cpustate->b.F & FLAG_H ) || ( tmp & 0x0F ) > 9 ) tmp += 6; - if ( ( Regs.b.F & FLAG_C ) || tmp > 0x9F ) + if ( ( cpustate->b.F & FLAG_C ) || tmp > 0x9F ) tmp += 0x60; } else { - if ( Regs.b.F & FLAG_H ) { + if ( cpustate->b.F & FLAG_H ) { tmp -= 6; - if ( ! ( Regs.b.F & FLAG_C ) ) + if ( ! ( cpustate->b.F & FLAG_C ) ) tmp &= 0xFF; } - if ( Regs.b.F & FLAG_C ) + if ( cpustate->b.F & FLAG_C ) tmp -= 0x60; } - Regs.b.F &= ~ ( FLAG_H | FLAG_Z ); + cpustate->b.F &= ~ ( FLAG_H | FLAG_Z ); if ( tmp & 0x100 ) - Regs.b.F |= FLAG_C; - Regs.b.A = tmp & 0xFF; - if ( ! Regs.b.A ) - Regs.b.F |= FLAG_Z; + cpustate->b.F |= FLAG_C; + cpustate->b.A = tmp & 0xFF; + if ( ! cpustate->b.A ) + cpustate->b.F |= FLAG_Z; } break; case 0x28: /* JR Z,n8 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { INT8 offset; - offset = mem_ReadByte (Regs.w.PC++); - Regs.w.PC += offset; + offset = mem_ReadByte (cpustate, cpustate->w.PC++); + cpustate->w.PC += offset; CYCLES_PASSED( 4 ); } else { - Regs.w.PC += 1; + cpustate->w.PC += 1; } break; case 0x29: /* ADD HL,HL */ - ADD_HL_RR (Regs.w.HL) + ADD_HL_RR (cpustate->w.HL) break; case 0x2A: /* LD A,(HL+) */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - Regs.b.A = mem_ReadByte (Regs.w.HL); - Regs.w.HL += 1; + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.HL); + cpustate->w.HL += 1; break; case 0x2B: /* DEC HL */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - Regs.w.HL -= 1; + cpustate->w.HL -= 1; break; case 0x2C: /* INC L */ - INC_8BIT (Regs.b.L); + INC_8BIT (cpustate->b.L); break; case 0x2D: /* DEC L */ - DEC_8BIT (Regs.b.L); + DEC_8BIT (cpustate->b.L); break; case 0x2E: /* LD L,n8 */ - Regs.b.L = mem_ReadByte (Regs.w.PC++); + cpustate->b.L = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x2F: /* CPL */ - Regs.b.A = ~Regs.b.A; - Regs.b.F |= FLAG_N | FLAG_H; + cpustate->b.A = ~cpustate->b.A; + cpustate->b.F |= FLAG_N | FLAG_H; break; case 0x30: /* JR NC,n8 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { - Regs.w.PC += 1; + cpustate->w.PC += 1; } else { INT8 offset; - offset = mem_ReadByte (Regs.w.PC++); - Regs.w.PC += offset; + offset = mem_ReadByte (cpustate, cpustate->w.PC++); + cpustate->w.PC += offset; CYCLES_PASSED( 4 ); } break; case 0x31: /* LD SP,n16 */ - Regs.w.SP = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + cpustate->w.SP = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; break; case 0x32: /* LD (HL-),A */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - mem_WriteByte (Regs.w.HL, Regs.b.A); - Regs.w.HL -= 1; + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.A); + cpustate->w.HL -= 1; break; case 0x33: /* INC SP */ - Regs.w.SP += 1; + cpustate->w.SP += 1; break; case 0x34: /* INC (HL) */ { register UINT8 r, f; - f = (UINT8) (Regs.b.F & FLAG_C); - r = (UINT8) (mem_ReadByte (Regs.w.HL) + 1); - mem_WriteByte (Regs.w.HL, r); + f = (UINT8) (cpustate->b.F & FLAG_C); + r = (UINT8) (mem_ReadByte (cpustate, cpustate->w.HL) + 1); + mem_WriteByte (cpustate, cpustate->w.HL, r); if (r == 0) f |= FLAG_Z; @@ -506,7 +506,7 @@ case 0x34: /* INC (HL) */ if ((r & 0xF) == 0) f |= FLAG_H; - Regs.b.F = f; + cpustate->b.F = f; } break; case 0x35: /* DEC (HL) */ @@ -514,9 +514,9 @@ case 0x35: /* DEC (HL) */ { register UINT8 r, f; - f = (UINT8) ((Regs.b.F & FLAG_C) | FLAG_N); - r = (UINT8) (mem_ReadByte (Regs.w.HL) - 1); - mem_WriteByte (Regs.w.HL, r); + f = (UINT8) ((cpustate->b.F & FLAG_C) | FLAG_N); + r = (UINT8) (mem_ReadByte (cpustate, cpustate->w.HL) - 1); + mem_WriteByte (cpustate, cpustate->w.HL, r); if (r == 0) f |= FLAG_Z; @@ -524,679 +524,679 @@ case 0x35: /* DEC (HL) */ if ((r & 0xF) == 0xF) f |= FLAG_H; - Regs.b.F = f; + cpustate->b.F = f; } break; case 0x36: /* LD (HL),n8 */ /* FIXED / broken ? */ - mem_WriteByte (Regs.w.HL, mem_ReadByte (Regs.w.PC++)); + mem_WriteByte (cpustate, cpustate->w.HL, mem_ReadByte (cpustate, cpustate->w.PC++)); break; case 0x37: /* SCF */ - Regs.b.F = (UINT8) ((Regs.b.F & FLAG_Z) | FLAG_C); + cpustate->b.F = (UINT8) ((cpustate->b.F & FLAG_Z) | FLAG_C); break; case 0x38: /* JR C,n8 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { INT8 offset; - offset = mem_ReadByte (Regs.w.PC++); - Regs.w.PC += offset; + offset = mem_ReadByte (cpustate, cpustate->w.PC++); + cpustate->w.PC += offset; CYCLES_PASSED( 4 ); } else { - Regs.w.PC += 1; + cpustate->w.PC += 1; } break; case 0x39: /* ADD HL,SP */ - ADD_HL_RR (Regs.w.SP) + ADD_HL_RR (cpustate->w.SP) break; case 0x3A: /* LD A,(HL-) */ #if 0 /* FIXME ?? do we want to support this? (bug emulation) */ - if (Regs.b.H == 0xFE) + if (cpustate->b.H == 0xFE) { trash_sprites (state); } #endif - Regs.b.A = mem_ReadByte (Regs.w.HL); - Regs.w.HL -= 1; + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.HL); + cpustate->w.HL -= 1; break; case 0x3B: /* DEC SP */ - Regs.w.SP -= 1; + cpustate->w.SP -= 1; break; case 0x3C: /* INC A */ - INC_8BIT (Regs.b.A); + INC_8BIT (cpustate->b.A); break; case 0x3D: /* DEC A */ - DEC_8BIT (Regs.b.A); + DEC_8BIT (cpustate->b.A); break; case 0x3E: /* LD A,n8 */ - Regs.b.A = mem_ReadByte (Regs.w.PC++); + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.PC++); break; case 0x3F: /* CCF */ - Regs.b.F = (UINT8) ((Regs.b.F & FLAG_Z) | ((Regs.b.F & FLAG_C) ? 0 : FLAG_C)); + cpustate->b.F = (UINT8) ((cpustate->b.F & FLAG_Z) | ((cpustate->b.F & FLAG_C) ? 0 : FLAG_C)); break; case 0x40: /* LD B,B */ break; case 0x41: /* LD B,C */ - Regs.b.B = Regs.b.C; + cpustate->b.B = cpustate->b.C; break; case 0x42: /* LD B,D */ - Regs.b.B = Regs.b.D; + cpustate->b.B = cpustate->b.D; break; case 0x43: /* LD B,E */ - Regs.b.B = Regs.b.E; + cpustate->b.B = cpustate->b.E; break; case 0x44: /* LD B,H */ - Regs.b.B = Regs.b.H; + cpustate->b.B = cpustate->b.H; break; case 0x45: /* LD B,L */ - Regs.b.B = Regs.b.L; + cpustate->b.B = cpustate->b.L; break; case 0x46: /* LD B,(HL) */ - Regs.b.B = mem_ReadByte (Regs.w.HL); + cpustate->b.B = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x47: /* LD B,A */ - Regs.b.B = Regs.b.A; + cpustate->b.B = cpustate->b.A; break; case 0x48: /* LD C,B */ - Regs.b.C = Regs.b.B; + cpustate->b.C = cpustate->b.B; break; case 0x49: /* LD C,C */ break; case 0x4A: /* LD C,D */ - Regs.b.C = Regs.b.D; + cpustate->b.C = cpustate->b.D; break; case 0x4B: /* LD C,E */ - Regs.b.C = Regs.b.E; + cpustate->b.C = cpustate->b.E; break; case 0x4C: /* LD C,H */ - Regs.b.C = Regs.b.H; + cpustate->b.C = cpustate->b.H; break; case 0x4D: /* LD C,L */ - Regs.b.C = Regs.b.L; + cpustate->b.C = cpustate->b.L; break; case 0x4E: /* LD C,(HL) */ - Regs.b.C = mem_ReadByte (Regs.w.HL); + cpustate->b.C = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x4F: /* LD C,A */ - Regs.b.C = Regs.b.A; + cpustate->b.C = cpustate->b.A; break; case 0x50: /* LD D,B */ - Regs.b.D = Regs.b.B; + cpustate->b.D = cpustate->b.B; break; case 0x51: /* LD D,C */ - Regs.b.D = Regs.b.C; + cpustate->b.D = cpustate->b.C; break; case 0x52: /* LD D,D */ break; case 0x53: /* LD D,E */ - Regs.b.D = Regs.b.E; + cpustate->b.D = cpustate->b.E; break; case 0x54: /* LD D,H */ - Regs.b.D = Regs.b.H; + cpustate->b.D = cpustate->b.H; break; case 0x55: /* LD D,L */ - Regs.b.D = Regs.b.L; + cpustate->b.D = cpustate->b.L; break; case 0x56: /* LD D,(HL) */ - Regs.b.D = mem_ReadByte (Regs.w.HL); + cpustate->b.D = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x57: /* LD D,A */ - Regs.b.D = Regs.b.A; + cpustate->b.D = cpustate->b.A; break; case 0x58: /* LD E,B */ - Regs.b.E = Regs.b.B; + cpustate->b.E = cpustate->b.B; break; case 0x59: /* LD E,C */ - Regs.b.E = Regs.b.C; + cpustate->b.E = cpustate->b.C; break; case 0x5A: /* LD E,D */ - Regs.b.E = Regs.b.D; + cpustate->b.E = cpustate->b.D; break; case 0x5B: /* LD E,E */ break; case 0x5C: /* LD E,H */ - Regs.b.E = Regs.b.H; + cpustate->b.E = cpustate->b.H; break; case 0x5D: /* LD E,L */ - Regs.b.E = Regs.b.L; + cpustate->b.E = cpustate->b.L; break; case 0x5E: /* LD E,(HL) */ - Regs.b.E = mem_ReadByte (Regs.w.HL); + cpustate->b.E = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x5F: /* LD E,A */ - Regs.b.E = Regs.b.A; + cpustate->b.E = cpustate->b.A; break; case 0x60: /* LD H,B */ - Regs.b.H = Regs.b.B; + cpustate->b.H = cpustate->b.B; break; case 0x61: /* LD H,C */ - Regs.b.H = Regs.b.C; + cpustate->b.H = cpustate->b.C; break; case 0x62: /* LD H,D */ - Regs.b.H = Regs.b.D; + cpustate->b.H = cpustate->b.D; break; case 0x63: /* LD H,E */ - Regs.b.H = Regs.b.E; + cpustate->b.H = cpustate->b.E; break; case 0x64: /* LD H,H */ break; case 0x65: /* LD H,L */ - Regs.b.H = Regs.b.L; + cpustate->b.H = cpustate->b.L; break; case 0x66: /* LD H,(HL) */ - Regs.b.H = mem_ReadByte (Regs.w.HL); + cpustate->b.H = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x67: /* LD H,A */ - Regs.b.H = Regs.b.A; + cpustate->b.H = cpustate->b.A; break; case 0x68: /* LD L,B */ - Regs.b.L = Regs.b.B; + cpustate->b.L = cpustate->b.B; break; case 0x69: /* LD L,C */ - Regs.b.L = Regs.b.C; + cpustate->b.L = cpustate->b.C; break; case 0x6A: /* LD L,D */ - Regs.b.L = Regs.b.D; + cpustate->b.L = cpustate->b.D; break; case 0x6B: /* LD L,E */ - Regs.b.L = Regs.b.E; + cpustate->b.L = cpustate->b.E; break; case 0x6C: /* LD L,H */ - Regs.b.L = Regs.b.H; + cpustate->b.L = cpustate->b.H; break; case 0x6D: /* LD L,L */ break; case 0x6E: /* LD L,(HL) */ - Regs.b.L = mem_ReadByte (Regs.w.HL); + cpustate->b.L = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x6F: /* LD L,A */ - Regs.b.L = Regs.b.A; + cpustate->b.L = cpustate->b.A; break; case 0x70: /* LD (HL),B */ - mem_WriteByte (Regs.w.HL, Regs.b.B); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.B); break; case 0x71: /* LD (HL),C */ - mem_WriteByte (Regs.w.HL, Regs.b.C); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.C); break; case 0x72: /* LD (HL),D */ - mem_WriteByte (Regs.w.HL, Regs.b.D); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.D); break; case 0x73: /* LD (HL),E */ - mem_WriteByte (Regs.w.HL, Regs.b.E); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.E); break; case 0x74: /* LD (HL),H */ - mem_WriteByte (Regs.w.HL, Regs.b.H); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.H); break; case 0x75: /* LD (HL),L */ - mem_WriteByte (Regs.w.HL, Regs.b.L); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.L); break; case 0x76: /* HALT */ - Regs.w.enable |= HALTED; - Regs.w.haltIFstatus = Regs.w.IF & Regs.w.IE; - Regs.w.PC--; + cpustate->w.enable |= HALTED; + cpustate->w.haltIFstatus = cpustate->w.IF & cpustate->w.IE; + cpustate->w.PC--; break; case 0x77: /* LD (HL),A */ - mem_WriteByte (Regs.w.HL, Regs.b.A); + mem_WriteByte (cpustate, cpustate->w.HL, cpustate->b.A); break; case 0x78: /* LD A,B */ - Regs.b.A = Regs.b.B; + cpustate->b.A = cpustate->b.B; break; case 0x79: /* LD A,C */ - Regs.b.A = Regs.b.C; + cpustate->b.A = cpustate->b.C; break; case 0x7A: /* LD A,D */ - Regs.b.A = Regs.b.D; + cpustate->b.A = cpustate->b.D; break; case 0x7B: /* LD A,E */ - Regs.b.A = Regs.b.E; + cpustate->b.A = cpustate->b.E; break; case 0x7C: /* LD A,H */ - Regs.b.A = Regs.b.H; + cpustate->b.A = cpustate->b.H; break; case 0x7D: /* LD A,L */ - Regs.b.A = Regs.b.L; + cpustate->b.A = cpustate->b.L; break; case 0x7E: /* LD A,(HL) */ - Regs.b.A = mem_ReadByte (Regs.w.HL); + cpustate->b.A = mem_ReadByte (cpustate, cpustate->w.HL); break; case 0x7F: /* LD A,A */ break; case 0x80: /* ADD A,B */ - ADD_A_X (Regs.b.B) + ADD_A_X (cpustate->b.B) break; case 0x81: /* ADD A,C */ - ADD_A_X (Regs.b.C) + ADD_A_X (cpustate->b.C) break; case 0x82: /* ADD A,D */ - ADD_A_X (Regs.b.D) + ADD_A_X (cpustate->b.D) break; case 0x83: /* ADD A,E */ - ADD_A_X (Regs.b.E) + ADD_A_X (cpustate->b.E) break; case 0x84: /* ADD A,H */ - ADD_A_X (Regs.b.H) + ADD_A_X (cpustate->b.H) break; case 0x85: /* ADD A,L */ - ADD_A_X (Regs.b.L) + ADD_A_X (cpustate->b.L) break; case 0x86: /* ADD A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); ADD_A_X (x) break; case 0x87: /* ADD A,A */ - ADD_A_X (Regs.b.A) + ADD_A_X (cpustate->b.A) break; case 0x88: /* ADC A,B */ - ADC_A_X (Regs.b.B) + ADC_A_X (cpustate->b.B) break; case 0x89: /* ADC A,C */ - ADC_A_X (Regs.b.C) + ADC_A_X (cpustate->b.C) break; case 0x8A: /* ADC A,D */ - ADC_A_X (Regs.b.D) + ADC_A_X (cpustate->b.D) break; case 0x8B: /* ADC A,E */ - ADC_A_X (Regs.b.E) + ADC_A_X (cpustate->b.E) break; case 0x8C: /* ADC A,H */ - ADC_A_X (Regs.b.H) + ADC_A_X (cpustate->b.H) break; case 0x8D: /* ADC A,L */ - ADC_A_X (Regs.b.L) + ADC_A_X (cpustate->b.L) break; case 0x8E: /* ADC A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); ADC_A_X (x) break; case 0x8F: /* ADC A,A */ - ADC_A_X (Regs.b.A) + ADC_A_X (cpustate->b.A) break; case 0x90: /* SUB A,B */ - SUB_A_X (Regs.b.B) + SUB_A_X (cpustate->b.B) break; case 0x91: /* SUB A,C */ - SUB_A_X (Regs.b.C) + SUB_A_X (cpustate->b.C) break; case 0x92: /* SUB A,D */ - SUB_A_X (Regs.b.D) + SUB_A_X (cpustate->b.D) break; case 0x93: /* SUB A,E */ - SUB_A_X (Regs.b.E) + SUB_A_X (cpustate->b.E) break; case 0x94: /* SUB A,H */ - SUB_A_X (Regs.b.H) + SUB_A_X (cpustate->b.H) break; case 0x95: /* SUB A,L */ - SUB_A_X (Regs.b.L) + SUB_A_X (cpustate->b.L) break; case 0x96: /* SUB A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SUB_A_X (x) break; case 0x97: /* SUB A,A */ - SUB_A_X (Regs.b.A) + SUB_A_X (cpustate->b.A) break; case 0x98: /* SBC A,B */ - SBC_A_X (Regs.b.B) + SBC_A_X (cpustate->b.B) break; case 0x99: /* SBC A,C */ - SBC_A_X (Regs.b.C) + SBC_A_X (cpustate->b.C) break; case 0x9A: /* SBC A,D */ - SBC_A_X (Regs.b.D) + SBC_A_X (cpustate->b.D) break; case 0x9B: /* SBC A,E */ - SBC_A_X (Regs.b.E) + SBC_A_X (cpustate->b.E) break; case 0x9C: /* SBC A,H */ - SBC_A_X (Regs.b.H) + SBC_A_X (cpustate->b.H) break; case 0x9D: /* SBC A,L */ - SBC_A_X (Regs.b.L) + SBC_A_X (cpustate->b.L) break; case 0x9E: /* SBC A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); SBC_A_X (x) break; case 0x9F: /* SBC A,A */ - SBC_A_X (Regs.b.A) + SBC_A_X (cpustate->b.A) break; case 0xA0: /* AND A,B */ - AND_A_X (Regs.b.B) + AND_A_X (cpustate->b.B) break; case 0xA1: /* AND A,C */ - AND_A_X (Regs.b.C) + AND_A_X (cpustate->b.C) break; case 0xA2: /* AND A,D */ - AND_A_X (Regs.b.D) + AND_A_X (cpustate->b.D) break; case 0xA3: /* AND A,E */ - AND_A_X (Regs.b.E) + AND_A_X (cpustate->b.E) break; case 0xA4: /* AND A,H */ - AND_A_X (Regs.b.H) + AND_A_X (cpustate->b.H) break; case 0xA5: /* AND A,L */ - AND_A_X (Regs.b.L) + AND_A_X (cpustate->b.L) break; case 0xA6: /* AND A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); AND_A_X (x) break; case 0xA7: /* AND A,A */ - Regs.b.F = (Regs.b.A == 0) ? (FLAG_H | FLAG_Z) : FLAG_H; + cpustate->b.F = (cpustate->b.A == 0) ? (FLAG_H | FLAG_Z) : FLAG_H; break; case 0xA8: /* XOR A,B */ - XOR_A_X (Regs.b.B) + XOR_A_X (cpustate->b.B) break; case 0xA9: /* XOR A,C */ - XOR_A_X (Regs.b.C) + XOR_A_X (cpustate->b.C) break; case 0xAA: /* XOR A,D */ - XOR_A_X (Regs.b.D) + XOR_A_X (cpustate->b.D) break; case 0xAB: /* XOR A,E */ - XOR_A_X (Regs.b.E) + XOR_A_X (cpustate->b.E) break; case 0xAC: /* XOR A,H */ - XOR_A_X (Regs.b.H) + XOR_A_X (cpustate->b.H) break; case 0xAD: /* XOR A,L */ - XOR_A_X (Regs.b.L) + XOR_A_X (cpustate->b.L) break; case 0xAE: /* XOR A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); XOR_A_X (x) break; case 0xAF: /* XOR A,A */ - XOR_A_X (Regs.b.A) + XOR_A_X (cpustate->b.A) break; case 0xB0: /* OR A,B */ - OR_A_X (Regs.b.B) + OR_A_X (cpustate->b.B) break; case 0xB1: /* OR A,C */ - OR_A_X (Regs.b.C) + OR_A_X (cpustate->b.C) break; case 0xB2: /* OR A,D */ - OR_A_X (Regs.b.D) + OR_A_X (cpustate->b.D) break; case 0xB3: /* OR A,E */ - OR_A_X (Regs.b.E) + OR_A_X (cpustate->b.E) break; case 0xB4: /* OR A,H */ - OR_A_X (Regs.b.H) + OR_A_X (cpustate->b.H) break; case 0xB5: /* OR A,L */ - OR_A_X (Regs.b.L) + OR_A_X (cpustate->b.L) break; case 0xB6: /* OR A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); OR_A_X (x) break; case 0xB7: /* OR A,A */ - OR_A_X (Regs.b.A) + OR_A_X (cpustate->b.A) break; case 0xB8: /* CP A,B */ - CP_A_X (Regs.b.B) + CP_A_X (cpustate->b.B) break; case 0xB9: /* CP A,C */ - CP_A_X (Regs.b.C) + CP_A_X (cpustate->b.C) break; case 0xBA: /* CP A,D */ - CP_A_X (Regs.b.D) + CP_A_X (cpustate->b.D) break; case 0xBB: /* CP A,E */ - CP_A_X (Regs.b.E) + CP_A_X (cpustate->b.E) break; case 0xBC: /* CP A,H */ - CP_A_X (Regs.b.H) + CP_A_X (cpustate->b.H) break; case 0xBD: /* CP A,L */ - CP_A_X (Regs.b.L) + CP_A_X (cpustate->b.L) break; case 0xBE: /* CP A,(HL) */ - x = mem_ReadByte (Regs.w.HL); + x = mem_ReadByte (cpustate, cpustate->w.HL); CP_A_X (x) break; case 0xBF: /* CP A,A */ - CP_A_X (Regs.b.A) + CP_A_X (cpustate->b.A) break; case 0xC0: /* RET NZ */ - if (!(Regs.b.F & FLAG_Z)) + if (!(cpustate->b.F & FLAG_Z)) { - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; CYCLES_PASSED( 12 ); } break; case 0xC1: /* POP BC */ - Regs.w.BC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.BC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; break; case 0xC2: /* JP NZ,n16 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { - Regs.w.PC += 2; + cpustate->w.PC += 2; } else { - Regs.w.PC = mem_ReadWord (Regs.w.PC); + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); CYCLES_PASSED( 4 ); } break; case 0xC3: /* JP n16 */ - Regs.w.PC = mem_ReadWord (Regs.w.PC); + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); break; case 0xC4: /* CALL NZ,n16 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { - Regs.w.PC += 2; + cpustate->w.PC += 2; } else { register UINT16 PC; - PC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + PC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = PC; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = PC; CYCLES_PASSED( 12 ); } break; case 0xC5: /* PUSH BC */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.BC); + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.BC); break; case 0xC6: /* ADD A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); ADD_A_X (x) break; case 0xC7: /* RST 0 */ { register UINT16 PC; - PC = Regs.w.PC; - Regs.w.PC = 0; + PC = cpustate->w.PC; + cpustate->w.PC = 0; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, PC); + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, PC); } break; case 0xC8: /* RET Z */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; CYCLES_PASSED( 12 ); } break; case 0xC9: /* RET */ - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; break; case 0xCA: /* JP Z,n16 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { - Regs.w.PC = mem_ReadWord (Regs.w.PC); + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); CYCLES_PASSED( 4 ); } else { - Regs.w.PC += 2; + cpustate->w.PC += 2; } break; case 0xCB: /* PREFIX! */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); CYCLES_PASSED( CyclesCB[x] ); switch (x) { @@ -1205,67 +1205,67 @@ case 0xCB: /* PREFIX! */ break; case 0xCC: /* CALL Z,n16 */ - if (Regs.b.F & FLAG_Z) + if (cpustate->b.F & FLAG_Z) { register UINT16 PC; - PC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + PC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = PC; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = PC; CYCLES_PASSED( 12 ); } else { - Regs.w.PC += 2; + cpustate->w.PC += 2; } break; case 0xCD: /* CALL n16 */ { register UINT16 PC; - PC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + PC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = PC; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = PC; } break; case 0xCE: /* ADC A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); ADC_A_X (x) break; case 0xCF: /* RST 8 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 8; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 8; break; case 0xD0: /* RET NC */ - if (!(Regs.b.F & FLAG_C)) + if (!(cpustate->b.F & FLAG_C)) { - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; CYCLES_PASSED( 12 ); } break; case 0xD1: /* POP DE */ - Regs.w.DE = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.DE = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; break; case 0xD2: /* JP NC,n16 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { - Regs.w.PC += 2; + cpustate->w.PC += 2; } else { - Regs.w.PC = mem_ReadWord (Regs.w.PC); + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); CYCLES_PASSED( 4 ); } break; @@ -1273,109 +1273,109 @@ case 0xD3: /* EH? */ break; case 0xD4: /* CALL NC,n16 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { - Regs.w.PC += 2; + cpustate->w.PC += 2; } else { register UINT16 PC; - PC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + PC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = PC; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = PC; CYCLES_PASSED( 12 ); } break; case 0xD5: /* PUSH DE */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.DE); + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.DE); break; case 0xD6: /* SUB A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); SUB_A_X (x) break; case 0xD7: /* RST $10 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x10; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x10; break; case 0xD8: /* RET C */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; CYCLES_PASSED( 12 ); } break; case 0xD9: /* RETI */ - Regs.w.PC = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; - Regs.w.enable |= IME; + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; + cpustate->w.enable |= IME; break; case 0xDA: /* JP C,n16 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { - Regs.w.PC = mem_ReadWord (Regs.w.PC); + cpustate->w.PC = mem_ReadWord (cpustate, cpustate->w.PC); CYCLES_PASSED( 4 ); } else { - Regs.w.PC += 2; + cpustate->w.PC += 2; } break; case 0xDB: /* EH? */ break; case 0xDC: /* CALL C,n16 */ - if (Regs.b.F & FLAG_C) + if (cpustate->b.F & FLAG_C) { register UINT16 PC; - PC = mem_ReadWord (Regs.w.PC); - Regs.w.PC += 2; + PC = mem_ReadWord (cpustate, cpustate->w.PC); + cpustate->w.PC += 2; - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = PC; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = PC; CYCLES_PASSED( 12 ); } else { - Regs.w.PC += 2; + cpustate->w.PC += 2; } break; case 0xDD: /* EH? */ break; case 0xDE: /* SBC A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); SBC_A_X (x) break; case 0xDF: /* RST $18 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x18; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x18; break; case 0xE0: /* LD ($FF00+n8),A */ - mem_WriteByte (mem_ReadByte (Regs.w.PC++) + 0xFF00, Regs.b.A); + mem_WriteByte (cpustate, mem_ReadByte (cpustate, cpustate->w.PC++) + 0xFF00, cpustate->b.A); break; case 0xE1: /* POP HL */ - Regs.w.HL = mem_ReadWord (Regs.w.SP); - Regs.w.SP += 2; + cpustate->w.HL = mem_ReadWord (cpustate, cpustate->w.SP); + cpustate->w.SP += 2; break; case 0xE2: /* LD ($FF00+C),A */ - mem_WriteByte ((UINT16) (0xFF00 + Regs.b.C), Regs.b.A); + mem_WriteByte (cpustate, (UINT16) (0xFF00 + cpustate->b.C), cpustate->b.A); break; case 0xE3: /* EH? */ break; @@ -1383,19 +1383,19 @@ case 0xE4: /* EH? */ break; case 0xE5: /* PUSH HL */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.HL); + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.HL); break; case 0xE6: /* AND A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); AND_A_X (x) break; case 0xE7: /* RST $20 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x20; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x20; break; case 0xE8: /* ADD SP,n8 */ /* @@ -1408,33 +1408,33 @@ case 0xE8: /* ADD SP,n8 */ { register INT32 n; - n = (INT32) ((INT8) mem_ReadByte (Regs.w.PC++)); + n = (INT32) ((INT8) mem_ReadByte (cpustate, cpustate->w.PC++)); - if ( ( Regs.w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) + if ( ( cpustate->w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) { - Regs.b.F = FLAG_C; + cpustate->b.F = FLAG_C; } else { - Regs.b.F = 0; + cpustate->b.F = 0; } - if ( ( Regs.w.SP & 0x0F ) + ( n & 0x0F ) > 0x0F ) + if ( ( cpustate->w.SP & 0x0F ) + ( n & 0x0F ) > 0x0F ) { - Regs.b.F |= FLAG_H; + cpustate->b.F |= FLAG_H; } - Regs.w.SP = (UINT16) ( Regs.w.SP + n ); + cpustate->w.SP = (UINT16) ( cpustate->w.SP + n ); } break; case 0xE9: /* JP (HL) */ - Regs.w.PC = Regs.w.HL; + cpustate->w.PC = cpustate->w.HL; break; case 0xEA: /* LD (n16),A */ - mem_WriteByte (mem_ReadWord (Regs.w.PC), Regs.b.A); - Regs.w.PC += 2; + mem_WriteByte (cpustate, mem_ReadWord (cpustate, cpustate->w.PC), cpustate->b.A); + cpustate->w.PC += 2; break; case 0xEB: /* EH? */ break; @@ -1444,49 +1444,49 @@ case 0xED: /* EH? */ break; case 0xEE: /* XOR A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); XOR_A_X (x) break; case 0xEF: /* RST $28 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x28; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x28; break; case 0xF0: /* LD A,($FF00+n8) */ - Regs.b.A = mem_ReadByte (0xFF00 + mem_ReadByte (Regs.w.PC++)); + cpustate->b.A = mem_ReadByte (cpustate, 0xFF00 + mem_ReadByte (cpustate, cpustate->w.PC++)); break; case 0xF1: /* POP AF */ - Regs.w.AF = (UINT16) (mem_ReadWord (Regs.w.SP) & 0xFFF0); - Regs.w.SP += 2; + cpustate->w.AF = (UINT16) (mem_ReadWord (cpustate, cpustate->w.SP) & 0xFFF0); + cpustate->w.SP += 2; break; case 0xF2: /* LD A,($FF00+C) */ - Regs.b.A = mem_ReadByte ((UINT16) (0xFF00 + Regs.b.C)); + cpustate->b.A = mem_ReadByte (cpustate, (UINT16) (0xFF00 + cpustate->b.C)); break; case 0xF3: /* DI */ - Regs.w.ei_delay = 0; - Regs.w.enable &= ~IME; + cpustate->w.ei_delay = 0; + cpustate->w.enable &= ~IME; break; case 0xF4: /* EH? */ break; case 0xF5: /* PUSH AF */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, (UINT16) (Regs.w.AF & 0xFFF0)); + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, (UINT16) (cpustate->w.AF & 0xFFF0)); break; case 0xF6: /* OR A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); OR_A_X (x) break; case 0xF7: /* RST $30 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x30; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x30; break; case 0xF8: /* LD HL,SP+n8 */ /* @@ -1502,38 +1502,38 @@ case 0xF8: /* LD HL,SP+n8 */ { register INT32 n; - n = (INT32) ((INT8) mem_ReadByte (Regs.w.PC++)); + n = (INT32) ((INT8) mem_ReadByte (cpustate, cpustate->w.PC++)); - if ( ( Regs.w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) + if ( ( cpustate->w.SP & 0xFF ) + (UINT8)(n & 0xFF) > 0xFF ) { - Regs.b.F = FLAG_C; + cpustate->b.F = FLAG_C; } else { - Regs.b.F = 0; + cpustate->b.F = 0; } - if ( ( Regs.w.SP & 0x0F ) + ( n & 0x0F ) > 0x0F ) + if ( ( cpustate->w.SP & 0x0F ) + ( n & 0x0F ) > 0x0F ) { - Regs.b.F |= FLAG_H; + cpustate->b.F |= FLAG_H; } - Regs.w.HL = (UINT16) ( Regs.w.SP + n ); + cpustate->w.HL = (UINT16) ( cpustate->w.SP + n ); } break; case 0xF9: /* LD SP,HL */ - Regs.w.SP = Regs.w.HL; + cpustate->w.SP = cpustate->w.HL; break; case 0xFA: /* LD A,(n16) */ - Regs.b.A = mem_ReadByte (mem_ReadWord (Regs.w.PC)); - Regs.w.PC += 2; + cpustate->b.A = mem_ReadByte (cpustate, mem_ReadWord (cpustate, cpustate->w.PC)); + cpustate->w.PC += 2; break; case 0xFB: /* EI */ - Regs.w.enable |= IME; - Regs.w.ei_delay = 1; + cpustate->w.enable |= IME; + cpustate->w.ei_delay = 1; break; case 0xFC: /* EH? */ break; @@ -1541,12 +1541,12 @@ case 0xFD: /* EH? */ break; case 0xFE: /* CP A,n8 */ - x = mem_ReadByte (Regs.w.PC++); + x = mem_ReadByte (cpustate, cpustate->w.PC++); CP_A_X (x) break; case 0xFF: /* RST $38 */ - Regs.w.SP -= 2; - mem_WriteWord (Regs.w.SP, Regs.w.PC); - Regs.w.PC = 0x38; + cpustate->w.SP -= 2; + mem_WriteWord (cpustate, cpustate->w.SP, cpustate->w.PC); + cpustate->w.PC = 0x38; break;