diff --git a/src/devices/bus/gio/newport.cpp b/src/devices/bus/gio/newport.cpp
index 94a88d6d37f..bd4ca1c7dbb 100644
--- a/src/devices/bus/gio/newport.cpp
+++ b/src/devices/bus/gio/newport.cpp
@@ -1186,7 +1186,7 @@ WRITE_LINE_MEMBER(newport_base_device::vblank_w)
 		if (BIT(m_vc2.m_display_ctrl, 0))
 		{
 			m_rex3.m_status |= 0x20;
-			m_gio->get_hpc3()->raise_local_irq(0, ioc2_device::INT3_LOCAL0_GRAPHICS);
+			m_gio->get_hpc3()->raise_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE);
 		}
 	}
 }
@@ -1609,7 +1609,7 @@ READ64_MEMBER(newport_base_device::rex3_r)
 			LOGMASKED(LOG_REX3, "REX3 Status Read: %08x\n", m_rex3.m_status);
 			uint32_t old_status = m_rex3.m_status;
 			m_rex3.m_status = 0;
-			m_gio->get_hpc3()->lower_local_irq(0, ioc2_device::INT3_LOCAL0_GRAPHICS);
+			m_gio->get_hpc3()->lower_local_irq(1, ioc2_device::INT3_LOCAL1_RETRACE);
 			ret |= (uint64_t)(old_status | 3) << 32;
 		}
 		if (ACCESSING_BITS_0_31)
@@ -1720,12 +1720,11 @@ bool newport_base_device::pixel_clip_pass(int16_t x, int16_t y)
 
 void newport_base_device::store_pixel(uint32_t *dest_buf, uint32_t src)
 {
-	const uint32_t fast_mask = BIT(m_rex3.m_draw_mode1, 17) ? m_rex3.m_write_mask : 0xffffffff;
+	const uint32_t fast_mask = m_rex3.m_write_mask;//BIT(m_rex3.m_draw_mode1, 17) ? 0xffffffff : m_rex3.m_write_mask;
 	const uint32_t write_mask = fast_mask & m_global_mask;
-	const uint32_t dst = *dest_buf;
+	const uint32_t dst = *dest_buf >> m_rex3.m_store_shift;
 	*dest_buf &= ~write_mask;
 
-
 	if (BIT(m_rex3.m_draw_mode1, 18)) // Blending
 	{
 		float sa = 0.0f;
@@ -1891,26 +1890,26 @@ void newport_base_device::store_pixel(uint32_t *dest_buf, uint32_t src)
 	}
 	else
 	{
-		src <<= m_rex3.m_store_shift;
+		//src <<= m_rex3.m_store_shift;
 
 		switch (m_rex3.m_logic_op)
 		{
 			case 0:                                                break;
-			case 1:     *dest_buf |= (src & dst) & write_mask;     break;
-			case 2:     *dest_buf |= (src & ~dst) & write_mask;    break;
-			case 3:     *dest_buf |= (src) & write_mask;           break;
-			case 4:     *dest_buf |= (~src & dst) & write_mask;    break;
-			case 5:     *dest_buf |= (dst) & write_mask;           break;
-			case 6:     *dest_buf |= (src ^ dst) & write_mask;     break;
-			case 7:     *dest_buf |= (src | dst) & write_mask;     break;
-			case 8:     *dest_buf |= ~(src | dst) & write_mask;    break;
-			case 9:     *dest_buf |= ~(src ^ dst) & write_mask;    break;
-			case 10:    *dest_buf |= ~(dst) & write_mask;          break;
-			case 11:    *dest_buf |= (src | ~dst) & write_mask;    break;
-			case 12:    *dest_buf |= ~(src) & write_mask;          break;
-			case 13:    *dest_buf |= (~src | dst) & write_mask;    break;
-			case 14:    *dest_buf |= ~(src & dst) & write_mask;    break;
-			case 15:    *dest_buf |= 0xffffff & write_mask;        break;
+			case 1:     *dest_buf |= ((src & dst) << m_rex3.m_store_shift) & write_mask;     break;
+			case 2:     *dest_buf |= ((src & ~dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 3:     *dest_buf |= ((src) << m_rex3.m_store_shift) & write_mask;           break;
+			case 4:     *dest_buf |= ((~src & dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 5:     *dest_buf |= ((dst) << m_rex3.m_store_shift) & write_mask;           break;
+			case 6:     *dest_buf |= ((src ^ dst) << m_rex3.m_store_shift) & write_mask;     break;
+			case 7:     *dest_buf |= ((src | dst) << m_rex3.m_store_shift) & write_mask;     break;
+			case 8:     *dest_buf |= (~(src | dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 9:     *dest_buf |= (~(src ^ dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 10:    *dest_buf |= (~(dst) << m_rex3.m_store_shift) & write_mask;          break;
+			case 11:    *dest_buf |= ((src | ~dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 12:    *dest_buf |= (~(src) << m_rex3.m_store_shift) & write_mask;          break;
+			case 13:    *dest_buf |= ((~src | dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 14:    *dest_buf |= (~(src & dst) << m_rex3.m_store_shift) & write_mask;    break;
+			case 15:    *dest_buf |= (0xffffff << m_rex3.m_store_shift) & write_mask;        break;
 		}
 	}
 }
@@ -2563,14 +2562,14 @@ void newport_base_device::do_rex3_command()
 						{
 							case 0: // 4bpp
 								color = m_rex3.m_color_vram & 0xf;
-								color |= color << 4;
+								//color |= color << 4;
 								break;
 							case 1: // 8bpp
 								color = m_rex3.m_color_vram & 0xff;
 								break;
 							case 2: // 12bpp
 								color = ((m_rex3.m_color_vram & 0xf00000) >> 12) | ((m_rex3.m_color_vram & 0xf000) >> 8) | ((m_rex3.m_color_vram & 0xf0) >> 4);
-								color |= color << 12;
+								//color |= color << 12;
 								break;
 							case 3: // 24bpp
 								color = m_rex3.m_color_vram & 0xffffff;
@@ -3493,9 +3492,9 @@ WRITE64_MEMBER(newport_base_device::rex3_w)
 		{
 			LOGMASKED(LOG_REX3, "REX3 Packed Color Fractions Write: %08x\n", (uint32_t)data);
 			m_rex3.m_color_i = (uint32_t)data;
-			m_rex3.m_color_red = ((m_rex3.m_color_i >> 0) & 0xff) << 11;
-			m_rex3.m_color_green = ((m_rex3.m_color_i >> 8) & 0xff) << 11;
-			m_rex3.m_color_blue = ((m_rex3.m_color_i >> 16) & 0xff) << 11;
+			//m_rex3.m_color_red = ((m_rex3.m_color_i >> 0) & 0xff) << 11;
+			//m_rex3.m_color_green = ((m_rex3.m_color_i >> 8) & 0xff) << 11;
+			//m_rex3.m_color_blue = ((m_rex3.m_color_i >> 16) & 0xff) << 11;
 		}
 		break;
 	case 0x0228/8:
diff --git a/src/devices/bus/gio/newport.h b/src/devices/bus/gio/newport.h
index efb95a83165..858afc517c7 100644
--- a/src/devices/bus/gio/newport.h
+++ b/src/devices/bus/gio/newport.h
@@ -200,10 +200,6 @@ protected:
 	void write_pixel(int16_t x, int16_t y, uint32_t color);
 	void store_pixel(uint32_t *dest_buf, uint32_t src);
 
-	void decode_vt_line(uint32_t line, uint32_t line_seq_ptr);
-	void decode_vt_table();
-	void update_screen_size();
-
 	void iterate_shade();
 
 	virtual uint32_t get_cmap_revision() = 0;
@@ -228,7 +224,12 @@ protected:
 
 	void do_rex3_command();
 
+	void decode_vt_line(uint32_t line, uint32_t line_seq_ptr);
+	void decode_vt_table();
+	void update_screen_size();
+
 	required_device<screen_device> m_screen;
+
 	vc2_t  m_vc2;
 	xmap_t m_xmap0;
 	xmap_t m_xmap1;
diff --git a/src/devices/cpu/mips/r4000.cpp b/src/devices/cpu/mips/r4000.cpp
index 2d7193b795a..9c670092bf0 100644
--- a/src/devices/cpu/mips/r4000.cpp
+++ b/src/devices/cpu/mips/r4000.cpp
@@ -199,6 +199,7 @@ void r4000_base_device::device_reset()
 	m_cp0_timer_zero = total_cycles();
 
 	m_ll_active = false;
+	m_bus_error = false;
 
 	m_cp0[CP0_WatchLo] = 0;
 	m_cp0[CP0_WatchHi] = 0;
@@ -2988,12 +2989,23 @@ template <typename T, typename U> std::enable_if_t<std::is_convertible<U, std::f
 
 	// TODO: cache lookup
 
+	T value = 0;
 	switch (sizeof(T))
 	{
-	case 1: apply(T(space(0).read_byte(address))); break;
-	case 2: apply(T(space(0).read_word(address))); break;
-	case 4: apply(T(space(0).read_dword(address))); break;
-	case 8: apply(T(space(0).read_qword(address))); break;
+	case 1: value = T(space(0).read_byte(address)); break;
+	case 2: value = T(space(0).read_word(address)); break;
+	case 4: value = T(space(0).read_dword(address)); break;
+	case 8: value = T(space(0).read_qword(address)); break;
+	}
+
+	if (m_bus_error)
+	{
+		m_bus_error = false;
+		cpu_exception(EXCEPTION_DBE);
+	}
+	else
+	{
+		apply(value);
 	}
 
 	return true;
@@ -3121,7 +3133,17 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
 	{
 		if (t == UNCACHED)
 		{
-			apply(space(0).read_dword(address));
+			const u32 insn = space(0).read_dword(address);
+
+			if (m_bus_error)
+			{
+				m_bus_error = false;
+				cpu_exception(EXCEPTION_IBE);
+			}
+			else
+			{
+				apply(insn);
+			}
 
 			return true;
 		}
@@ -3153,7 +3175,19 @@ bool r4000_base_device::fetch(u64 address, std::function<void(u32)> &&apply)
 		apply(m_icache_data[cache_address >> 2]);
 	}
 	else
-		apply(space(0).read_dword(address));
+	{
+		const u32 insn = space(0).read_dword(address);
+
+		if (m_bus_error)
+		{
+			m_bus_error = false;
+			cpu_exception(EXCEPTION_IBE);
+		}
+		else
+		{
+			apply(insn);
+		}
+	}
 
 	return true;
 }
diff --git a/src/devices/cpu/mips/r4000.h b/src/devices/cpu/mips/r4000.h
index d0e78cf845a..a7751a4a8c4 100644
--- a/src/devices/cpu/mips/r4000.h
+++ b/src/devices/cpu/mips/r4000.h
@@ -42,6 +42,8 @@ public:
 			COMBINE_DATA(&m_cp0[CP0_Config]);
 	}
 
+	void bus_error() { m_bus_error = true; }
+
 protected:
 	enum cache_size_t
 	{
@@ -401,6 +403,7 @@ protected:
 	u64 m_cp0_timer_zero;
 	emu_timer *m_cp0_timer;
 	bool m_ll_active;
+	bool m_bus_error;
 	struct tlb_entry_t
 	{
 		u64 mask;
diff --git a/src/mame/drivers/indy_indigo2.cpp b/src/mame/drivers/indy_indigo2.cpp
index 4b7a8599d4d..cd04d1499c1 100644
--- a/src/mame/drivers/indy_indigo2.cpp
+++ b/src/mame/drivers/indy_indigo2.cpp
@@ -96,6 +96,7 @@ protected:
 	virtual void machine_reset() override;
 
 	DECLARE_WRITE64_MEMBER(write_ram);
+	DECLARE_READ32_MEMBER(bus_error);
 
 	void ip22_map(address_map &map);
 	void ip22_base_map(address_map &map);
@@ -137,6 +138,12 @@ private:
 	required_device<wd33c93b_device> m_scsi_ctrl2;
 };
 
+READ32_MEMBER(ip22_state::bus_error)
+{
+	m_maincpu->bus_error();
+	return 0;
+}
+
 READ32_MEMBER(ip24_state::eisa_io_r)
 {
 	return 0xffffffff;
@@ -167,6 +174,7 @@ void ip22_state::ip22_base_map(address_map &map)
 	map(0x08000000, 0x0fffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram));     /* 128 MB of main RAM */
 	map(0x1f000000, 0x1f9fffff).rw(m_gio, FUNC(gio_device::read), FUNC(gio_device::write));
 	map(0x1fa00000, 0x1fa1ffff).rw(m_mem_ctrl, FUNC(sgi_mc_device::read), FUNC(sgi_mc_device::write));
+	map(0x1fb00000, 0x1fb7ffff).r(FUNC(ip22_state::bus_error));
 	map(0x1fb80000, 0x1fbfffff).m(m_hpc3, FUNC(hpc3_base_device::map));
 	map(0x1fc00000, 0x1fc7ffff).rom().region("user1", 0);
 	map(0x20000000, 0x27ffffff).share("mainram").ram().w(FUNC(ip22_state::write_ram));
diff --git a/src/mame/machine/hpc3.cpp b/src/mame/machine/hpc3.cpp
index 4c0c5053f4a..6f276f5f0f4 100644
--- a/src/mame/machine/hpc3.cpp
+++ b/src/mame/machine/hpc3.cpp
@@ -53,8 +53,6 @@ hpc3_base_device::hpc3_base_device(const machine_config &mconfig, device_type ty
 void hpc3_base_device::device_start()
 {
 	save_item(NAME(m_intstat));
-	save_item(NAME(m_enetr_nbdp));
-	save_item(NAME(m_enetr_cbp));
 	save_item(NAME(m_cpu_aux_ctrl));
 	save_item(NAME(m_pio_config));
 	save_item(NAME(m_volume_l));
@@ -75,6 +73,19 @@ void hpc3_base_device::device_start()
 		save_item(NAME(m_scsi_dma[i].m_active), i);
 	}
 
+	for (uint32_t i = 0; i < 2; i++)
+	{
+		save_item(NAME(m_enet_dma[i].m_cbp), i);
+		save_item(NAME(m_enet_dma[i].m_nbdp), i);
+		save_item(NAME(m_enet_dma[i].m_bc), i);
+		save_item(NAME(m_enet_dma[i].m_ctrl), i);
+		save_item(NAME(m_enet_dma[i].m_gio_fifo_ptr), i);
+		save_item(NAME(m_enet_dma[i].m_dev_fifo_ptr), i);
+	}
+	save_item(NAME(m_enet_reset));
+	save_item(NAME(m_enet_dmacfg));
+	save_item(NAME(m_enet_piocfg));
+
 	for (uint32_t i = 0; i < 8; i++)
 	{
 		save_item(NAME(m_pbus_dma[i].m_active), i);
@@ -89,15 +100,33 @@ void hpc3_base_device::device_start()
 		m_pbus_dma[i].m_timer = timer_alloc(TIMER_PBUS_DMA + i);
 		m_pbus_dma[i].m_timer->adjust(attotime::never);
 	}
+
+	m_pbus_fifo = make_unique_clear<uint32_t[]>(96);
+	m_scsi_fifo[0] = make_unique_clear<uint32_t[]>(96);
+	m_scsi_fifo[1] = make_unique_clear<uint32_t[]>(96);
+	m_enet_fifo[ENET_RECV] = make_unique_clear<uint32_t[]>(32);
+	m_enet_fifo[ENET_XMIT] = make_unique_clear<uint32_t[]>(40);
+
+	save_pointer(NAME(m_pbus_fifo), 96);
+	save_pointer(NAME(m_scsi_fifo[0]), 96);
+	save_pointer(NAME(m_scsi_fifo[1]), 96);
+	save_pointer(NAME(m_enet_fifo[ENET_RECV]), 32);
+	save_pointer(NAME(m_enet_fifo[ENET_XMIT]), 40);
 }
 
 void hpc3_base_device::device_reset()
 {
-	m_enetr_nbdp = 0x80000000;
-	m_enetr_cbp = 0x80000000;
 	m_cpu_aux_ctrl = 0;
 
 	memset(m_scsi_dma, 0, sizeof(scsi_dma_t) * 2);
+	memset(m_enet_dma, 0, sizeof(enet_dma_t) * 2);
+	m_enet_dmacfg = 0;
+	m_enet_piocfg = 0;
+
+	m_enet_dma[ENET_RECV].m_cbp = 0x80000000;
+	m_enet_dma[ENET_XMIT].m_cbp = 0x80000000;
+	m_enet_dma[ENET_RECV].m_nbdp = 0x80000000;
+	m_enet_dma[ENET_XMIT].m_nbdp = 0x80000000;
 
 	for (uint32_t i = 0; i < 8; i++)
 	{
@@ -157,6 +186,11 @@ void hpc3_base_device::map(address_map &map)
 {
 	map(0x00000000, 0x0000ffff).rw(FUNC(hpc3_base_device::pbusdma_r), FUNC(hpc3_base_device::pbusdma_w));
 	map(0x00010000, 0x0001ffff).rw(FUNC(hpc3_base_device::hd_enet_r), FUNC(hpc3_base_device::hd_enet_w));
+	map(0x00020000, 0x000202ff).rw(FUNC(hpc3_base_device::fifo_r<FIFO_PBUS>), FUNC(hpc3_base_device::fifo_w<FIFO_PBUS>)); // PBUS FIFO
+	map(0x00028000, 0x000282ff).rw(FUNC(hpc3_base_device::fifo_r<FIFO_SCSI0>), FUNC(hpc3_base_device::fifo_w<FIFO_SCSI0>)); // SCSI0 FIFO
+	map(0x0002a000, 0x0002a2ff).rw(FUNC(hpc3_base_device::fifo_r<FIFO_SCSI1>), FUNC(hpc3_base_device::fifo_w<FIFO_SCSI1>)); // SCSI1 FIFO
+	map(0x0002c000, 0x0002c0ff).rw(FUNC(hpc3_base_device::fifo_r<FIFO_ENET_RECV>), FUNC(hpc3_base_device::fifo_w<FIFO_ENET_RECV>)); // ENET Recv FIFO
+	map(0x0002e000, 0x0002e13f).rw(FUNC(hpc3_base_device::fifo_r<FIFO_ENET_XMIT>), FUNC(hpc3_base_device::fifo_w<FIFO_ENET_XMIT>)); // ENET Xmit FIFO
 	map(0x00030000, 0x00030003).r(FUNC(hpc3_base_device::intstat_r));
 	map(0x00030008, 0x0003000b).rw(FUNC(hpc3_base_device::eeprom_r), FUNC(hpc3_base_device::eeprom_w));
 	map(0x0003000c, 0x0003000f).r(FUNC(hpc3_base_device::intstat_r));
@@ -324,11 +358,50 @@ READ32_MEMBER(hpc3_base_device::hd_enet_r)
 		return m_scsi_dma[channel].m_piocfg;
 	}
 	case 0x4000/4:
-		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet CBP Read: %08x & %08x\n", machine().describe_context(), m_enetr_nbdp, mem_mask);
-		return m_enetr_cbp;
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Current Buffer Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_cbp);
+		return m_enet_dma[ENET_RECV].m_cbp;
 	case 0x4004/4:
-		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet NBDP Read: %08x & %08x\n", machine().describe_context(), m_enetr_nbdp, mem_mask);
-		return m_enetr_nbdp;
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Next Buffer Desc Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_nbdp);
+		return m_enet_dma[ENET_RECV].m_nbdp;
+	case 0x5000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Buffer Count Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_bc);
+		return m_enet_dma[ENET_RECV].m_bc;
+	case 0x5004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver DMA Control Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_ctrl);
+		return m_enet_dma[ENET_RECV].m_ctrl;
+	case 0x5008/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver GIO FIFO Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_gio_fifo_ptr);
+		return m_enet_dma[ENET_RECV].m_gio_fifo_ptr;
+	case 0x500c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Device FIFO Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_RECV].m_dev_fifo_ptr);
+		return m_enet_dma[ENET_RECV].m_dev_fifo_ptr;
+	case 0x5014/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Reset Register Read: %08x\n", machine().describe_context(), m_enet_reset);
+		return m_enet_reset;
+	case 0x5018/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet DMA Config Read: %08x\n", machine().describe_context(), m_enet_dmacfg);
+		return m_enet_dmacfg;
+	case 0x501c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet PIO Config Read: %08x\n", machine().describe_context(), m_enet_piocfg);
+		return m_enet_piocfg;
+	case 0x6000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Current Buffer Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_cbp);
+		return m_enet_dma[ENET_XMIT].m_cbp;
+	case 0x6004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Next Buffer Desc Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_nbdp);
+		return m_enet_dma[ENET_XMIT].m_nbdp;
+	case 0x7000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Buffer Count Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_bc);
+		return m_enet_dma[ENET_XMIT].m_bc;
+	case 0x7004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter DMA Control Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_ctrl);
+		return m_enet_dma[ENET_XMIT].m_ctrl;
+	case 0x7008/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter GIO FIFO Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_gio_fifo_ptr);
+		return m_enet_dma[ENET_XMIT].m_gio_fifo_ptr;
+	case 0x700c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Device FIFO Pointer Read: %08x\n", machine().describe_context(), m_enet_dma[ENET_XMIT].m_dev_fifo_ptr);
+		return m_enet_dma[ENET_XMIT].m_dev_fifo_ptr;
 	default:
 		LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx Read: %08x & %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask);
 		return 0;
@@ -345,7 +418,6 @@ WRITE32_MEMBER(hpc3_base_device::hd_enet_w)
 		const uint32_t channel = (offset & 0x2000/4) ? 1 : 0;
 		LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI%d Next Buffer Desc Pointer Write: %08x\n", machine().describe_context(), channel, data);
 		m_scsi_dma[channel].m_nbdp = data;
-		fetch_chain(channel);
 		break;
 	}
 	case 0x1004/4:
@@ -353,11 +425,16 @@ WRITE32_MEMBER(hpc3_base_device::hd_enet_w)
 	{
 		const uint32_t channel = (offset & 0x2000/4) ? 1 : 0;
 		LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI%d DMA Control Write: %08x\n", machine().describe_context(), channel, data);
+		const bool was_active = m_scsi_dma[channel].m_active;
 		m_scsi_dma[channel].m_ctrl = data;
 		m_scsi_dma[channel].m_to_device = (m_scsi_dma[channel].m_ctrl & HPC3_DMACTRL_DIR);
 		m_scsi_dma[channel].m_big_endian = (m_scsi_dma[channel].m_ctrl & HPC3_DMACTRL_ENDIAN);
 		m_scsi_dma[channel].m_active = (m_scsi_dma[channel].m_ctrl & HPC3_DMACTRL_ENABLE);
 		m_scsi_dma[channel].m_irq = (m_scsi_dma[channel].m_ctrl & HPC3_DMACTRL_IRQ);
+		if (!was_active && m_scsi_dma[channel].m_active)
+		{
+			fetch_chain(channel);
+		}
 		if (channel)
 		{
 			if (m_wd33c93_2)
@@ -390,12 +467,57 @@ WRITE32_MEMBER(hpc3_base_device::hd_enet_w)
 		break;
 	}
 	case 0x4000/4:
-		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet CBP Write: %08x\n", machine().describe_context(), data);
-		m_enetr_cbp = data;
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Current Buffer Pointer Write: %08x\n", machine().describe_context(), data);
+		m_enet_dma[ENET_RECV].m_cbp = data;
 		break;
 	case 0x4004/4:
-		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet NBDP Write: %08x\n", machine().describe_context(), data);
-		m_enetr_nbdp = data;
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Next Buffer Desc Pointer Write: %08x\n", machine().describe_context(), data);
+		m_enet_dma[ENET_RECV].m_nbdp = data;
+		break;
+	case 0x5000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Buffer Count Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x5004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver DMA Control Write: %08x\n", machine().describe_context(), data);
+		m_enet_dma[ENET_RECV].m_ctrl = data;
+		break;
+	case 0x5008/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver GIO FIFO Pointer Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x500c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Receiver Device FIFO Pointer Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x5014/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Reset Register Write: %08x\n", machine().describe_context(), data);
+		m_enet_reset = data;
+		break;
+	case 0x5018/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet DMA Config Write: %08x\n", machine().describe_context(), data);
+		m_enet_dmacfg = data;
+		break;
+	case 0x501c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet PIO Config Write: %08x\n", machine().describe_context(), data);
+		m_enet_piocfg = data;
+		break;
+	case 0x6000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Current Buffer Pointer Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x6004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Next Buffer Desc Pointer Write: %08x\n", machine().describe_context(), data);
+		m_enet_dma[ENET_XMIT].m_nbdp = data;
+		break;
+	case 0x7000/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Buffer Count Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x7004/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter DMA Control Write: %08x\n", machine().describe_context(), data);
+		m_enet_dma[ENET_XMIT].m_ctrl = data;
+		break;
+	case 0x7008/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter GIO FIFO Pointer Write (ignored): %08x\n", machine().describe_context(), data);
+		break;
+	case 0x700c/4:
+		LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet Transmitter Device FIFO Pointer Write (ignored): %08x\n", machine().describe_context(), data);
 		break;
 	default:
 		LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), data, mem_mask);
@@ -403,6 +525,51 @@ WRITE32_MEMBER(hpc3_base_device::hd_enet_w)
 	}
 }
 
+template<hpc3_base_device::fifo_type_t type>
+READ32_MEMBER(hpc3_base_device::fifo_r)
+{
+	uint32_t ret = 0;
+	if (type == FIFO_PBUS)
+		ret = m_pbus_fifo[offset >> 1];
+	else if (type == FIFO_SCSI0)
+		ret = m_scsi_fifo[0][offset >> 1];
+	else if (type == FIFO_SCSI1)
+		ret = m_scsi_fifo[1][offset >> 1];
+	else if (type == FIFO_ENET_RECV)
+		ret = m_enet_fifo[ENET_RECV][offset >> 1];
+	else if (type == FIFO_ENET_XMIT)
+		ret = m_enet_fifo[ENET_XMIT][offset >> 1];
+	logerror("Reading %08x from %d FIFO offset %08x (%08x)\n", ret, type, offset, offset >> 1);
+	return ret;
+}
+
+template<hpc3_base_device::fifo_type_t type>
+WRITE32_MEMBER(hpc3_base_device::fifo_w)
+{
+	logerror("Writing %08x to %d FIFO offset %08x (%08x)\n", data, type, offset, offset >> 2);
+	if (type == FIFO_PBUS)
+		m_pbus_fifo[offset >> 2] = data;
+	else if (type == FIFO_SCSI0)
+		m_scsi_fifo[0][offset >> 1] = data;
+	else if (type == FIFO_SCSI1)
+		m_scsi_fifo[1][offset >> 1] = data;
+	else if (type == FIFO_ENET_RECV)
+		m_enet_fifo[ENET_RECV][offset >> 2] = data;
+	else if (type == FIFO_ENET_XMIT)
+		m_enet_fifo[ENET_XMIT][offset >> 2] = data;
+}
+
+template READ32_MEMBER(hpc3_base_device::fifo_r<hpc3_base_device::FIFO_PBUS>);
+template READ32_MEMBER(hpc3_base_device::fifo_r<hpc3_base_device::FIFO_SCSI0>);
+template READ32_MEMBER(hpc3_base_device::fifo_r<hpc3_base_device::FIFO_SCSI1>);
+template READ32_MEMBER(hpc3_base_device::fifo_r<hpc3_base_device::FIFO_ENET_RECV>);
+template READ32_MEMBER(hpc3_base_device::fifo_r<hpc3_base_device::FIFO_ENET_XMIT>);
+template WRITE32_MEMBER(hpc3_base_device::fifo_w<hpc3_base_device::FIFO_PBUS>);
+template WRITE32_MEMBER(hpc3_base_device::fifo_w<hpc3_base_device::FIFO_SCSI0>);
+template WRITE32_MEMBER(hpc3_base_device::fifo_w<hpc3_base_device::FIFO_SCSI1>);
+template WRITE32_MEMBER(hpc3_base_device::fifo_w<hpc3_base_device::FIFO_ENET_RECV>);
+template WRITE32_MEMBER(hpc3_base_device::fifo_w<hpc3_base_device::FIFO_ENET_XMIT>);
+
 template<uint32_t index>
 READ32_MEMBER(hpc3_base_device::hd_r)
 {
diff --git a/src/mame/machine/hpc3.h b/src/mame/machine/hpc3.h
index 87e9e2a472f..494b244d1a9 100644
--- a/src/mame/machine/hpc3.h
+++ b/src/mame/machine/hpc3.h
@@ -31,6 +31,8 @@ public:
 
 	void raise_local_irq(int channel, uint32_t mask) { m_ioc2->raise_local_irq(channel, mask); }
 	void lower_local_irq(int channel, uint32_t mask) { m_ioc2->lower_local_irq(channel, mask); }
+	void raise_mappable_irq(uint8_t mask) { m_ioc2->set_mappable_int(mask, true); }
+	void lower_mappable_irq(uint8_t mask) { m_ioc2->set_mappable_int(mask, false); }
 
 	DECLARE_WRITE_LINE_MEMBER(scsi0_irq);
 	DECLARE_WRITE_LINE_MEMBER(scsi0_drq);
@@ -45,12 +47,23 @@ protected:
 	virtual void device_add_mconfig(machine_config &config) override;
 	virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
 
+	enum fifo_type_t : uint32_t
+	{
+		FIFO_PBUS,
+		FIFO_SCSI0,
+		FIFO_SCSI1,
+		FIFO_ENET_RECV,
+		FIFO_ENET_XMIT
+	};
+
 	DECLARE_READ32_MEMBER(enet_r);
 	DECLARE_WRITE32_MEMBER(enet_w);
 	DECLARE_READ32_MEMBER(hd_enet_r);
 	DECLARE_WRITE32_MEMBER(hd_enet_w);
 	template <uint32_t index> DECLARE_READ32_MEMBER(hd_r);
 	template <uint32_t index> DECLARE_WRITE32_MEMBER(hd_w);
+	template <fifo_type_t type> DECLARE_READ32_MEMBER(fifo_r);
+	template <fifo_type_t type> DECLARE_WRITE32_MEMBER(fifo_w);
 	DECLARE_READ32_MEMBER(intstat_r);
 	DECLARE_READ32_MEMBER(eeprom_r);
 	DECLARE_WRITE32_MEMBER(eeprom_w);
@@ -123,6 +136,12 @@ protected:
 		HPC3_DMACTRL_ENABLE = 0x10,
 	};
 
+	enum
+	{
+		ENET_RECV = 0,
+		ENET_XMIT = 1
+	};
+
 	required_device<cpu_device> m_maincpu;
 	required_device<wd33c93b_device> m_wd33c93;
 	optional_device<wd33c93b_device> m_wd33c93_2;
@@ -134,8 +153,6 @@ protected:
 	required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
 
 	uint32_t m_intstat;
-	uint32_t m_enetr_nbdp;
-	uint32_t m_enetr_cbp;
 	uint32_t m_cpu_aux_ctrl;
 	uint8_t m_volume_l;
 	uint8_t m_volume_r;
@@ -155,10 +172,29 @@ protected:
 		bool m_active;
 	};
 
+	struct enet_dma_t
+	{
+		uint32_t m_cbp;
+		uint32_t m_nbdp;
+		uint32_t m_bc;
+		uint32_t m_ctrl;
+		uint32_t m_gio_fifo_ptr;
+		uint32_t m_dev_fifo_ptr;
+	};
+
+	enet_dma_t m_enet_dma[2];
+	uint32_t m_enet_reset;
+	uint32_t m_enet_dmacfg;
+	uint32_t m_enet_piocfg;
+
 	scsi_dma_t m_scsi_dma[2];
 	pbus_dma_t m_pbus_dma[8];
 	uint32_t m_pio_config[10];
 
+	std::unique_ptr<uint32_t[]> m_pbus_fifo;
+	std::unique_ptr<uint32_t[]> m_scsi_fifo[2];
+	std::unique_ptr<uint32_t[]> m_enet_fifo[2];
+
 	address_space *m_cpu_space;
 };
 
diff --git a/src/mame/machine/ioc2.cpp b/src/mame/machine/ioc2.cpp
index 5c5d1b3355b..c9455b4197e 100644
--- a/src/mame/machine/ioc2.cpp
+++ b/src/mame/machine/ioc2.cpp
@@ -90,10 +90,28 @@ void ioc2_device::device_add_mconfig(machine_config &config)
 
 	PC_LPT(config, m_pi1);
 
+#if IOC2_NEW_KBDC
+	pc_kbdc_device &kbdc(PC_KBDC(config, "pc_kbdc", 0));
+	kbdc.out_clock_cb().set(m_kbdc, FUNC(ps2_keyboard_controller_device::kbd_clk_w));
+	kbdc.out_data_cb().set(m_kbdc, FUNC(ps2_keyboard_controller_device::kbd_data_w));
+
+	// keyboard port
+	pc_kbdc_slot_device &kbd(PC_KBDC_SLOT(config, "kbd", 0));
+	pc_at_keyboards(kbd);
+	kbd.set_default_option(STR_KBD_MICROSOFT_NATURAL);
+	kbd.set_pc_kbdc_slot(&kbdc);
+
+	// keyboard controller
+	PS2_KEYBOARD_CONTROLLER(config, m_kbdc, 12_MHz_XTAL);
+	m_kbdc->kbd_clk().set(kbdc, FUNC(pc_kbdc_device::clock_write_from_mb));
+	m_kbdc->kbd_data().set(kbdc, FUNC(pc_kbdc_device::data_write_from_mb));
+	m_kbdc->kbd_irq().set(FUNC(ioc2_device::kbdc_int_w));
+#else
 	KBDC8042(config, m_kbdc);
 	m_kbdc->set_keyboard_type(kbdc8042_device::KBDC8042_PS2);
 	m_kbdc->system_reset_callback().set_inputline(m_maincpu, INPUT_LINE_RESET);
 	m_kbdc->input_buffer_full_callback().set(FUNC(ioc2_device::kbdc_int_w));
+#endif
 
 	PIT8254(config, m_pit, 0);
 	m_pit->set_clk<0>(0);
@@ -211,7 +229,9 @@ WRITE_LINE_MEMBER(ioc2_device::pit_clock2_out)
 {
 	m_pit->write_clk0(state);
 	m_pit->write_clk1(state);
+#if !IOC2_NEW_KBDC
 	m_kbdc->write_out2(state);
+#endif
 }
 
 WRITE_LINE_MEMBER(ioc2_device::kbdc_int_w)
@@ -338,13 +358,21 @@ READ32_MEMBER(ioc2_device::read)
 
 		case KBD_MOUSE_REGS1:
 		{
+#if IOC2_NEW_KBDC
+			const uint8_t data = m_kbdc->data_r();
+#else
 			const uint8_t data = m_kbdc->data_r(space, 0);
+#endif
 			LOGMASKED(LOG_MOUSEKBD, "%s: Read Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), data);
 			return data;
 		}
 		case KBD_MOUSE_REGS2:
 		{
+#if IOC2_NEW_KBDC
+			const uint8_t data = m_kbdc->status_r();
+#else
 			const uint8_t data = m_kbdc->data_r(space, 4);
+#endif
 			LOGMASKED(LOG_MOUSEKBD, "%s: Read Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), data);
 			return data;
 		}
@@ -519,11 +547,19 @@ WRITE32_MEMBER( ioc2_device::write )
 
 		case KBD_MOUSE_REGS1:
 			LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 1: %02x\n", machine().describe_context(), (uint8_t)data);
+#if IOC2_NEW_KBDC
+			m_kbdc->data_w(data & 0xff);
+#else
 			m_kbdc->data_w(space, 0, data & 0xff);
+#endif
 			return;
 		case KBD_MOUSE_REGS2:
 			LOGMASKED(LOG_MOUSEKBD, "%s: Write Keyboard/Mouse Register 2: %02x\n", machine().describe_context(), (uint8_t)data);
+#if IOC2_NEW_KBDC
+			m_kbdc->command_w(data & 0xff);
+#else
 			m_kbdc->data_w(space, 4, data & 0xff);
+#endif
 			return;
 
 		case PANEL_REG:
@@ -658,7 +694,9 @@ void ioc2_device::handle_reset_reg_write(uint8_t data)
 	// guinness/fullhouse-specific implementations can handle bit 3 being used for ISDN reset on Indy only and bit 2 for EISA reset on Indigo 2 only, but for now we do nothing with it
 	if (BIT(data, 1))
 	{
+#if !IOC2_NEW_KBDC
 		m_kbdc->reset();
+#endif
 	}
 	m_reset_reg = 0;
 }
diff --git a/src/mame/machine/ioc2.h b/src/mame/machine/ioc2.h
index 7a5db0ec1fb..0d61bda84b7 100644
--- a/src/mame/machine/ioc2.h
+++ b/src/mame/machine/ioc2.h
@@ -11,7 +11,15 @@
 
 #pragma once
 
+#define IOC2_NEW_KBDC	(0)
+
+#if IOC2_NEW_KBDC
+#include "machine/at_keybc.h"
+#else
 #include "machine/8042kbdc.h"
+#endif
+#include "bus/pc_kbd/pc_kbdc.h"
+#include "bus/pc_kbd/keyboards.h"
 #include "machine/pc_lpt.h"
 #include "machine/pckeybrd.h"
 #include "machine/pit8253.h"
@@ -64,6 +72,7 @@ public:
 	void set_local_int_mask(int channel, const uint32_t mask);
 	void set_map_int_mask(int channel, const uint32_t mask);
 	void set_timer_int_clear(const uint32_t data);
+	void set_mappable_int(uint8_t mask, bool state);
 
 	uint8_t get_pit_reg(uint32_t offset) { return m_pit->read(offset); }
 	void set_pit_reg(uint32_t offset, uint8_t data) { return m_pit->write(offset, data); }
@@ -82,7 +91,6 @@ protected:
 	DECLARE_WRITE_LINE_MEMBER(kbdc_int_w);
 	DECLARE_WRITE_LINE_MEMBER(duart_int_w);
 
-	void set_mappable_int(uint8_t mask, bool state);
 	void check_mappable_interrupt(int channel);
 
 	enum
@@ -158,8 +166,12 @@ protected:
 	required_device<cpu_device> m_maincpu;
 	required_device<scc85230_device> m_scc;
 	required_device<pc_lpt_device> m_pi1;   // we assume standard parallel port (SPP) mode
-											// TODO: SGI parallel port (SGIPP), HP BOISE high speed parallel port (HPBPP), and Ricoh scanner modes
+											// TODO: SGI parallel port (SGIPP), HP BOISE high speed parallel port (HPBPP), and Ricoh scanner mode
+#if IOC2_NEW_KBDC
+	required_device<ps2_keyboard_controller_device> m_kbdc;
+#else
 	required_device<kbdc8042_device> m_kbdc;
+#endif
 	required_device<pit8254_device> m_pit;
 
 	virtual void handle_reset_reg_write(uint8_t data);
diff --git a/src/mame/machine/sgi.cpp b/src/mame/machine/sgi.cpp
index d7ab63e0109..91a9ae7870e 100644
--- a/src/mame/machine/sgi.cpp
+++ b/src/mame/machine/sgi.cpp
@@ -234,7 +234,6 @@ void sgi_mc_device::dma_tick()
 			uint64_t data = m_space->read_qword(m_dma_gio64_addr);
 			for (uint32_t i = 0; i < length; i++)
 			{
-				logerror("Copy-mode DMA of %02x to %08x\n", (uint8_t)(data >> shift), addr);
 				m_space->write_byte(addr, (uint8_t)(data >> shift));
 				addr++;
 				shift -= 8;
@@ -373,10 +372,10 @@ READ32_MEMBER(sgi_mc_device::read)
 		LOGMASKED(LOG_READS, "%s: EISA Lock Read: %08x & %08x\n", machine().describe_context(), m_eisa_lock, mem_mask);
 		return m_eisa_lock;
 	case 0x0150/4:
-		LOGMASKED(LOG_READS, "%s: GIO64 Translation Address Mask Read: %08x & %08x\n", machine().describe_context(), m_gio64_translate_mask, mem_mask);
+		LOGMASKED(LOG_READS | LOG_DMA, "%s: GIO64 Translation Address Mask Read: %08x & %08x\n", machine().describe_context(), m_gio64_translate_mask, mem_mask);
 		return m_gio64_translate_mask;
 	case 0x0158/4:
-		LOGMASKED(LOG_READS, "%s: GIO64 Translation Address Substitution Bits Read: %08x & %08x\n", machine().describe_context(), m_gio64_substitute_bits, mem_mask);
+		LOGMASKED(LOG_READS | LOG_DMA, "%s: GIO64 Translation Address Substitution Bits Read: %08x & %08x\n", machine().describe_context(), m_gio64_substitute_bits, mem_mask);
 		return m_gio64_substitute_bits;
 	case 0x0160/4:
 		LOGMASKED(LOG_READS | LOG_DMA, "%s: DMA Interrupt Cause: %08x & %08x\n", machine().describe_context(), m_dma_int_cause, mem_mask);
@@ -571,11 +570,11 @@ WRITE32_MEMBER( sgi_mc_device::write )
 		m_eisa_lock = data;
 		break;
 	case 0x0150/4:
-		LOGMASKED(LOG_WRITES, "%s: GIO64 Translation Address Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
+		LOGMASKED(LOG_WRITES | LOG_DMA, "%s: GIO64 Translation Address Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
 		m_gio64_translate_mask = data;
 		break;
 	case 0x0158/4:
-		LOGMASKED(LOG_WRITES, "%s: GIO64 Translation Address Substitution Bits Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
+		LOGMASKED(LOG_WRITES | LOG_DMA, "%s: GIO64 Translation Address Substitution Bits Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
 		m_gio64_substitute_bits = data;
 		break;
 	case 0x0160/4: