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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
Created a better logic-to-analog proxy approximating output impedance. This revealed some bugs in the code which have been fixed.
Basically, borderline schematics like TTL_7404_INVERT(c9f, c9c.Q) TTL_7404_INVERT(c9c, c9f.Q) SWITCH2(coinsw) NET_C(c9c.Q, coinsw.1) NET_C(c9f.Q, coinsw.2) in which the switch connects TTL-Outputs to ground now work. In this case, the addition of an analog device (switch) cause the netlist code to treat the TTL outputs as "analog" and (re)connect all existing and future connected terminals to the analog output. The downside is a slight performance penalty. This penalty may be mitigated going forward by introducing "proxy-hints" for selected outputs.
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5f9b93e172
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@ -184,7 +184,7 @@ protected:
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private:
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};
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#if 1
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#if 0
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class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
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{
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public:
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@ -18,7 +18,7 @@ netlist_logic_family_desc_t netlist_family_ttl =
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0.3, // m_low_V - these depend on sinked/sourced current. Values should be suitable for typical applications.
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3.4, // m_high_V
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10.0, // m_g_low;
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130.0, // m_g_high;
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130.0, //130.0, // m_g_high;
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};
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// ----------------------------------------------------------------------------------------
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@ -389,6 +389,7 @@ public:
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//ATTR_COLD void init_object(netlist_core_device_t &dev, const pstring &aname);
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ATTR_COLD void set_net(netlist_net_t &anet);
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ATTR_COLD inline void clear_net() { m_net = NULL; }
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ATTR_COLD inline bool has_net() const { return (m_net != NULL); }
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ATTR_HOT inline const netlist_net_t & RESTRICT net() const { return *m_net;}
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ATTR_HOT inline netlist_net_t & RESTRICT net() { return *m_net;}
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@ -724,6 +725,7 @@ public:
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ATTR_COLD void initial(const netlist_sig_t val);
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ATTR_COLD bool has_proxy() { return (m_proxy != NULL); }
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ATTR_COLD nld_base_d_to_a_proxy *get_proxy() { return m_proxy; }
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ATTR_COLD void set_proxy(nld_base_d_to_a_proxy *proxy) { m_proxy = proxy; }
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@ -366,6 +366,18 @@ nld_base_d_to_a_proxy *netlist_setup_t::get_d_a_proxy(netlist_output_t &out)
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proxy->init(netlist(), x);
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register_dev(proxy, x);
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/* connect all existing terminals to new net */
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netlist_core_terminal_t *p = out.net().m_head;
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while (p != NULL)
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{
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netlist_core_terminal_t *np = p->m_update_list_next;
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p->clear_net(); // de-link from all nets ...
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connect(proxy->out(), *p);
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p = np;
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}
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out.net().m_head = NULL; // clear the list
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out.net().m_num_cons = 0;
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out.net().register_con(proxy->m_I);
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out_cast.set_proxy(proxy);
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@ -488,9 +500,22 @@ void netlist_setup_t::connect_terminals(netlist_core_terminal_t &t1, netlist_cor
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}
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}
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void netlist_setup_t::connect(netlist_core_terminal_t &t1, netlist_core_terminal_t &t2)
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static netlist_core_terminal_t &resolve_proxy(netlist_core_terminal_t &term)
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{
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if (term.isType(netlist_core_terminal_t::OUTPUT) && term.isFamily(netlist_core_terminal_t::LOGIC))
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{
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netlist_logic_output_t &out = dynamic_cast<netlist_logic_output_t &>(term);
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if (out.has_proxy())
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return out.get_proxy()->out();
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}
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return term;
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}
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void netlist_setup_t::connect(netlist_core_terminal_t &t1_in, netlist_core_terminal_t &t2_in)
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{
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NL_VERBOSE_OUT(("Connecting %s to %s\n", t1.name().cstr(), t2.name().cstr()));
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netlist_core_terminal_t &t1 = resolve_proxy(t1_in);
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netlist_core_terminal_t &t2 = resolve_proxy(t2_in);
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// FIXME: amend device design so that warnings can be turned into errors
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// Only variable inputs have this issue
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@ -63,7 +63,7 @@ fixedfreq_interface fixedfreq_mode_pong = {
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H_TOTAL-67,H_TOTAL-40,H_TOTAL-8,H_TOTAL,
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V_TOTAL-22,V_TOTAL-19,V_TOTAL-12,V_TOTAL,
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1, /* non-interlaced */
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0.32
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0.30
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};
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fixedfreq_interface fixedfreq_mode_pongX2 = {
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@ -71,7 +71,7 @@ fixedfreq_interface fixedfreq_mode_pongX2 = {
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(H_TOTAL-67) * 2, (H_TOTAL-40) * 2, (H_TOTAL-8) * 2, (H_TOTAL) * 2,
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V_TOTAL-22,V_TOTAL-19,V_TOTAL-16,V_TOTAL,
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1, /* non-interlaced */
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0.32
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0.30
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};
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enum input_changed_enum
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@ -134,8 +134,9 @@ static NETLIST_START(pong_schematics)
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/* Coin, antenna and startup circuit */
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ANALOG_INPUT(STOPG, 0)
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ALIAS(SRSTQ, RYf.2)
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ALIAS(SRST, RYc.2)
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ALIAS(SRSTQ, c9f.Q)
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ALIAS(SRST, c9c.Q)
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/* SRSTQ has a diode to +3V to protect against overvoltage - omitted */
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@ -145,6 +146,16 @@ static NETLIST_START(pong_schematics)
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TTL_7404_INVERT(e4d, STOPG)
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#if 1
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TTL_7404_INVERT(c9f, c9c.Q)
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TTL_7404_INVERT(c9c, c9f.Q)
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SWITCH2(coinsw)
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NET_C(c9c.Q, coinsw.1)
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NET_C(c9f.Q, coinsw.2)
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#else
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RES(RYf, 50) // output impedance - not in schematics, hack (till better proxies exist)
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RES(RYc, 50) // output impedance - not in schematics, hack (till better proxies exist)
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@ -156,7 +167,7 @@ static NETLIST_START(pong_schematics)
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SWITCH2(coinsw)
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NET_C(RYc.2, coinsw.1)
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NET_C(RYf.2, coinsw.2)
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#endif
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NET_C(coinsw.Q, GND)
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/* Antenna circuit */
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