mirror of
https://github.com/holub/mame
synced 2025-05-31 10:01:51 +03:00
Merge pull request #514 from bmunger/r9751
New driver: ROLM 9751 [Brandon Munger]
This commit is contained in:
Miodrag Milanović
commit
54cadc3c31
@ -2701,3 +2701,14 @@ if (MACHINES["VT82C496"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/emu/machine/pdc.h,MACHINES["PDC"] = true
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---------------------------------------------------
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if (MACHINES["PDC"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/pdc.cpp",
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MAME_DIR .. "src/devices/machine/pdc.h",
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}
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end
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@ -486,6 +486,7 @@ MACHINES["PC_LPT"] = true
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MACHINES["PCCARD"] = true
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MACHINES["PCF8593"] = true
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MACHINES["PCKEYBRD"] = true
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MACHINES["PDC"] = true
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MACHINES["PIC8259"] = true
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MACHINES["PIT68230"] = true
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MACHINES["PIT8253"] = true
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@ -808,6 +809,7 @@ function linkProjects_mame_mess(_target, _subtarget)
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"robotron",
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"rockwell",
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"roland",
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"rolm",
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"sage",
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"samcoupe",
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"samsung",
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@ -2361,6 +2363,11 @@ files {
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MAME_DIR .. "src/mame/drivers/tb303.cpp",
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}
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createMESSProjects(_target, _subtarget, "rolm")
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files {
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MAME_DIR .. "src/mame/drivers/r9751.cpp",
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}
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createMESSProjects(_target, _subtarget, "rockwell")
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files {
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MAME_DIR .. "src/mame/drivers/aim65.cpp",
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591
src/devices/machine/pdc.cpp
Normal file
591
src/devices/machine/pdc.cpp
Normal file
@ -0,0 +1,591 @@
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// license:GPL-2.0+
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// copyright-holders:Brandon Munger
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/**********************************************************************
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ROLM 9751 9005 Peripheral device controller emulation
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**********************************************************************/
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/*
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Device PDCN
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Board Copyright - IBM Corp 1989 Made in USA
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Labels:
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* 96D1975
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MN 90594C
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* EC# A6466SP
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MFG 85575
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Hardware:
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* CPU - Zilog Z0840006PSC Z80 @ 5MHz - U19
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* FDC - NEC D765AC-2 9002P7004 - U35
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* HDC - HDC9224 SMC E8838 8/90 - U59
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* DMA - P8237A-5 L1041330 - U34
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* Channel 0 - FDC
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* Channel 1 - Main system ram
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* Memory - HM6264ALP-12 SRAM 8KB - U16
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* Memory - HM6116P-2 SRAM 2KB - U33
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Logic:
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* U1 - PLS105AN Label: 59D9101
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* U11 - ?? Label: 59D10001
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* U27 - ?? Label: 96D1978
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* U28 - ?? Label: 97D8750
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* U31 - TIBPAL20L8-25CNT Label: 96D1987
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* U32 - ?? Label: 59D1001
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* U37 - PLS100N Label: 72D2701
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* U38 - PLS100N Label: 58D9201
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* U39 - ?? Label: 96D1981
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* U40 - ?? Label: 96D1984
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* U68 - ?? Label: 91D4301
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* U69 - ?? Label: 59D1001
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* U70 - ?? Label: 59D1001
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Switches:
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* S1 - Hard drive format configuration (Default all off)
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* S2 - Floppy drive format configuration (Default 1-7 off, 8 on)
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Program Memory:
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* 0x0000 - 0x3FFF : ROM 27128 Label: 97D9988
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* 0x8000 - 0x9FFF : SRAM HM6264ALP-12 8KB
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* 0xC000 - 0xC7FF : SRAM HM6116P-2 2KB
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IO Memory:
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* 0x00 - 0x01 : Old style command [0x5FF041B0]
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* 0x02 - 0x03 : FDC command address [0x5FF0C0B0][0x5FF0C1B0]
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* 0x04 - 0x05 : FDC command completion status [0x5FF030B0]
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* 0x06 - 0x07 : FDC data address [0x5FF080B0]
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* 0x10 - 0x18 : HDC registers (unknown)
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* 0x21 - 0x21 : FDC unknown, resets bit 1 on 0x38
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* 0x22 - 0x22 : FDC unknown
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* 0x23 - 0x24 : FDC Active DMA host address (auto increments)
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* 0x25 - 0x25 : FDC unknown
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* 0x26 - 0x26 : DREQ1 on
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* 0x27 - 0x27 : FDC unknown
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* 0x28 - 0x2A : Possibly LED lights
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* 0x2C - 0x2C : DREQ1 off
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* 0x2D - 0x2D : Unknown
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* 0x2E - 0x2E : Transfer direction 0x80 = PDC -> Host (read data)
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0x00 = Host -> PDC (Commands, write data)
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* 0x2F - 0x2F : Unknown
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* 0x38 - 0x38 : FDC command request
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Bit 1: Debug?
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Bit 2: Command complete
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Bit 3: Unknown
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Bit 5: Unknown
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Bit 6-7: Error conditions
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* 0x39 - 0x39 : Interrupt status
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Bit 0: HDC9224 interrupt
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Bit 1: Incoming command
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Bit 3: FDD related, maybe uPD interrupt pin?
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* 0x3C - 0x3D : Dipswitch 2 and 1
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* 0x40 - 0x40 : HDC9224 DATA register
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* 0x41 - 0x41 : HDC9224 COMMAND register
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* 0x42 - 0x42 : uPD765 STATUS register
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* 0x43 - 0x43 : uPD765 DATA register
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* 0x50 - 0x51 : Unknown - reset latch maybe?
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* 0x52 - 0x52 : FDD Master motor control
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* 0x53 - 0x53 : Unknown
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* 0x54 - 0x57 : FDD motor control (Units 1-4)
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* 0x60 - 0x6F : P8237A DMA controller register set
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*/
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#include "pdc.h"
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//**************************************************************************
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// MACROS / CONSTANTS
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//**************************************************************************
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#define Z80_TAG "pdc_z80" // U19
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#define FDC_TAG "fdc"
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#define HDC_TAG "hdc"
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#define FDCDMA_TAG "i8237dma"
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#define TRACE_PDC_FDC 0
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#define TRACE_PDC_HDC 0
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#define TRACE_PDC_DMA 0
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#define TRACE_PDC_CMD 0
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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const device_type PDC = &device_creator<pdc_device>;
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//-------------------------------------------------
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// ROM( PDC )
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//-------------------------------------------------
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ROM_START( pdc )
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ROM_REGION( 0x4000, "rom", 0 )
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ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17
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ROM_END
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//-------------------------------------------------
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// rom_region - device-specific ROM region
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//-------------------------------------------------
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const rom_entry *pdc_device::device_rom_region() const
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{
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return ROM_NAME( pdc );
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}
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//-------------------------------------------------
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// ADDRESS_MAP( pdc_mem )
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//-------------------------------------------------
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static ADDRESS_MAP_START( pdc_mem, AS_PROGRAM, 8, pdc_device )
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AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("rom", 0)
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AM_RANGE(0x8000, 0x9FFF) AM_RAM AM_SHARE("pdc_ram") // HM6264ALP-12 SRAM 8KB
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AM_RANGE(0xC000, 0xC7FF) AM_RAM // HM6116P-2 SRAM 2KB
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ADDRESS_MAP_END
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//-------------------------------------------------
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// ADDRESS_MAP( pdc_io )
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//-------------------------------------------------
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static ADDRESS_MAP_START( pdc_io, AS_IO, 8, pdc_device )
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AM_RANGE(0x00, 0x07) AM_READWRITE(p0_7_r,p0_7_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x21, 0x2F) AM_READWRITE(fdd_68k_r,fdd_68k_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x38, 0x38) AM_READ(p38_r) AM_MIRROR(0xFF00) // Possibly UPD765 interrupt
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AM_RANGE(0x39, 0x39) AM_READ(p39_r) AM_MIRROR(0xFF00) // HDD related
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AM_RANGE(0x3c, 0x3c) AM_READ_PORT("SW2") AM_MIRROR(0xFF00) /* FDC Dipswitch */
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AM_RANGE(0x3d, 0x3d) AM_READ_PORT("SW1") AM_MIRROR(0xFF00) /* HDC Dipswitch */
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AM_RANGE(0x40, 0x41) AM_DEVREADWRITE(HDC_TAG, hdc9224_device,read,write) AM_MIRROR(0xFF00)
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AM_RANGE(0x42, 0x43) AM_DEVICE(FDC_TAG, upd765a_device, map) AM_MIRROR(0xFF00)
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AM_RANGE(0x50, 0x5f) AM_WRITE(p50_5f_w) AM_MIRROR(0xFF00)
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AM_RANGE(0x60, 0x6f) AM_DEVREADWRITE(FDCDMA_TAG,am9517a_device,read,write) AM_MIRROR(0xFF00)
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ADDRESS_MAP_END
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//-------------------------------------------------
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// INPUT_PORTS_START( pdc )
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//-------------------------------------------------
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static INPUT_PORTS_START( pdc_ports )
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/* Hard Disk Controller SW1 */
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PORT_START("SW1")
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PORT_DIPNAME( 0x80, 0x80, "SW1-1") PORT_DIPLOCATION("SW1:1")
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, "SW1-2") PORT_DIPLOCATION("SW1:2")
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, "SW1-3") PORT_DIPLOCATION("SW1:3")
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, "SW1-4") PORT_DIPLOCATION("SW1:4")
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, "SW1-5") PORT_DIPLOCATION("SW1:5")
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, "SW1-6") PORT_DIPLOCATION("SW1:6")
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, "SW1-7") PORT_DIPLOCATION("SW1:7")
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x01, 0x01, "SW1-8") PORT_DIPLOCATION("SW1:8")
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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/* Floppy Disk Controller SW2 */
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PORT_START("SW2")
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PORT_DIPNAME( 0x80, 0x80, "SW2-1") PORT_DIPLOCATION("SW2:1")
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PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x40, 0x40, "SW2-2") PORT_DIPLOCATION("SW2:2")
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PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x20, 0x20, "SW2-3") PORT_DIPLOCATION("SW2:3")
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x10, 0x10, "SW2-4") PORT_DIPLOCATION("SW2:4")
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PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x08, 0x08, "SW2-5") PORT_DIPLOCATION("SW2:5")
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PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x04, 0x04, "SW2-6") PORT_DIPLOCATION("SW2:6")
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PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x02, 0x02, "SW2-7") PORT_DIPLOCATION("SW2:7")
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PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_DIPNAME( 0x01, 0x00, "SW2-8") PORT_DIPLOCATION("SW2:8")
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PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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INPUT_PORTS_END
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//-------------------------------------------------
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// SLOT_INTERFACE( pdc_floppies )
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//-------------------------------------------------
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static SLOT_INTERFACE_START( pdc_floppies )
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SLOT_INTERFACE( "35hd", FLOPPY_35_HD )
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SLOT_INTERFACE_END
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//-------------------------------------------------
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// SLOT_INTERFACE( pdc_harddisks )
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//-------------------------------------------------
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static SLOT_INTERFACE_START( pdc_harddisks )
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SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image)
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SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB)
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SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB)
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SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB)
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SLOT_INTERFACE_END
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//-------------------------------------------------
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// FLOPPY_FORMATS( floppy_formats )
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//-------------------------------------------------
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FLOPPY_FORMATS_MEMBER( pdc_device::floppy_formats )
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FLOPPY_PC_FORMAT
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FLOPPY_FORMATS_END
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//-------------------------------------------------
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// MACHINE_DRIVER( pdc )
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//-------------------------------------------------
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static MACHINE_CONFIG_FRAGMENT( pdc )
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/* CPU - Zilog Z0840006PSC */
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MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2)
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MCFG_CPU_PROGRAM_MAP(pdc_mem)
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MCFG_CPU_IO_MAP(pdc_io)
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//MCFG_QUANTUM_PERFECT_CPU(M6502_TAG)
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/* Floppy Disk Controller - uPD765a - NEC D765AC-2 */
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MCFG_UPD765A_ADD(FDC_TAG, true, true)
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MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pdc_device, fdc_irq))
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MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE(FDCDMA_TAG, am9517a_device, dreq0_w)) //MCFG_DEVCB_INVERT
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// Floppy disk drive
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MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", pdc_device::floppy_formats)
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/* DMA Controller - Intel P8237A-5 */
|
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/* Channel 0: uPD765a Floppy Disk Controller */
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/* Channel 1: M68K main system memory */
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MCFG_DEVICE_ADD(FDCDMA_TAG, AM9517A, XTAL_10MHz / 2)
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MCFG_I8237_OUT_HREQ_CB(WRITELINE(pdc_device, i8237_hreq_w))
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MCFG_I8237_OUT_EOP_CB(WRITELINE(pdc_device, i8237_eop_w))
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MCFG_I8237_IN_MEMR_CB(READ8(pdc_device, i8237_dma_mem_r))
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MCFG_I8237_OUT_MEMW_CB(WRITE8(pdc_device, i8237_dma_mem_w))
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MCFG_I8237_IN_IOR_0_CB(READ8(pdc_device, i8237_fdc_dma_r))
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MCFG_I8237_OUT_IOW_0_CB(WRITE8(pdc_device, i8237_fdc_dma_w))
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MCFG_I8237_IN_IOR_1_CB(READ8(pdc_device, m68k_dma_r))
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MCFG_I8237_OUT_IOW_1_CB(WRITE8(pdc_device, m68k_dma_w))
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/* Hard Disk Controller - HDC9224 */
|
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MCFG_DEVICE_ADD(HDC_TAG, HDC9224, 0)
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MCFG_MFM_HARDDISK_CONN_ADD("h1", pdc_harddisks, NULL, MFM_BYTE, 3000, 20, MFMHD_GEN_FORMAT)
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MACHINE_CONFIG_END
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//-------------------------------------------------
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// machine_config_additions - device-specific
|
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// machine configurations
|
||||
//-------------------------------------------------
|
||||
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machine_config_constructor pdc_device::device_mconfig_additions() const
|
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{
|
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return MACHINE_CONFIG_NAME( pdc );
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}
|
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|
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ioport_constructor pdc_device::device_input_ports() const
|
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{
|
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return INPUT_PORTS_NAME( pdc_ports );
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}
|
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|
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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|
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//-------------------------------------------------
|
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// pdc_device - constructor
|
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//-------------------------------------------------
|
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|
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pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__),
|
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m_pdccpu(*this, Z80_TAG),
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m_dma8237(*this, FDCDMA_TAG),
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m_fdc(*this, FDC_TAG),
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m_hdc9224(*this, HDC_TAG),
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m_pdc_ram(*this, "pdc_ram"),
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m_m68k_r_cb(*this),
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m_m68k_w_cb(*this)
|
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{
|
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}
|
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|
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//-------------------------------------------------
|
||||
// device_start - device-specific startup
|
||||
//-------------------------------------------------
|
||||
|
||||
void pdc_device::device_start()
|
||||
{
|
||||
}
|
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|
||||
//-------------------------------------------------
|
||||
// device_reset - device-specific reset
|
||||
//-------------------------------------------------
|
||||
|
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void pdc_device::device_reset()
|
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{
|
||||
/* Reset registers */
|
||||
reg_p38 = 0;
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reg_p38 |= 4; /* ready for 68k ram DMA */
|
||||
//reg_p38 |= 0x20; // no idea at all - bit 5 (32)
|
||||
|
||||
/* Reset CPU */
|
||||
m_pdccpu->reset();
|
||||
|
||||
/* Resolve callbacks */
|
||||
m_m68k_r_cb.resolve_safe(0);
|
||||
m_m68k_w_cb.resolve_safe();
|
||||
|
||||
m_fdc->set_rate(500000) ;
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
// I8237 DMA
|
||||
//-------------------------------------------------
|
||||
|
||||
WRITE_LINE_MEMBER(pdc_device::i8237_hreq_w)
|
||||
{
|
||||
m_pdccpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_dma8237->hack_w(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(pdc_device::i8237_eop_w)
|
||||
{
|
||||
m_fdc->tc_w(state);
|
||||
reg_p38 |= 4; /* ready for 68k ram DMA */
|
||||
if(state) m_dma8237->dreq1_w(0);
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::i8237_dma_mem_r)
|
||||
{
|
||||
return m_pdccpu->space(AS_PROGRAM).read_byte(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::i8237_dma_mem_w)
|
||||
{
|
||||
m_pdccpu->space(AS_PROGRAM).write_byte(offset,data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::i8237_fdc_dma_r)
|
||||
{
|
||||
UINT8 ret = m_fdc->dma_r();
|
||||
if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 READ ADDRESS: %08X, DATA: %02X\n", offset, ret );
|
||||
return ret;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::i8237_fdc_dma_w)
|
||||
{
|
||||
if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
|
||||
m_fdc->dma_w(data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::m68k_dma_r)
|
||||
{
|
||||
UINT32 address;
|
||||
UINT8 data;
|
||||
|
||||
address = fdd_68k_dma_address++;
|
||||
data = m_m68k_r_cb(address);
|
||||
if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::m68k_dma_w)
|
||||
{
|
||||
if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", fdd_68k_dma_address, data );
|
||||
m_m68k_w_cb(data);
|
||||
fdd_68k_dma_address++;
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(pdc_device::hdd_irq)
|
||||
{
|
||||
m_pdccpu->set_input_line(INPUT_LINE_IRQ0, HOLD_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(pdc_device::fdc_irq)
|
||||
{
|
||||
b_fdc_irq = state != 0;
|
||||
}
|
||||
READ8_MEMBER(pdc_device::p0_7_r)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
case 0: /* Port 0: Old style command low byte [0x5FF041B0] */
|
||||
if(TRACE_PDC_CMD) logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
|
||||
return reg_p0;
|
||||
case 1: /* Port 1: Old style command high byte [0x5FF041B0] */
|
||||
if(TRACE_PDC_CMD) logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
|
||||
return reg_p1;
|
||||
case 2: /* Port 2: FDD command address low byte [0x5FF0C0B0][0x5FF0C1B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
|
||||
return reg_p2;
|
||||
case 3: /* Port 3: FDD command address high byte [0x5FF0C0B0][0x5FF0C1B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
|
||||
return reg_p3;
|
||||
case 6: /* Port 6: FDD data destination address low byte [0x5FF080B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x06 READ: %02X\n", reg_p6);
|
||||
return reg_p6;
|
||||
case 7: /* Port 7: FDD data destination address high byte [0x5FF080B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x07 READ: %02X\n", reg_p7);
|
||||
return reg_p7;
|
||||
default:
|
||||
if(TRACE_PDC_CMD) logerror("(!)PDC: Port %02X READ: \n", offset);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::p0_7_w)
|
||||
{
|
||||
switch(offset)
|
||||
{
|
||||
case 4: /* Port 4: FDD command completion status low byte [0x5FF030B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x04 WRITE: %02X\n", data);
|
||||
reg_p4 = data;
|
||||
break;
|
||||
case 5: /* Port 5: FDD command completion status high byte [0x5FF030B0] */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x05 WRITE: %02X\n", data);
|
||||
reg_p5 = data;
|
||||
break;
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X\n", offset, data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::fdd_68k_r)
|
||||
{
|
||||
UINT8 address = offset + 0x21;
|
||||
switch(address)
|
||||
{
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X READ: \n", address);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
WRITE8_MEMBER(pdc_device::fdd_68k_w)
|
||||
{
|
||||
UINT8 address = offset + 0x21;
|
||||
switch(address)
|
||||
{
|
||||
case 0x21: /* Port 21: ?? */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x21 WRITE: %02X\n", data);
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1\n");
|
||||
reg_p38 &= ~2; // Clear bit 1
|
||||
reg_p21 = data;
|
||||
break;
|
||||
case 0x23: /* Port 23: FDD 68k DMA high byte */
|
||||
/* The address is << 1 on the 68k side */
|
||||
fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<1)) | (data << 9);
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
|
||||
break;
|
||||
case 0x24: /* Port 24: FDD 68k DMA low byte */
|
||||
/* The address is << 1 on the 68k side */
|
||||
fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<9)) | (data << 1);
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
|
||||
break;
|
||||
case 0x26:
|
||||
switch(data)
|
||||
{
|
||||
case 0x80:
|
||||
m_dma8237->dreq1_w(1);
|
||||
reg_p38 &= ~4; // Clear bit 4
|
||||
if(TRACE_PDC_DMA) logerror("PDC: Port 0x26 WRITE: 0x80, DMA REQ CH 1\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 0x2C:
|
||||
switch(data)
|
||||
{
|
||||
case 0xFF:
|
||||
m_dma8237->dreq1_w(0);
|
||||
if(TRACE_PDC_DMA) logerror("PDC: Port 0x2C WRITE: 0xFF, DMA REQ CH 1 OFF\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X, PC: %X\n", address, data, space.device().safe_pc());
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::p38_w)
|
||||
{
|
||||
if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 WRITE: %i\n", data);
|
||||
//reg_p38 |= data;
|
||||
reg_p38 = data;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::p38_r)
|
||||
{
|
||||
reg_p38 ^= 0x20; /* Invert bit 5 (32) */
|
||||
if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 READ: %02X, PC: %X\n", reg_p38, space.device().safe_pc());
|
||||
return reg_p38;
|
||||
}
|
||||
|
||||
READ8_MEMBER(pdc_device::p39_r)
|
||||
{
|
||||
UINT8 data = 1;
|
||||
if(b_fdc_irq) data |= 8; // Set bit 3
|
||||
if(TRACE_PDC_CMD) logerror("PDC: Port 0x39 READ: %02X, PC: %X\n", data, space.device().safe_pc());
|
||||
return data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(pdc_device::p50_5f_w)
|
||||
{
|
||||
UINT8 address = 0x50 + offset;
|
||||
switch(address)
|
||||
{
|
||||
case 0x52:
|
||||
switch(data)
|
||||
{
|
||||
case 0x00:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor off.\n");
|
||||
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
|
||||
break;
|
||||
case 0x80:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor on.\n");
|
||||
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
|
||||
break;
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x52 WRITE: %x\n", data);
|
||||
}
|
||||
break;
|
||||
case 0x53: /* Probably set_rate here */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x53 WRITE: %x\n", data);
|
||||
break;
|
||||
case 0x54: /* Port 54: FDD Unit 1 Motor control */
|
||||
switch(data)
|
||||
{
|
||||
case 0x00:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor off.\n");
|
||||
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
|
||||
break;
|
||||
case 0x80:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor on.\n");
|
||||
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
|
||||
break;
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port 0x54 WRITE: %x\n", data);
|
||||
}
|
||||
break;
|
||||
case 0x55: /* Port 54: FDD Unit 2 Motor control */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD 2 motor control: %02X\n", data);
|
||||
break;
|
||||
case 0x56: /* Port 54: FDD Unit 3 Motor control */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD 3 motor control: %02X\n", data);
|
||||
break;
|
||||
case 0x57: /* Port 54: FDD Unit 4 Motor control */
|
||||
if(TRACE_PDC_FDC) logerror("PDC: FDD 4 motor control: %02X\n", data);
|
||||
break;
|
||||
default:
|
||||
if(TRACE_PDC_FDC) logerror("PDC: Port %02x WRITE: %x\n", address, data);
|
||||
}
|
||||
}
|
||||
118
src/devices/machine/pdc.h
Normal file
118
src/devices/machine/pdc.h
Normal file
@ -0,0 +1,118 @@
|
||||
// license:GPL-2.0+
|
||||
// copyright-holders:Brandon Munger
|
||||
/**********************************************************************
|
||||
|
||||
ROLM 9751 9005 Peripheral device controller emulation
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __R9751_PDC_H__
|
||||
#define __R9751_PDC_H__
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/z80/z80.h"
|
||||
#include "machine/upd765.h"
|
||||
#include "machine/am9517a.h"
|
||||
#include "formats/pc_dsk.h"
|
||||
#include "machine/hdc92x4.h"
|
||||
#include "imagedev/mfmhd.h"
|
||||
|
||||
//**************************************************************************
|
||||
// MACROS / CONSTANTS
|
||||
//**************************************************************************
|
||||
|
||||
#define PDC_TAG "pdc"
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> pdc_device
|
||||
|
||||
class pdc_device : public device_t
|
||||
{
|
||||
public:
|
||||
/* Constructor and Destructor */
|
||||
pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
/* Optional information overrides */
|
||||
virtual machine_config_constructor device_mconfig_additions() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual const rom_entry *device_rom_region() const override;
|
||||
|
||||
/* Callbacks */
|
||||
template<class _Object> static devcb_base &m68k_r_callback(device_t &device, _Object object) { return downcast<pdc_device &>(device).m_m68k_r_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &m68k_w_callback(device_t &device, _Object object) { return downcast<pdc_device &>(device).m_m68k_w_cb.set_callback(object); }
|
||||
|
||||
/* Read and Write members */
|
||||
DECLARE_WRITE_LINE_MEMBER(i8237_hreq_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(i8237_eop_w);
|
||||
DECLARE_READ8_MEMBER(i8237_dma_mem_r);
|
||||
DECLARE_WRITE8_MEMBER(i8237_dma_mem_w);
|
||||
DECLARE_READ8_MEMBER(i8237_fdc_dma_r);
|
||||
DECLARE_WRITE8_MEMBER(i8237_fdc_dma_w);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(hdd_irq);
|
||||
|
||||
DECLARE_READ8_MEMBER(p0_7_r);
|
||||
DECLARE_WRITE8_MEMBER(p0_7_w);
|
||||
DECLARE_READ8_MEMBER(fdd_68k_r);
|
||||
DECLARE_WRITE8_MEMBER(fdd_68k_w);
|
||||
DECLARE_WRITE8_MEMBER(p38_w);
|
||||
DECLARE_READ8_MEMBER(p38_r);
|
||||
DECLARE_READ8_MEMBER(p39_r);
|
||||
DECLARE_WRITE8_MEMBER(p50_5f_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(m68k_dma_r);
|
||||
DECLARE_WRITE8_MEMBER(m68k_dma_w);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(fdc_irq);
|
||||
DECLARE_FLOPPY_FORMATS( floppy_formats );
|
||||
|
||||
/* Main CPU accessible registers */
|
||||
UINT8 reg_p0;
|
||||
UINT8 reg_p1;
|
||||
UINT8 reg_p2;
|
||||
UINT8 reg_p3;
|
||||
UINT8 reg_p4;
|
||||
UINT8 reg_p5;
|
||||
UINT8 reg_p6;
|
||||
UINT8 reg_p7;
|
||||
UINT8 reg_p21;
|
||||
UINT8 reg_p38;
|
||||
UINT32 fdd_68k_dma_address; /* FDD <-> m68k DMA read/write address */
|
||||
protected:
|
||||
/* Device-level overrides */
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
/* Protected variables */
|
||||
//UINT32 fdd_68k_dma_address;
|
||||
bool b_fdc_irq;
|
||||
|
||||
/* Attached devices */
|
||||
required_device<cpu_device> m_pdccpu;
|
||||
required_device<am9517a_device> m_dma8237;
|
||||
required_device<upd765a_device> m_fdc;
|
||||
//required_device<floppy_connector> m_floppy;
|
||||
//required_device<floppy_image_device> m_floppy;
|
||||
optional_device<hdc9224_device> m_hdc9224;
|
||||
mfm_harddisk_device* m_harddisk;
|
||||
required_shared_ptr<UINT8> m_pdc_ram;
|
||||
|
||||
/* Callbacks */
|
||||
devcb_read8 m_m68k_r_cb;
|
||||
devcb_write8 m_m68k_w_cb;
|
||||
};
|
||||
|
||||
/* Device type */
|
||||
extern const device_type PDC;
|
||||
|
||||
/* MCFG defines */
|
||||
#define MCFG_PDC_R_CB(_devcb) \
|
||||
devcb = &pdc_device::m68k_r_callback(*device, DEVCB_##_devcb);
|
||||
#define MCFG_PDC_W_CB(_devcb) \
|
||||
devcb = &pdc_device::m68k_w_callback(*device, DEVCB_##_devcb);
|
||||
#endif
|
||||
448
src/mame/drivers/r9751.cpp
Normal file
448
src/mame/drivers/r9751.cpp
Normal file
@ -0,0 +1,448 @@
|
||||
// license:GPL-2.0+
|
||||
// copyright-holders:Brandon Munger
|
||||
/******************************************************************************
|
||||
*
|
||||
* Rolm CBX 9751 Driver
|
||||
*
|
||||
* This driver attempts to emulate the following models:
|
||||
* * Model 10
|
||||
* * Model 20
|
||||
* * Model 40
|
||||
* * Model 50
|
||||
* * Model 70
|
||||
*
|
||||
* The following software releases are known:
|
||||
* * 9004
|
||||
* * 9005
|
||||
*
|
||||
* The basis of this driver was influenced by the zexall.c driver by
|
||||
* Jonathan Gevaryahu and Robbbert.
|
||||
*
|
||||
*
|
||||
* Special Thanks to:
|
||||
* * Stephen Stair (sgstair) - for help with reverse engineering,
|
||||
* programming, and emulation
|
||||
* * Felipe Sanches (FSanches) - for help with MESS and emulation
|
||||
* * Michael Zapf (mizapf) - for building the HDC9234/HDC9224
|
||||
* driver that makes this driver possible
|
||||
*
|
||||
* Memory map:
|
||||
* * 0x00000000 - 0x00ffffff : RAM 12MB to 16MB known, up to 128MB?
|
||||
* * 0x08000000 - 0x0800ffff : PROM Region
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/* Core includes */
|
||||
#include "emu.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/terminal.h"
|
||||
|
||||
#include "bus/scsi/scsi.h"
|
||||
#include "machine/wd33c93.h"
|
||||
|
||||
#include "machine/pdc.h"
|
||||
|
||||
#define TERMINAL_TAG "terminal"
|
||||
|
||||
/* Log defines */
|
||||
#define TRACE_FDC 0
|
||||
#define TRACE_HDC 0
|
||||
#define TRACE_SMIOC 0
|
||||
#define TRACE_CPU_REG 0
|
||||
#define TRACE_LED 0
|
||||
|
||||
class r9751_state : public driver_device
|
||||
{
|
||||
public:
|
||||
r9751_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_pdc(*this, "pdc"),
|
||||
m_wd33c93(*this, "wd33c93"),
|
||||
m_terminal(*this, TERMINAL_TAG),
|
||||
m_main_ram(*this, "main_ram")
|
||||
{
|
||||
}
|
||||
|
||||
DECLARE_READ32_MEMBER(r9751_mmio_5ff_r);
|
||||
DECLARE_WRITE32_MEMBER(r9751_mmio_5ff_w);
|
||||
DECLARE_READ32_MEMBER(r9751_mmio_ff05_r);
|
||||
DECLARE_WRITE32_MEMBER(r9751_mmio_ff05_w);
|
||||
DECLARE_READ32_MEMBER(r9751_mmio_fff8_r);
|
||||
DECLARE_WRITE32_MEMBER(r9751_mmio_fff8_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(pdc_dma_r);
|
||||
DECLARE_WRITE8_MEMBER(pdc_dma_w);
|
||||
|
||||
DECLARE_DRIVER_INIT(r9751);
|
||||
|
||||
//DECLARE_FLOPPY_FORMATS( floppy_formats );
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<pdc_device> m_pdc;
|
||||
required_device<wd33c93_device> m_wd33c93;
|
||||
required_device<generic_terminal_device> m_terminal;
|
||||
required_shared_ptr<UINT32> m_main_ram;
|
||||
|
||||
// Begin registers
|
||||
UINT32 reg_ff050004;
|
||||
UINT32 reg_ff050320; // Counter?
|
||||
UINT32 reg_fff80040;
|
||||
UINT32 fdd_dest_address; // 5FF080B0
|
||||
UINT32 fdd_cmd_complete;
|
||||
UINT32 smioc_out_addr;
|
||||
// End registers
|
||||
|
||||
// UINT32 fdd_scsi_command;
|
||||
address_space *m_mem;
|
||||
|
||||
// functions
|
||||
UINT32 swap_uint32( UINT32 val );
|
||||
|
||||
virtual void machine_reset() override;
|
||||
};
|
||||
|
||||
|
||||
UINT32 r9751_state::swap_uint32( UINT32 val )
|
||||
{
|
||||
val = ((val << 8) & 0xFF00FF00 ) | ((val >> 8) & 0xFF00FF );
|
||||
return (val << 16) | (val >> 16);
|
||||
}
|
||||
|
||||
READ8_MEMBER(r9751_state::pdc_dma_r)
|
||||
{
|
||||
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(r9751_state::pdc_dma_w)
|
||||
{
|
||||
/* NOTE: This needs to be changed to a function that accepts an address and data */
|
||||
m_maincpu->space(AS_PROGRAM).write_byte(m_pdc->fdd_68k_dma_address,data);
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(r9751_state,r9751)
|
||||
{
|
||||
reg_ff050004 = 0;
|
||||
reg_ff050320 = 1;
|
||||
reg_fff80040 = 0;
|
||||
fdd_dest_address = 0;
|
||||
// fdd_scsi_command = 0;
|
||||
fdd_cmd_complete = 0;
|
||||
smioc_out_addr = 0;
|
||||
m_mem = &m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
}
|
||||
|
||||
void r9751_state::machine_reset()
|
||||
{
|
||||
UINT8 *rom = memregion("prom")->base();
|
||||
UINT32 *ram = m_main_ram;
|
||||
|
||||
memcpy(ram, rom, 8);
|
||||
|
||||
m_maincpu->reset();
|
||||
m_pdc->reset();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
External board communication registers [0x5FF00000 - 0x5FFFFFFF]
|
||||
******************************************************************************/
|
||||
READ32_MEMBER( r9751_state::r9751_mmio_5ff_r )
|
||||
{
|
||||
UINT32 data;
|
||||
UINT32 address = offset * 4 + 0x5FF00000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
/* PDC HDD region (0x24, device 9) */
|
||||
case 0x5FF00824: /* HDD Command result code */
|
||||
return 0x10;
|
||||
break;
|
||||
case 0x5FF03024: /* HDD SCSI command completed successfully */
|
||||
data = 0x1;
|
||||
if(TRACE_HDC) logerror("SCSI HDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
return data;
|
||||
break;
|
||||
/* SMIOC region (0x98, device 26) */
|
||||
case 0x5FF00898: /* Serial status or DMA status */
|
||||
return 0x40;
|
||||
break;
|
||||
/* PDC FDD region (0xB0, device 44 */
|
||||
case 0x5FF008B0: /* FDD Command result code */
|
||||
return 0x10;
|
||||
break;
|
||||
case 0x5FF010B0: /* Clear 5FF030B0 ?? */
|
||||
if(TRACE_FDC) logerror("--- FDD 0x5FF010B0 READ (0)\n");
|
||||
return 0;
|
||||
case 0x5FF030B0: /* FDD command completion status */
|
||||
data = (m_pdc->reg_p5 << 8) + m_pdc->reg_p4;
|
||||
if(TRACE_FDC) logerror("--- SCSI FDD command completion status - Read: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
return data;
|
||||
break;
|
||||
default:
|
||||
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, 0, mem_mask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
|
||||
{
|
||||
UINT8 data_b0, data_b1;
|
||||
UINT32 address = offset * 4 + 0x5FF00000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
/* PDC HDD region (0x24, device 9 */
|
||||
case 0x5FF00224: /* HDD SCSI read command */
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF08024: /* HDD SCSI read command */
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF0C024: /* HDD SCSI read command */
|
||||
if(TRACE_HDC) logerror("@@@ HDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
/* SMIOC region (0x98, device 26) */
|
||||
case 0x5FF04098: /* Serial DMA Command */
|
||||
switch(data)
|
||||
{
|
||||
case 0x4100: /* Send byte to serial */
|
||||
if(TRACE_SMIOC) logerror("Serial byte: %02X\n", m_mem->read_dword(smioc_out_addr));
|
||||
m_terminal->write(space,0,m_mem->read_dword(smioc_out_addr));
|
||||
break;
|
||||
default:
|
||||
if(TRACE_SMIOC) logerror("Uknown serial DMA command: %X\n", data);
|
||||
}
|
||||
break;
|
||||
case 0x5FF0C098: /* Serial DMA output address */
|
||||
smioc_out_addr = data * 2;
|
||||
break;
|
||||
/* PDC FDD region (0xB0, device 44 */
|
||||
case 0x5FF001B0: /* FDD SCSI read command */
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF002B0: /* FDD SCSI read command */
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF008B0: /* FDD SCSI read command */
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
break;
|
||||
case 0x5FF041B0: /* Unknown - Probably old style commands */
|
||||
if(TRACE_FDC) logerror("--- FDD Command: %08X, From: %08X, Register: %08X\n", data, space.machine().firstcpu->pc(), address);
|
||||
|
||||
/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5)*/
|
||||
m_pdc->reg_p4 = 0;
|
||||
m_pdc->reg_p5 = 0;
|
||||
|
||||
data_b0 = data & 0xFF;
|
||||
data_b1 = (data & 0xFF00) >> 8;
|
||||
m_pdc->reg_p0 = data_b0;
|
||||
m_pdc->reg_p1 = data_b1;
|
||||
m_pdc->reg_p38 |= 0x2; /* Set bit 1 on port 38 register, PDC polls this port looking for a command */
|
||||
if(TRACE_FDC) logerror("--- FDD Old Command: %02X and %02X\n", data_b0, data_b1);
|
||||
break;
|
||||
case 0x5FF080B0: /* fdd_dest_address register */
|
||||
fdd_dest_address = data << 1;
|
||||
if(TRACE_FDC) logerror("--- FDD destination address: %08X\n", fdd_dest_address);
|
||||
data_b0 = data & 0xFF;
|
||||
data_b1 = (data & 0xFF00) >> 8;
|
||||
m_pdc->reg_p6 = data_b0;
|
||||
m_pdc->reg_p7 = data_b1;
|
||||
break;
|
||||
case 0x5FF0C0B0:
|
||||
case 0x5FF0C1B0: /* FDD command address register */
|
||||
UINT32 fdd_scsi_command;
|
||||
UINT32 fdd_scsi_command2;
|
||||
unsigned char c_fdd_scsi_command[8]; // Array for SCSI command
|
||||
int scsi_lba; // FDD LBA location here, extracted from command
|
||||
|
||||
/* Clear FDD Command completion status 0x5FF030B0 (PDC 0x4, 0x5)*/
|
||||
m_pdc->reg_p4 = 0;
|
||||
m_pdc->reg_p5 = 0;
|
||||
|
||||
/* Send FDD SCSI command location address to PDC 0x2, 0x3 */
|
||||
if(TRACE_FDC) logerror("--- FDD command address: %08X\n", data);
|
||||
data_b0 = data & 0xFF;
|
||||
data_b1 = (data & 0xFF00) >> 8;
|
||||
m_pdc->reg_p2 = data_b0;
|
||||
m_pdc->reg_p3 = data_b1;
|
||||
|
||||
fdd_scsi_command = swap_uint32(m_mem->read_dword(data << 1));
|
||||
fdd_scsi_command2 = swap_uint32(m_mem->read_dword((data << 1)+4));
|
||||
|
||||
memcpy(c_fdd_scsi_command,&fdd_scsi_command,4);
|
||||
memcpy(c_fdd_scsi_command+4,&fdd_scsi_command2,4);
|
||||
|
||||
if(TRACE_FDC)
|
||||
{
|
||||
logerror("--- FDD SCSI Command: ");
|
||||
for(int i = 0; i < 8; i++)
|
||||
logerror("%02X ", c_fdd_scsi_command[i]);
|
||||
logerror("\n");
|
||||
}
|
||||
|
||||
scsi_lba = c_fdd_scsi_command[3] | (c_fdd_scsi_command[2]<<8) | ((c_fdd_scsi_command[1]&0x1F)<<16);
|
||||
if(TRACE_FDC) logerror("--- FDD SCSI LBA: %i\n", scsi_lba);
|
||||
|
||||
m_pdc->reg_p38 |= 0x2; // Set bit 1 on port 38 register, PDC polls this port looking for a command
|
||||
if(TRACE_FDC)logerror("--- FDD SET PDC Port 38: %X\n",m_pdc->reg_p38);
|
||||
break;
|
||||
|
||||
default:
|
||||
if(TRACE_FDC || TRACE_HDC || TRACE_SMIOC) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
CPU board registers [0xFF050000 - 0xFF06FFFF]
|
||||
******************************************************************************/
|
||||
READ32_MEMBER( r9751_state::r9751_mmio_ff05_r )
|
||||
{
|
||||
UINT32 data;
|
||||
UINT32 address = offset * 4 + 0xFF050000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
case 0xFF050004:
|
||||
return reg_ff050004;
|
||||
break;
|
||||
case 0xFF050300:
|
||||
return 0x1B | (1<<0x14);
|
||||
break;
|
||||
case 0xFF050320: /* Some type of counter */
|
||||
reg_ff050320++;
|
||||
return reg_ff050320;
|
||||
break;
|
||||
case 0xFF050584:
|
||||
return 0;
|
||||
break;
|
||||
case 0xFF050610:
|
||||
return 0xabacabac;
|
||||
break;
|
||||
case 0xFF060014:
|
||||
return 0x80;
|
||||
break;
|
||||
default:
|
||||
data = 0;
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return data;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( r9751_state::r9751_mmio_ff05_w )
|
||||
{
|
||||
UINT32 address = offset * 4 + 0xFF050000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
case 0xFF050004:
|
||||
reg_ff050004 = data;
|
||||
return;
|
||||
break;
|
||||
case 0xFF05000C: /* CPU LED hex display indicator */
|
||||
if(TRACE_LED) logerror("\n*** LED: %02x, Instruction: %08x ***\n\n", data, space.machine().firstcpu->pc());
|
||||
return;
|
||||
break;
|
||||
default:
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER( r9751_state::r9751_mmio_fff8_r )
|
||||
{
|
||||
UINT32 data;
|
||||
UINT32 address = offset * 4 + 0xFFF80000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
case 0xFFF80040:
|
||||
return reg_fff80040;
|
||||
break;
|
||||
default:
|
||||
data = 0;
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x READ MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
return data;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( r9751_state::r9751_mmio_fff8_w )
|
||||
{
|
||||
UINT32 address = offset * 4 + 0xFFF80000;
|
||||
|
||||
switch(address)
|
||||
{
|
||||
case 0xFFF80040:
|
||||
reg_fff80040 = data;
|
||||
return;
|
||||
break;
|
||||
default:
|
||||
if(TRACE_CPU_REG) logerror("Instruction: %08x WRITE MMIO(%08x): %08x & %08x\n", space.machine().firstcpu->pc(), address, data, mem_mask);
|
||||
}
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
Address Maps
|
||||
******************************************************************************/
|
||||
|
||||
static ADDRESS_MAP_START(r9751_mem, AS_PROGRAM, 32, r9751_state)
|
||||
//ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x00000000,0x00ffffff) AM_RAM AM_SHARE("main_ram") // 16MB
|
||||
//AM_RANGE(0x01000000,0x07ffffff) AM_NOP
|
||||
AM_RANGE(0x08000000,0x0800ffff) AM_ROM AM_REGION("prom", 0)
|
||||
AM_RANGE(0x5FF00000,0x5FFFFFFF) AM_READWRITE(r9751_mmio_5ff_r, r9751_mmio_5ff_w)
|
||||
AM_RANGE(0xFF050000,0xFF06FFFF) AM_READWRITE(r9751_mmio_ff05_r, r9751_mmio_ff05_w)
|
||||
AM_RANGE(0xFFF80000,0xFFF8FFFF) AM_READWRITE(r9751_mmio_fff8_r, r9751_mmio_fff8_w)
|
||||
//AM_RANGE(0xffffff00,0xffffffff) AM_RAM // Unknown area
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/******************************************************************************
|
||||
Input Ports
|
||||
******************************************************************************/
|
||||
static INPUT_PORTS_START( r9751 )
|
||||
INPUT_PORTS_END
|
||||
|
||||
/******************************************************************************
|
||||
Machine Drivers
|
||||
******************************************************************************/
|
||||
|
||||
static MACHINE_CONFIG_START( r9751, r9751_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68030, 20000000)
|
||||
MCFG_CPU_PROGRAM_MAP(r9751_mem)
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(60))
|
||||
|
||||
/* video hardware */
|
||||
MCFG_DEVICE_ADD(TERMINAL_TAG, GENERIC_TERMINAL, 0)
|
||||
|
||||
/* disk hardware */
|
||||
MCFG_DEVICE_ADD("pdc", PDC, 0)
|
||||
MCFG_PDC_R_CB(READ8(r9751_state, pdc_dma_r))
|
||||
MCFG_PDC_W_CB(WRITE8(r9751_state, pdc_dma_w))
|
||||
MCFG_DEVICE_ADD("scsi", SCSI_PORT, 0)
|
||||
//MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE1, "cdrom", SCSICD, SCSI_ID_1)
|
||||
MCFG_DEVICE_ADD("wd33c93", WD33C93, 0)
|
||||
MCFG_LEGACY_SCSI_PORT("scsi")
|
||||
//MCFG_WD33C93_IRQ_CB(WRITELINE(r9751_state,scsi_irq))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
ROM Definitions
|
||||
******************************************************************************/
|
||||
|
||||
ROM_START(r9751)
|
||||
ROM_REGION32_BE(0x00010000, "prom", 0)
|
||||
ROM_SYSTEM_BIOS(0, "prom34", "PROM Version 3.4")
|
||||
ROMX_LOAD( "p-n_98d4643__abaco_v3.4__(49fe7a)__j221.27512.bin", 0x0000, 0x10000, CRC(9fb19a85) SHA1(c861e15a2fc9a4ef689c2034c53fbb36f17f7da6), ROM_GROUPWORD | ROM_BIOS(1) ) // Label: "P/N 98D4643 // ABACO V3.4 // (49FE7A) // J221" 27128 @Unknown
|
||||
ROM_END
|
||||
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
Drivers
|
||||
******************************************************************************/
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1988, r9751, 0, 0, r9751, r9751, r9751_state, r9751, "ROLM Systems, Inc.", "ROLM 9751 Model 10", MACHINE_NO_SOUND | MACHINE_NOT_WORKING )
|
||||
@ -2340,7 +2340,7 @@ wildfire // Parker Bros
|
||||
|
||||
ssem // Manchester Small-Scale Experimental Machine, "Baby"
|
||||
craft // Craft, by [lft]
|
||||
|
||||
r9751 // ROLM 9751 phone system
|
||||
|
||||
//********** To sort (mostly skeleton drivers) *****************************
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user