Fix loading roms in two devices. (nl)

This commit is contained in:
couriersud 2016-12-27 04:32:37 +01:00
parent bf1a504545
commit 54cbd67a42
4 changed files with 15 additions and 17 deletions

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@ -118,7 +118,7 @@ static void initialize_factory(factory_list_t &factory)
ENTRYX(7475, TTL_7475, "-")
ENTRYX(7477, TTL_7477, "-")
ENTRYX(7483, TTL_7483, "+A1,A2,A3,A4,B1,B2,B3,B4,C0")
ENTRYX(7485, TTL_7485, "-")
ENTRYX(7485, TTL_7485, "+A0,A1,A2,A3,B0,B1,B2,B3,LTIN,EQIN,GTIN")
ENTRYX(7490, TTL_7490, "+A,B,R1,R2,R91,R92")
ENTRYX(7493, TTL_7493, "+CLKA,CLKB,R1,R2")
ENTRYX(74107, TTL_74107, "+CLK,J,K,CLRQ")
@ -126,24 +126,24 @@ static void initialize_factory(factory_list_t &factory)
ENTRYX(74123, TTL_74123, "-")
ENTRYX(74153, TTL_74153, "+C0,C1,C2,C3,A,B,G")
ENTRYX(74161, TTL_74161, "+A,B,C,D,CLRQ,LOADQ,CLK,ENABLEP,ENABLET")
ENTRYX(74165, TTL_74165, "-")
ENTRYX(74165, TTL_74165, "+CLK,CLKINH,SH_LDQ,SER,A,B,C,D,E,F,G,H")
ENTRYX(74166, TTL_74166, "+CLK,CLKINH,SH_LDQ,SER,A,B,C,D,E,F,G,H,CLRQ")
ENTRYX(74174, TTL_74174, "+CLK,D1,D2,D3,D4,D5,D6,CLRQ")
ENTRYX(74175, TTL_74175, "+CLK,D1,D2,D3,D4,CLRQ")
ENTRYX(74192, TTL_74192, "-")
ENTRYX(74192, TTL_74192, "+A,B,C,D,CLEAR,LOADQ,CU,CD")
ENTRYX(74193, TTL_74193, "+A,B,C,D,CLEAR,LOADQ,CU,CD")
ENTRYX(74194, TTL_74194, "-")
ENTRYX(74194, TTL_74194, "+CLK,S0,S1,SRIN,A,B,C,D,SLIN,CLRQ")
ENTRYX(74365, TTL_74365, "+G1Q,G2Q,A1,A2,A3,A4,A5,A6")
//ENTRY(74279, TTL_74279, "-") // only dip available
ENTRYX(SN74LS629, SN74LS629, "CAP")
ENTRYX(82S16, TTL_82S16, "-")
ENTRYX(82S115, PROM_82S115, "-")
ENTRYX(82S123, PROM_82S123, "-")
ENTRYX(82S115, PROM_82S115, "+CE1Q,CE2,A0,A1,A2,A3,A4,A5,A6,A7,A8,STROBE")
ENTRYX(82S123, PROM_82S123, "+CEQ,A0,A1,A2,A3,A4")
ENTRYX(82S126, PROM_82S126, "+CE1Q,CE2Q,A0,A1,A2,A3,A4,A5,A6,A7")
ENTRYX(9310, TTL_9310, "-")
ENTRYX(9312, TTL_9312, "-")
ENTRYX(9312, TTL_9312, "+A,B,C,D0,D1,D2,D3,D4,D5,D6,D7,G")
ENTRYX(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
ENTRYX(9322, TTL_9322, "-")
ENTRYX(9322, TTL_9322, "+SELECT,A1,B1,A2,B2,A3,B3,A4,B4,STROBE")
ENTRYX(9334, TTL_9334, "+CQ,EQ,D,A0,A1,A2")
ENTRYX(AM2847, TTL_AM2847, "+CP,INA,INB,INC,IND,RCA,RCB,RCC,RCD")
ENTRYX(CD4020, CD4020, "")

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@ -20,7 +20,7 @@ namespace netlist
, m_STROBE(*this, "STROBE")
, m_O(*this, {{"O1", "O2", "O3", "O4", "O5", "O6", "O7", "O8"}})
, m_last_O(*this, "m_last_O", 0)
, m_ROM(*this, "m_ROM", nullptr)
, m_ROM(*this, "ROM")
{
}
@ -36,7 +36,7 @@ namespace netlist
state_var<unsigned> m_last_O;
param_ptr_t m_ROM; // 4096 bits, 512x8
param_rom_t<uint8_t, 9, 8> m_ROM; // 4096 bits, 512x8
};
NETLIB_OBJECT_DERIVED(82S115_dip, 82S115)
@ -90,8 +90,7 @@ namespace netlist
for (std::size_t i=0; i<9; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
o = m_ROM[a];
}
else
{

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@ -17,7 +17,7 @@ namespace netlist
, m_A(*this, {{"A0", "A1", "A2", "A3", "A4"}})
, m_CEQ(*this, "CEQ")
, m_O(*this, {{"O1", "O2", "O3", "O4", "O5", "O6", "O7", "O8"}})
, m_ROM(*this, "m_ROM", nullptr)
, m_ROM(*this, "ROM")
{
}
@ -28,7 +28,7 @@ namespace netlist
logic_input_t m_CEQ;
object_array_t<logic_output_t, 8> m_O;
param_ptr_t m_ROM; // 256 bits, 32x8
param_rom_t<uint8_t, 5, 8> m_ROM; // 256 bits, 32x8
};
NETLIB_OBJECT_DERIVED(82S123_dip, 82S123)
@ -66,8 +66,7 @@ namespace netlist
for (std::size_t i=0; i<5; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
o = m_ROM[a];
delay = NLTIME_FROM_NS(50);
}

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@ -222,7 +222,7 @@ void setup_t::register_and_set_param(pstring name, param_t &param)
break;
case param_t::STRING:
{
static_cast<param_str_t &>(param).initial(val);
static_cast<param_str_base_t &>(param).initial(val);
}
break;
default: