From 552d0d0fc27f188ac58309162bb97e3546a6a487 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Banaan=20Ananas?= Date: Wed, 29 May 2013 04:37:43 +0000 Subject: [PATCH] added new 7200 FIFO chip device --- .gitattributes | 2 + src/emu/emu.mak | 1 + src/emu/machine/7200fifo.c | 130 +++++++++++++++++++++++++++++++++++ src/emu/machine/7200fifo.h | 137 +++++++++++++++++++++++++++++++++++++ src/mame/drivers/zn.c | 76 ++++++-------------- 5 files changed, 291 insertions(+), 55 deletions(-) create mode 100644 src/emu/machine/7200fifo.c create mode 100644 src/emu/machine/7200fifo.h diff --git a/.gitattributes b/.gitattributes index 93c358a8f99..a79e094683f 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1148,6 +1148,8 @@ src/emu/machine/6850acia.c svneol=native#text/plain src/emu/machine/6850acia.h svneol=native#text/plain src/emu/machine/68681.c svneol=native#text/plain src/emu/machine/68681.h svneol=native#text/plain +src/emu/machine/7200fifo.c svneol=native#text/plain +src/emu/machine/7200fifo.h svneol=native#text/plain src/emu/machine/74123.c svneol=native#text/plain src/emu/machine/74123.h svneol=native#text/plain src/emu/machine/74145.c svneol=native#text/plain diff --git a/src/emu/emu.mak b/src/emu/emu.mak index b4a731e78d9..51a11561dcb 100644 --- a/src/emu/emu.mak +++ b/src/emu/emu.mak @@ -152,6 +152,7 @@ EMUMACHINEOBJS = \ $(EMUMACHINE)/6840ptm.o \ $(EMUMACHINE)/6850acia.o \ $(EMUMACHINE)/68681.o \ + $(EMUMACHINE)/7200fifo.o \ $(EMUMACHINE)/74123.o \ $(EMUMACHINE)/74145.o \ $(EMUMACHINE)/74148.o \ diff --git a/src/emu/machine/7200fifo.c b/src/emu/machine/7200fifo.c new file mode 100644 index 00000000000..fa42953035a --- /dev/null +++ b/src/emu/machine/7200fifo.c @@ -0,0 +1,130 @@ +/********************************************************************** + + IDT7200 series 9-bit Asynchronous FIFO Emulation + + TODO: + - retransmit (RT pin) + +**********************************************************************/ + +#include "emu.h" + +#include "machine/7200fifo.h" + + +const device_type FIFO7200 = &device_creator; + +//------------------------------------------------- +// fifo7200_device - constructor +//------------------------------------------------- + +fifo7200_device::fifo7200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : device_t(mconfig, FIFO7200, "IDT7200 Asynchronous FIFO", tag, owner, clock), + m_ram_size(0), + m_ef_handler(*this), + m_ff_handler(*this), + m_hf_handler(*this) +{ +} + +//------------------------------------------------- +// device_start - device-specific startup +//------------------------------------------------- + +void fifo7200_device::device_start() +{ + assert(m_ram_size > 1 && ~m_ram_size & 1); + m_buffer = auto_alloc_array(machine(), UINT16, m_ram_size); + + // resolve callbacks + m_ef_handler.resolve(); + m_ff_handler.resolve(); + m_hf_handler.resolve(); + + // state save + save_item(NAME(m_read_ptr)); + save_item(NAME(m_write_ptr)); + save_item(NAME(m_ef)); + save_item(NAME(m_ff)); + save_item(NAME(m_hf)); +} + +//------------------------------------------------- +// device_reset - device-specific reset +//------------------------------------------------- + +void fifo7200_device::device_reset() +{ + // master reset + memset(m_buffer, 0, m_ram_size * sizeof(UINT16)); + m_read_ptr = 0; + m_write_ptr = 0; + + m_ef = 1; + m_ff = 0; + m_hf = 0; + + if (!m_ef_handler.isnull()) m_ef_handler(m_ef); + if (!m_ff_handler.isnull()) m_ff_handler(m_ff); + if (!m_hf_handler.isnull()) m_hf_handler(m_hf); +} + + + +void fifo7200_device::fifo_write(UINT32 data) +{ + if (m_ff) + return; + + m_buffer[m_write_ptr] = data; + m_write_ptr = (m_write_ptr + 1) % m_ram_size; + + // update flags + if (m_ef) + { + m_ef = 0; + if (!m_ef_handler.isnull()) m_ef_handler(m_ef); + } + + else if (m_read_ptr == m_write_ptr) + { + m_ff = 1; + if (!m_ff_handler.isnull()) m_ff_handler(m_ff); + } + + else if (((m_read_ptr + 1 + m_ram_size / 2) % m_ram_size) == m_write_ptr) + { + m_hf = 1; + if (!m_hf_handler.isnull()) m_hf_handler(m_hf); + } +} + +UINT32 fifo7200_device::fifo_read() +{ + if (m_ef) + return ~0; + + UINT16 ret = m_buffer[m_read_ptr]; + m_read_ptr = (m_read_ptr + 1) % m_ram_size; + + // update flags + if (m_ff) + { + m_ff = 0; + if (!m_ff_handler.isnull()) m_ff_handler(m_ff); + } + + else if (m_read_ptr == m_write_ptr) + { + m_ef = 1; + if (!m_ef_handler.isnull()) m_ef_handler(m_ef); + } + + else if (((m_read_ptr + m_ram_size / 2) % m_ram_size) == m_write_ptr) + { + m_hf = 0; + if (!m_hf_handler.isnull()) m_hf_handler(m_hf); + } + + return ret; +} diff --git a/src/emu/machine/7200fifo.h b/src/emu/machine/7200fifo.h new file mode 100644 index 00000000000..24dd8ee82dc --- /dev/null +++ b/src/emu/machine/7200fifo.h @@ -0,0 +1,137 @@ +/********************************************************************** + + IDT7200 series 9-bit Asynchronous FIFO Emulation + + Copyright MAME Team. + Visit http://mamedev.org for licensing and usage restrictions. + +********************************************************************** + _____ _____ + _W 1 |* \_/ | 28 Vcc + D8 2 | | 27 D4 + D3 3 | | 26 D5 + D2 4 | | 25 D6 + D1 5 | | 24 D7 + D0 6 | | 23 _FL/_RT + _XI 7 | 7200 | 22 _MR + _FF 8 | | 21 _EF + Q0 9 | | 20 _XO/_HF + Q1 10 | | 19 Q7 + Q2 11 | | 18 Q6 + Q3 12 | | 17 Q5 + Q8 13 | | 16 Q4 + GND 14 |_____________| 15 _R + + +Known chips and buffer sizes are listed below. Note that in width or depth +expansion mode (using more than one chip and XO/XI), it may be increased more. + + 256x9 512x9 1Kx9 2Kx9 4Kx9 8Kx9 16Kx9 32Kx9 64Kx9 + ------------------------------------------------------------------------------------------- + IDT7200 IDT7201 IDT7202 IDT7203 IDT7204 IDT7205 IDT7206 IDT7207 IDT7208 + +The following chips are functionally equivalent and pin-compatible. + + AM7200 AM7201 AM7202 AM7203 AM7204 + MS7200 MS7201 MS7202 MS7203 MS7204 + + LH5495 LH5496 LH5497 LH5498 LH5499 + LH540201 LH540202 LH540203 LH540204 LH540205 LH540206 + + CY7C419 CY7C420 CY7C424 CY7C428 CY7C432 + CY7C421 CY7C425 CY7C429 CY7C433 + +32-pin PLCC/LCC or TQFP configurations are also available. + + +**********************************************************************/ + +#pragma once + +#ifndef _7200FIFO_H +#define _7200FIFO_H + +#include "emu.h" + + +//************************************************************************** +// INTERFACE CONFIGURATION MACROS +//************************************************************************** + +#define MCFG_FIFO7200_ADD(_tag, _ramsize) \ + MCFG_DEVICE_ADD(_tag, FIFO7200, 0) \ + fifo7200_device::set_ram_size(*device, _ramsize); + +#define MCFG_FIFO7200_EF_HANDLER(_devcb) \ + devcb = &fifo7200_device::set_ef_handler(*device, DEVCB2_##_devcb); + +#define MCFG_FIFO7200_FF_HANDLER(_devcb) \ + devcb = &fifo7200_device::set_ff_handler(*device, DEVCB2_##_devcb); + +#define MCFG_FIFO7200_HF_HANDLER(_devcb) \ + devcb = &fifo7200_device::set_hf_handler(*device, DEVCB2_##_devcb); + + + +//************************************************************************** +// TYPE DEFINITIONS +//************************************************************************** + +// ======================> fifo7200_device + +class fifo7200_device : public device_t +{ +public: + fifo7200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + // static configuration helpers + template static devcb2_base &set_ef_handler(device_t &device, _Object object) { return downcast(device).m_ef_handler.set_callback(object); } + template static devcb2_base &set_ff_handler(device_t &device, _Object object) { return downcast(device).m_ff_handler.set_callback(object); } + template static devcb2_base &set_hf_handler(device_t &device, _Object object) { return downcast(device).m_hf_handler.set_callback(object); } + static void set_ram_size(device_t &device, int size) { downcast(device).m_ram_size = size; } + + DECLARE_READ_LINE_MEMBER( ef_r ) { return m_ef; } + DECLARE_READ_LINE_MEMBER( ff_r ) { return m_ff; } + DECLARE_READ_LINE_MEMBER( hf_r ) { return m_hf; } + + // normal configuration + DECLARE_WRITE16_MEMBER( data_word_w ) { fifo_write(data); } + DECLARE_READ16_MEMBER( data_word_r ) { return (UINT16)fifo_read(); } + + // use these for simple configurations that don't have d8/q8 connected + DECLARE_WRITE8_MEMBER( data_byte_w ) { fifo_write(data); } + DECLARE_READ8_MEMBER( data_byte_r ) { return (UINT8)fifo_read(); } + + // use these for configurations in cascaded width expansion mode using more than 16 bits + DECLARE_WRITE32_MEMBER( data_dword_w ) { fifo_write(data); } + DECLARE_READ32_MEMBER( data_dword_r ) { return (UINT16)fifo_read(); } + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + +private: + void fifo_write(UINT32 data); + UINT32 fifo_read(); + + UINT16* m_buffer; + int m_ram_size; + + int m_read_ptr; + int m_write_ptr; + + int m_ef; // empty flag + int m_ff; // full flag + int m_hf; // half-full flag + + devcb2_write_line m_ef_handler; + devcb2_write_line m_ff_handler; + devcb2_write_line m_hf_handler; +}; + +// device type definition +extern const device_type FIFO7200; + + +#endif /* _7200FIFO_H */ diff --git a/src/mame/drivers/zn.c b/src/mame/drivers/zn.c index 3451d45f5f1..3313b97b939 100644 --- a/src/mame/drivers/zn.c +++ b/src/mame/drivers/zn.c @@ -16,6 +16,7 @@ #include "machine/at28c16.h" #include "machine/nvram.h" #include "machine/mb3773.h" +#include "machine/7200fifo.h" #include "machine/znsec.h" #include "machine/zndip.h" #include "machine/idectrl.h" @@ -40,7 +41,9 @@ public: m_zndip(*this,"maincpu:sio0:zndip"), m_maincpu(*this, "maincpu"), m_audiocpu(*this, "audiocpu"), - m_ram(*this, "maincpu:ram") + m_ram(*this, "maincpu:ram"), + m_cbaj_fifo1(*this, "cbaj_fifo1"), + m_cbaj_fifo2(*this, "cbaj_fifo2") { } @@ -75,12 +78,8 @@ public: DECLARE_WRITE_LINE_MEMBER(coh1001l_ymz_irq); DECLARE_WRITE8_MEMBER(coh1002v_bank_w); DECLARE_WRITE8_MEMBER(coh1002m_bank_w); - DECLARE_READ8_MEMBER(cbaj_from_z80_latch_r); - DECLARE_WRITE8_MEMBER(cbaj_to_z80_latch_w); - DECLARE_READ8_MEMBER(cbaj_from_z80_status_r); - DECLARE_READ8_MEMBER(cbaj_to_z80_latch_r); - DECLARE_WRITE8_MEMBER(cbaj_from_z80_latch_w); - DECLARE_READ8_MEMBER(cbaj_to_z80_status_r); + DECLARE_READ8_MEMBER(cbaj_sound_main_status_r); + DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r); DECLARE_READ8_MEMBER(jdredd_idestat_r); DECLARE_READ16_MEMBER(jdredd_ide_r); DECLARE_WRITE16_MEMBER(jdredd_ide_w); @@ -97,7 +96,6 @@ public: DECLARE_MACHINE_RESET(coh1001l); DECLARE_MACHINE_RESET(coh1002v); DECLARE_MACHINE_RESET(coh1002m); - DECLARE_MACHINE_RESET(coh1002msnd); DECLARE_WRITE_LINE_MEMBER(irqhandler); INTERRUPT_GEN_MEMBER(qsound_interrupt); void atpsx_dma_read(UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size ); @@ -120,10 +118,6 @@ private: size_t m_nbajamex_eeprom_size; UINT8 *m_nbajamex_eeprom; - UINT8 m_cbaj_fifo_buffer[2][0x400]; - int m_cbaj_fifo_main_ptr[2]; - int m_cbaj_fifo_z80_ptr[2]; - required_device m_gpu; required_device m_znsec0; required_device m_znsec1; @@ -131,6 +125,8 @@ private: required_device m_maincpu; optional_device m_audiocpu; required_device m_ram; + optional_device m_cbaj_fifo1; + optional_device m_cbaj_fifo2; }; inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... ) @@ -2422,47 +2418,23 @@ static MACHINE_CONFIG_DERIVED( coh1002m, zn1_2mb_vram ) MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1002m) MACHINE_CONFIG_END -READ8_MEMBER(zn_state::cbaj_from_z80_latch_r) +READ8_MEMBER(zn_state::cbaj_sound_main_status_r) { - UINT8 ret = m_cbaj_fifo_buffer[1][m_cbaj_fifo_main_ptr[1]]; - m_cbaj_fifo_main_ptr[1] = (m_cbaj_fifo_main_ptr[1] + 1) & 0x3ff; - return ret; -} - -WRITE8_MEMBER(zn_state::cbaj_to_z80_latch_w) -{ - m_cbaj_fifo_buffer[0][m_cbaj_fifo_main_ptr[0]] = data; - m_cbaj_fifo_main_ptr[0] = (m_cbaj_fifo_main_ptr[0] + 1) & 0x3ff; -} - -READ8_MEMBER(zn_state::cbaj_from_z80_status_r) -{ - return (m_cbaj_fifo_main_ptr[1] != m_cbaj_fifo_z80_ptr[1]) ? 0x02 : 0x00; + // d1: fifo empty flag, other bits: unused(?) + return ~(m_cbaj_fifo2->ef_r() << 1); } static ADDRESS_MAP_START(coh1002msnd_map, AS_PROGRAM, 32, zn_state) - AM_RANGE(0x1fb00000, 0x1fb00003) AM_READWRITE8(cbaj_from_z80_latch_r, cbaj_to_z80_latch_w, 0x000000ff) - AM_RANGE(0x1fb00000, 0x1fb00003) AM_READ8(cbaj_from_z80_status_r, 0xff000000) + AM_RANGE(0x1fb00000, 0x1fb00003) AM_DEVREAD8("cbaj_fifo2", fifo7200_device, data_byte_r, 0x000000ff) AM_DEVWRITE8("cbaj_fifo1", fifo7200_device, data_byte_w, 0x000000ff) + AM_RANGE(0x1fb00000, 0x1fb00003) AM_READ8(cbaj_sound_main_status_r, 0xff000000) AM_IMPORT_FROM(coh1002m_map) ADDRESS_MAP_END -READ8_MEMBER(zn_state::cbaj_to_z80_latch_r) +READ8_MEMBER(zn_state::cbaj_sound_z80_status_r) { - UINT8 ret = m_cbaj_fifo_buffer[0][m_cbaj_fifo_z80_ptr[0]]; - m_cbaj_fifo_z80_ptr[0] = (m_cbaj_fifo_z80_ptr[0] + 1) & 0x3ff; - return ret; -} - -WRITE8_MEMBER(zn_state::cbaj_from_z80_latch_w) -{ - m_cbaj_fifo_buffer[1][m_cbaj_fifo_z80_ptr[1]] = data; - m_cbaj_fifo_z80_ptr[1] = (m_cbaj_fifo_z80_ptr[1] + 1) & 0x3ff; -} - -READ8_MEMBER(zn_state::cbaj_to_z80_status_r) -{ - return (m_cbaj_fifo_main_ptr[0] != m_cbaj_fifo_z80_ptr[0]) ? 0x02 : 0x00; + // d1: fifo empty flag, other bits: unused + return ~(m_cbaj_fifo1->ef_r() << 1); } static ADDRESS_MAP_START( cbaj_z80_map, AS_PROGRAM, 8, zn_state ) @@ -2473,18 +2445,10 @@ ADDRESS_MAP_END static ADDRESS_MAP_START( cbaj_z80_port_map, AS_IO, 8, zn_state ) ADDRESS_MAP_GLOBAL_MASK(0xff) AM_RANGE(0x84, 0x85) AM_DEVREADWRITE("ymz", ymz280b_device, read, write) - AM_RANGE(0x90, 0x90) AM_READWRITE(cbaj_to_z80_latch_r, cbaj_from_z80_latch_w) - AM_RANGE(0x91, 0x91) AM_READ(cbaj_to_z80_status_r) + AM_RANGE(0x90, 0x90) AM_DEVREAD("cbaj_fifo1", fifo7200_device, data_byte_r) AM_DEVWRITE("cbaj_fifo2", fifo7200_device, data_byte_w) + AM_RANGE(0x91, 0x91) AM_READ(cbaj_sound_z80_status_r) ADDRESS_MAP_END -MACHINE_RESET_MEMBER(zn_state,coh1002msnd) -{ - m_cbaj_fifo_main_ptr[0] = m_cbaj_fifo_main_ptr[1] = 0; - m_cbaj_fifo_z80_ptr[0] = m_cbaj_fifo_z80_ptr[1] = 0; - - MACHINE_RESET_CALL_MEMBER(coh1002m); -} - static MACHINE_CONFIG_DERIVED( coh1002msnd, coh1002m ) MCFG_CPU_MODIFY("maincpu") MCFG_CPU_PROGRAM_MAP(coh1002msnd_map) @@ -2492,9 +2456,11 @@ static MACHINE_CONFIG_DERIVED( coh1002msnd, coh1002m ) MCFG_CPU_ADD("audiocpu", Z80, XTAL_32MHz/8) MCFG_CPU_PROGRAM_MAP(cbaj_z80_map) MCFG_CPU_IO_MAP(cbaj_z80_port_map) + + MCFG_FIFO7200_ADD("cbaj_fifo1", 0x400) // LH540202 + MCFG_FIFO7200_ADD("cbaj_fifo2", 0x400) // LH540202 MCFG_QUANTUM_TIME(attotime::from_hz(6000)) - MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1002msnd) MCFG_SOUND_ADD("ymz", YMZ280B, XTAL_16_9344MHz) MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)