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https://github.com/holub/mame
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prodigy: Added BCD display and initial layout (nw)
This commit is contained in:
Joakim Larsson Edstrom
parent
520e693dc2
commit
5595d69336
@ -31,11 +31,60 @@
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|LEDS-> O O O O O O O O OOOOOOOOOOO KPDCN |
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+-------------------------------------------------------------------------------------+
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******************************************************************************/
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Tracing the image shows that VIA Port A is used on the ROWCN and Port B on COLCN
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The VIA pins CB1 and CB2 together with PB0 and PB1 via the 74145 drives the BCD display.
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The BCD display is of common anode type and each anode a0-a3 selects which digit that
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will be lit selected by PB0 and PB1. The segments to be lit is selected by the 8 bits
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shifted into the 74164 by clock from VIA CB1 and data from CB2.
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Behind the BCD display we find the following supporting circuit
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4x7 segment BCD display
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+---+ +-----+ +---+---+---+---+
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+-----------------+ CB1 |74 |==/4/=>|2x |==/8/====>| 0 1 2 3 |
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| | VIA CB2 |164|==/4/=>|75491| segments | |
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| 4 char BCD LED | ===> 6522 +---+ +-----+ +---+---+---+---+
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+-----------------+ PB1--->|74 | | | | |
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||||||||||||||||||| PB2--->|145|=/4/=/R/=>b(4x )c=/4/==============>
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+---+ (PN2907)e=+ anodes
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|+5v
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*******************************************************************************************/
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#include "emu.h"
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#include "cpu/m6502/m6502.h"
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#include "machine/74145.h"
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#include "machine/netlist.h"
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#include "machine/nl_prodigy.h"
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#include "machine/6522via.h"
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// Generated artwork includes
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#include "prodigy.lh"
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#define LOG_SETUP (1U << 1)
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#define LOG_READ (1U << 2)
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#define LOG_BCD (1U << 3)
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#define LOG_NETLIST (1U << 4)
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#define LOG_CLK (1U << 5)
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//#define VERBOSE (LOG_BCD|LOG_NETLIST|LOG_SETUP)
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//#define LOG_OUTPUT_FUNC printf
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#include "logmacro.h"
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#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
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#define LOGR(...) LOGMASKED(LOG_READ, __VA_ARGS__)
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#define LOGBCD(...) LOGMASKED(LOG_BCD, __VA_ARGS__)
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#define LOGNL(...) LOGMASKED(LOG_NETLIST, __VA_ARGS__)
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#define LOGCLK(...) LOGMASKED(LOG_CLK, __VA_ARGS__)
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#ifdef _MSC_VER
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#define FUNCNAME __func__
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#else
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#define FUNCNAME __PRETTY_FUNCTION__
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#endif
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#define NETLIST_TAG "bcd"
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#define TTL74164DEV 0
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class prodigy_state : public driver_device
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{
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@ -43,13 +92,123 @@ public:
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prodigy_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_74145(*this, "io_74145")
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, m_segments(0)
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, m_via(*this, "via")
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, m_bcd(*this, NETLIST_TAG)
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, m_cb1(*this, "bcd:cb1")
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, m_cb2(*this, "bcd:cb2")
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, m_digit(0.0)
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{ }
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit0_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit1_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit2_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit3_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit4_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit5_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit6_cb);
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NETDEV_LOGIC_CALLBACK_MEMBER(bcd_bit7_cb);
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DECLARE_WRITE8_MEMBER( via_pb_w );
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DECLARE_WRITE_LINE_MEMBER(via_cb1_w);
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DECLARE_WRITE_LINE_MEMBER(via_cb2_w);
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DECLARE_WRITE_LINE_MEMBER(irq_handler);
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private:
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required_device<cpu_device> m_maincpu;
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required_device<ttl74145_device> m_74145;
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uint8_t m_segments;
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required_device<via6522_device> m_via;
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#if TTL74164DEV
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required_device<ttl74164_device> m_shift;
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#else
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required_device<netlist_mame_device_t> m_bcd;
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required_device<netlist_mame_logic_input_t> m_cb1;
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required_device<netlist_mame_logic_input_t> m_cb2;
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#endif
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uint8_t m_digit;
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void update_bcd();
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virtual void device_reset() override;
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};
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit0_cb) { if (data != 0) m_digit |= 0x01; else m_digit &= ~(0x01); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit1_cb) { if (data != 0) m_digit |= 0x02; else m_digit &= ~(0x02); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit2_cb) { if (data != 0) m_digit |= 0x04; else m_digit &= ~(0x04); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit3_cb) { if (data != 0) m_digit |= 0x08; else m_digit &= ~(0x08); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit4_cb) { if (data != 0) m_digit |= 0x10; else m_digit &= ~(0x10); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit5_cb) { if (data != 0) m_digit |= 0x20; else m_digit &= ~(0x20); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit6_cb) { if (data != 0) m_digit |= 0x40; else m_digit &= ~(0x40); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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NETDEV_LOGIC_CALLBACK_MEMBER(prodigy_state::bcd_bit7_cb) { if (data != 0) m_digit |= 0x80; else m_digit &= ~(0x80); LOGBCD("%s: %d m_digit: %02x\n", FUNCNAME, data, m_digit); }
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void prodigy_state::device_reset()
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{
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#if TTL74164DEV
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m_shift->b_w(1);
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m_shift->clear_w(1);
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#endif
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}
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WRITE_LINE_MEMBER(prodigy_state::via_cb1_w)
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{
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LOGCLK("%s: %d\n", FUNCNAME, state);
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m_cb1->write(state);
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}
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WRITE_LINE_MEMBER(prodigy_state::via_cb2_w)
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{
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LOGCLK("%s: %d\n", FUNCNAME, state);
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m_cb2->write(state);
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}
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WRITE_LINE_MEMBER(prodigy_state::irq_handler)
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{
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LOGBCD("%s: %d\n", FUNCNAME, state);
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m_maincpu->set_input_line(M6502_IRQ_LINE, state);
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update_bcd();
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}
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/* Pulling the base of the PN2907 PNP transistor low by the output of the 74145 controlled by PB0 and PB1 will feed
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the coresponding anode enabling the correct digit and lit the segments currently held by the outputs of the 74164
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serial to 8 bit parallel converter fed by serial data using CB1 clock and CB2 data
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PB2 and PB3 is also connected to the 74145, usage to be traced....
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*/
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WRITE8_MEMBER( prodigy_state::via_pb_w ) // Needs to trace which port decides what digit
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{
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LOGBCD("%s: %02x ANODE %02x\n", FUNCNAME, data, data & 0x03);
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m_74145->write( data & 0x0f ); // Write PB0-PB3 to the 74145
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}
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void prodigy_state::update_bcd()
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{
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LOGBCD("%s\n", FUNCNAME);
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uint8_t ttl74145_data;
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uint8_t digit_nbr = 4;
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ttl74145_data = m_74145->read();
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LOGBCD(" - 74145: %02x\n", ttl74145_data);
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if ((ttl74145_data & 0x0f) != 0x00)
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{
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switch (ttl74145_data & 0x0f)
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{
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case 0x01: digit_nbr = 0; break;
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case 0x02: digit_nbr = 1; break;
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case 0x04: digit_nbr = 2; break;
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case 0x08: digit_nbr = 3; break;
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default: logerror("Wrong BCD digit, shouldn't happen, call the maintainer!\n");
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}
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LOGBCD(" - digit number: %d\n", digit_nbr);
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LOGBCD(" - segments: %02x -> ", m_digit);
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m_segments = m_digit;
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LOGBCD("%02x\n", m_segments);
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output().set_digit_value( digit_nbr, m_segments);
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}
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}
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static ADDRESS_MAP_START( maincpu_map, AS_PROGRAM, 8, prodigy_state )
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AM_RANGE(0x0000, 0x07ff) AM_RAM
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AM_RANGE(0x2000, 0x200f) AM_DEVREADWRITE("via", via6522_device, read, write)
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@ -63,9 +222,72 @@ static MACHINE_CONFIG_START( prodigy, prodigy_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", M6502, XTAL_2MHz)
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MCFG_CPU_PROGRAM_MAP(maincpu_map)
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MCFG_DEFAULT_LAYOUT(layout_prodigy)
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MCFG_DEVICE_ADD("io_74145", TTL74145, 0)
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MCFG_DEVICE_ADD("via", VIA6522, XTAL_2MHz)
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(prodigy_state, irq_handler));
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MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(prodigy_state, via_pb_w))
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MCFG_VIA6522_CB1_HANDLER(WRITELINE(prodigy_state, via_cb1_w))
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MCFG_VIA6522_CB2_HANDLER(WRITELINE(prodigy_state, via_cb2_w))
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MCFG_DEVICE_ADD(NETLIST_TAG, NETLIST_CPU, XTAL_2MHz * 30)
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MCFG_NETLIST_SETUP(prodigy)
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MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cb1", "cb1.IN", 0)
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MCFG_NETLIST_LOGIC_INPUT(NETLIST_TAG, "cb2", "cb2.IN", 0)
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit0", "bcd_bit0", prodigy_state, bcd_bit0_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit1", "bcd_bit1", prodigy_state, bcd_bit1_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit2", "bcd_bit2", prodigy_state, bcd_bit2_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit3", "bcd_bit3", prodigy_state, bcd_bit3_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit4", "bcd_bit4", prodigy_state, bcd_bit4_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit5", "bcd_bit5", prodigy_state, bcd_bit5_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit6", "bcd_bit6", prodigy_state, bcd_bit6_cb, "")
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MCFG_NETLIST_LOGIC_OUTPUT(NETLIST_TAG, "bcd_bit7", "bcd_bit7", prodigy_state, bcd_bit7_cb, "")
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MACHINE_CONFIG_END
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/*
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* 6522 VIA init sequence
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* :via Reg 03 <- 00 - DDRA - Data Direction A, pin A0-A7 programmed as inputs
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* :via Reg 02 <- 8f - DDRB - Data Direction B, pin B4-B6 programmed as inputs, other pins as outputs
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* :via Reg 0c <- e0 - PCR - Peripheral Control Register, CB2 out pos out, CB1 ints on neg edg, CA2 inp neg act edg, CA1 ints on neg edg
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* :via Reg 0b <- 58 - ACR - Auxilary Control Register, con ints, B7 dis, timed ints, shift out on 0/2, PA and PB latches disabled
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* :via Reg 09 <- 58 - T2C-H - Timer 2 High Order Counter value
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* :via Reg 04 <- ff - T1C-L - Timer 1 Low Order Latches
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* :via Reg 0e <- a0 - IER - Interrupt Enable Register, Timer 2 Interrupts enabled
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*
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* ISR VIA accesses
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* Reg 08 -> e1 - T2C-L - T2 low order counter
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* Reg 08 <- 6e - T2C-L - T2 low order latches
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* Reg 09 <- 20 - T2C-H - T2 High Order Counter
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* Reg 0a <- 00 - SR - Shift Register
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* Reg 00 <- 09
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* Reg 01 -> ff
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* Reg 00 -> 09
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* Reg 00 <- 08
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* Reg 01 -> ff
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* Reg 00 -> 08
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* Reg 00 <- 07
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* Reg 01 -> ff
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* Reg 00 <- 06
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* Reg 01 -> ff
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* Reg 00 <- 05
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* Reg 01 -> ff
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* Reg 00 <- 04
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* Reg 01 -> ff
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* Reg 00 <- 03
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* Reg 01 -> ff
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* Reg 00 <- 02
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* Reg 01 -> ff
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* Reg 00 <- 01
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* Reg 01 -> ff
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* Reg 00 <- 00
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* Reg 01 -> ff
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* Reg 0a <- 00
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* Reg 00 <- 05
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* Reg 08 -> e2
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*/
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ROM_START(prodigy)
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ROM_REGION(0x2000, "roms", 0)
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ROM_LOAD("0x2000.bin", 0x0000, 0x02000, CRC(8d60345a) SHA1(fff18ff12e1b1be91f8eac1178605a682564eff2))
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