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https://github.com/holub/mame
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(MESS) ti99: Fixing the TI floppy controller; still issues. (nw)
This commit is contained in:
Michael Zapf
parent
175ef51ec4
commit
55c1991174
@ -15,14 +15,33 @@
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#include "emu.h"
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#include "peribox.h"
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#include "ti_fdc.h"
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#include "machine/wd17xx.h"
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#include "formats/ti99_dsk.h"
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#define LOG logerror
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#define VERBOSE 1
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// ----------------------------------
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// Flags for debugging
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#define fdc_IRQ 1
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#define fdc_DRQ 2
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// Show read and write accesses
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#define TRACE_RW 0
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// Show CRU bit accesses
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#define TRACE_CRU 0
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// Show ready line activity
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#define TRACE_READY 0
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// Show detailed signal activity
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#define TRACE_SIGNALS 0
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// Show sector data
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#define TRACE_DATA 0
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// Show address bus operations
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#define TRACE_ADDRESS 0
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// Show address bus operations
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#define TRACE_MOTOR 0
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// ----------------------------------
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#define TI_FDC_TAG "ti_dssd_controller"
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@ -39,9 +58,8 @@ const wd17xx_interface ti_wd17xx_interface =
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};
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ti_fdc_device::ti_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: ti_expansion_card_device(mconfig, TI99_FDC, "TI-99 Standard DSSD Floppy Controller", tag, owner, clock, "ti99_fdc", __FILE__)
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{
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}
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: ti_expansion_card_device(mconfig, TI99_FDC, "TI-99 Standard DSSD Floppy Controller", tag, owner, clock, "ti99_fdc", __FILE__),
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m_fd1771(*this, FDC_TAG) { }
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/*
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callback called at the end of DVENA pulse
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@ -49,48 +67,85 @@ ti_fdc_device::ti_fdc_device(const machine_config &mconfig, const char *tag, dev
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void ti_fdc_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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m_DVENA = CLEAR_LINE;
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handle_hold();
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if (TRACE_MOTOR) logerror("tifdc: Motor off\n");
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set_ready_line();
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}
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/*
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Operate the wait state logic.
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*/
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void ti_fdc_device::set_ready_line()
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{
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// This is the wait state logic
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if (TRACE_SIGNALS) logerror("tifdc: address=%04x, DRQ=%d, INTRQ=%d, MOTOR=%d\n", m_address & 0xffff, m_DRQ, m_IRQ, m_DVENA);
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line_state nready = (m_WDsel && // Are we accessing 5ffx?
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m_WAITena && // and the wait state generation is active (SBO 2)
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(m_DRQ==CLEAR_LINE) && // and we are waiting for a byte
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(m_IRQ==CLEAR_LINE) && // and there is no interrupt yet
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(m_DVENA==ASSERT_LINE) // and the motor is turning?
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)? ASSERT_LINE : CLEAR_LINE; // In that case, clear READY and thus trigger wait states
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if (TRACE_READY) if (nready==ASSERT_LINE) logerror("tifdc: READY line = %d\n", (nready==CLEAR_LINE)? 1:0);
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m_slot->set_ready((nready==CLEAR_LINE)? ASSERT_LINE : CLEAR_LINE);
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}
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SETADDRESS_DBIN_MEMBER( ti_fdc_device::setaddress_dbin )
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{
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// Selection login in the PAL and some circuits on the board
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// Is the card being selected?
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m_address = offset;
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m_inDsrArea = ((m_address & m_select_mask)==m_select_value);
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if (!m_inDsrArea) return;
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if (TRACE_ADDRESS) logerror("tifdc: set address = %04x\n", offset & 0xffff);
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// Is the WD chip on the card being selected?
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m_WDsel = m_inDsrArea && ((m_address & 0x1ff0)==0x1ff0);
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// Clear or assert the outgoing READY line
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set_ready_line();
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}
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READ8Z_MEMBER(ti_fdc_device::readz)
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{
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if (m_selected)
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if (m_inDsrArea && m_selected)
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{
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if ((offset & m_select_mask)==m_select_value)
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{
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// only use the even addresses from 1ff0 to 1ff6.
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// Note that data is inverted.
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// 0101 1111 1111 0xx0
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UINT8 reply = 0;
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// only use the even addresses from 1ff0 to 1ff6.
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// Note that data is inverted.
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// 0101 1111 1111 0xx0
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UINT8 reply = 0;
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if ((offset & 0x1ff9)==0x1ff0)
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if (m_WDsel && ((m_address & 1)==0))
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{
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if (!space.debugger_access()) reply = wd17xx_r(m_fd1771, space, (offset >> 1)&0x03);
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if (TRACE_DATA)
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{
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if (!space.debugger_access()) reply = wd17xx_r(m_controller, space, (offset >> 1)&0x03);
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if ((m_address & 0xffff)==0x5ff6) logerror("%02x ", ~reply & 0xff);
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else logerror("\n%04x: %02x", m_address&0xffff, ~reply & 0xff);
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}
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else
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{
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reply = m_dsrrom[offset & 0x1fff];
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}
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*value = reply;
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if (VERBOSE>5) LOG("ti_fdc: %04x -> %02x\n", offset & 0xffff, *value);
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}
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else
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{
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reply = m_dsrrom[m_address & 0x1fff];
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}
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*value = reply;
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if (TRACE_RW) logerror("ti_fdc: %04x -> %02x\n", offset & 0xffff, *value);
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}
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}
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WRITE8_MEMBER(ti_fdc_device::write)
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{
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if (m_selected)
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if (m_inDsrArea && m_selected)
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{
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if ((offset & m_select_mask)==m_select_value)
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if (TRACE_RW) logerror("ti_fdc: %04x <- %02x\n", offset & 0xffff, ~data & 0xff);
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// only use the even addresses from 1ff8 to 1ffe.
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// Note that data is inverted.
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// 0101 1111 1111 1xx0
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if (m_WDsel && ((m_address & 9)==8))
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{
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if (VERBOSE>5) LOG("ti_fdc: %04x <- %02x\n", offset & 0xffff, data);
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// only use the even addresses from 1ff8 to 1ffe.
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// Note that data is inverted.
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// 0101 1111 1111 1xx0
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if ((offset & 0x1ff9)==0x1ff8)
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{
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if (!space.debugger_access()) wd17xx_w(m_controller, space, (offset >> 1)&0x03, data);
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}
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if (!space.debugger_access()) wd17xx_w(m_fd1771, space, (offset >> 1)&0x03, data);
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}
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}
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}
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@ -121,6 +176,7 @@ READ8Z_MEMBER(ti_fdc_device::crureadz)
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if (m_SIDSEL) reply |= 0x80;
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}
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*value = reply;
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if (TRACE_CRU) logerror("tifdc: Read CRU = %02x\n", *value);
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}
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}
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@ -136,17 +192,19 @@ WRITE8_MEMBER(ti_fdc_device::cruwrite)
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case 0:
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/* (De)select the card. Indicated by a LED on the board. */
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m_selected = (data!=0);
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if (VERBOSE>4) LOG("ti_fdc: Map DSR = %d\n", m_selected);
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if (TRACE_CRU) logerror("tifdc: Map DSR (bit 0) = %d\n", m_selected);
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break;
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case 1:
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/* Activate motor */
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if (data && !m_strobe_motor)
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if (data==1 && m_lastval==0)
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{ /* on rising edge, set motor_running for 4.23s */
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if (TRACE_CRU) logerror("tifdc: trigger motor (bit 1)\n");
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m_DVENA = ASSERT_LINE;
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handle_hold();
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if (TRACE_MOTOR) logerror("tifdc: motor on\n");
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set_ready_line();
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m_motor_on_timer->adjust(attotime::from_msec(4230));
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}
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m_strobe_motor = (data!=0);
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m_lastval = data;
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break;
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case 2:
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@ -155,13 +213,13 @@ WRITE8_MEMBER(ti_fdc_device::cruwrite)
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// 1: TMS9900 is stopped until IRQ or DRQ are set
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// OR the motor stops rotating - rotates for 4.23s after write
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// to CRU bit 1
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// This is not emulated and could cause the TI99 to lock up
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m_hold = (data != 0);
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handle_hold();
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m_WAITena = (data != 0);
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if (TRACE_CRU) logerror("tifdc: arm wait state logic (bit 2) = %d\n", data);
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break;
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case 3:
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/* Load disk heads (HLT pin) (bit 3). Not implemented. */
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if (TRACE_CRU) logerror("tifdc: set head load (bit 3) = %d\n", data);
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break;
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case 4:
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@ -169,17 +227,17 @@ WRITE8_MEMBER(ti_fdc_device::cruwrite)
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case 6:
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/* Select drive X (bits 4-6) */
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drive = bit-4; /* drive # (0-2) */
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if (TRACE_CRU) logerror("tifdc: set drive (bit %d) = %d\n", bit, data);
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drivebit = 1<<drive;
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if (data)
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if (data != 0)
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{
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if ((m_DSEL & drivebit)!=0) /* select drive */
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if ((m_DSEL & drivebit) == 0) /* select drive */
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{
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if (m_DSEL != 0)
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LOG("ti_fdc: Multiple drives selected, %02x\n", m_DSEL);
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logerror("tifdc: Multiple drives selected, %02x\n", m_DSEL);
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m_DSEL |= drivebit;
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wd17xx_set_drive(m_controller, drive);
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/*wd17xx_set_side(DSKside);*/
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wd17xx_set_drive(m_fd1771, drive);
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}
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}
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else
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@ -189,34 +247,13 @@ WRITE8_MEMBER(ti_fdc_device::cruwrite)
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case 7:
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/* Select side of disk (bit 7) */
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m_SIDSEL = data;
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wd17xx_set_side(m_controller, data);
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if (TRACE_CRU) logerror("tifdc: set side (bit 7) = %d\n", data);
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wd17xx_set_side(m_fd1771, data);
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break;
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}
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}
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}
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/*
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Call this when the state of DSKhold or DRQ/IRQ or DVENA change
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Emulation is faulty because the CPU is actually stopped in the midst of
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instruction, at the end of the memory access
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TODO: This has to be replaced by the proper READY handling that is already
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prepared here. (Requires READY handling by the CPU.)
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*/
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void ti_fdc_device::handle_hold()
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{
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line_state state;
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if (m_hold && !m_DRQ && !m_IRQ && (m_DVENA==ASSERT_LINE))
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state = ASSERT_LINE;
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else
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state = CLEAR_LINE;
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m_slot->set_ready((state==CLEAR_LINE)? ASSERT_LINE : CLEAR_LINE);
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// machine().device("maincpu")->execute().set_input_line(INPUT_LINE_HALT, state);
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}
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/*
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Resets the drive geometry. This is required because the heuristic of
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the default implementation sets the drive geometry to the geometry
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@ -243,40 +280,37 @@ void ti_fdc_device::set_all_geometries(floppy_type_t type)
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*/
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WRITE_LINE_MEMBER( ti_fdc_device::intrq_w )
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{
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if (VERBOSE>8) LOG("ti_fdc: set irq = %02x\n", state);
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m_IRQ = (state==ASSERT_LINE);
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if (TRACE_SIGNALS) logerror("ti_fdc: set irq = %d\n", state);
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m_IRQ = (line_state)state;
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// Note that INTB is actually not used in the TI-99 family. But the
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// controller asserts the line nevertheless, probably intended for
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// use in another planned TI system
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m_slot->set_intb(state);
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handle_hold();
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set_ready_line();
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}
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WRITE_LINE_MEMBER( ti_fdc_device::drq_w )
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{
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if (VERBOSE>8) LOG("ti_fdc: set drq = %02x\n", state);
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m_DRQ = (state == ASSERT_LINE);
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handle_hold();
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if (TRACE_SIGNALS) logerror("ti_fdc: set drq = %d\n", state);
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m_DRQ = (line_state)state;
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set_ready_line();
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}
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void ti_fdc_device::device_start(void)
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{
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if (VERBOSE>5) LOG("ti_fdc: TI FDC start\n");
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logerror("ti_fdc: TI FDC start\n");
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m_dsrrom = memregion(DSRROM)->base();
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m_motor_on_timer = timer_alloc(MOTOR_TIMER);
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m_controller = subdevice(FDC_TAG);
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m_cru_base = 0x1100;
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}
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void ti_fdc_device::device_reset(void)
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{
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if (VERBOSE>5) LOG("ti_fdc: TI FDC reset\n");
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logerror("ti_fdc: TI FDC reset\n");
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m_DSEL = 0;
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m_SIDSEL = 0;
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m_DVENA = CLEAR_LINE;
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m_strobe_motor = false;
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m_lastval = 0;
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if (m_genmod)
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{
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m_select_mask = 0x1fe000;
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@ -287,9 +321,9 @@ void ti_fdc_device::device_reset(void)
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m_select_mask = 0x7e000;
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m_select_value = 0x74000;
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}
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m_DRQ = false;
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m_IRQ = false;
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m_hold = false;
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m_DRQ = CLEAR_LINE;
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m_IRQ = CLEAR_LINE;
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m_WAITena = false;
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m_selected = false;
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ti99_set_80_track_drives(FALSE);
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@ -16,6 +16,7 @@
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#define __TIFDC__
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#include "ti99defs.h"
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#include "machine/wd17xx.h"
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#include "imagedev/flopdrv.h"
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extern const device_type TI99_FDC;
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@ -26,6 +27,7 @@ public:
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ti_fdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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DECLARE_READ8Z_MEMBER(readz);
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DECLARE_WRITE8_MEMBER(write);
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DECLARE_SETADDRESS_DBIN_MEMBER(setaddress_dbin);
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DECLARE_WRITE_LINE_MEMBER( intrq_w );
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DECLARE_WRITE_LINE_MEMBER( drq_w );
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@ -41,22 +43,30 @@ protected:
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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private:
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void handle_hold(void);
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void set_ready_line();
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void set_all_geometries(floppy_type_t type);
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void set_geometry(device_t *drive, floppy_type_t type);
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// Recent address
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int m_address;
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// Holds the status of the DRQ and IRQ lines.
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bool m_DRQ, m_IRQ;
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line_state m_DRQ, m_IRQ;
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// When TRUE, keeps DVENA high.
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bool m_strobe_motor;
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// Needed for triggering the motor monoflop
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UINT8 m_lastval;
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// Signal DVENA. When TRUE, makes some drive turning.
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line_state m_DVENA;
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// When TRUE the CPU is halted while DRQ/IRQ are true.
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bool m_hold;
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bool m_WAITena;
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// WD chip selected
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bool m_WDsel;
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// Set when address is in card area
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bool m_inDsrArea;
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// Indicates which drive has been selected. Values are 0, 1, 2, and 4.
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// 000 = no drive
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@ -72,7 +82,7 @@ private:
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emu_timer* m_motor_on_timer;
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// Link to the FDC1771 controller on the board.
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device_t* m_controller;
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required_device<fd1771_device> m_fd1771;
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// DSR ROM
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UINT8* m_dsrrom;
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