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More device normalization:

Browse Source 
cpu_get_info_* -> device_get_info_*
  cpu_set_info_* -> device_set_info_*
  cpu_reset      -> device_reset

Removed the cputype_get_* macros as they are not necessary.

Removed cpuintrf_init() which is no longer necessary.
This commit is contained in:
Aaron Giles 2008-12-16 16:30:28 +00:00
parent 98c40f06db
commit 5630547540
64 changed files with 426 additions and 674 deletions
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2
src/emu/clifront.c
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@ -337,7 +337,6 @@ int cli_info_listxml(core_options *options, const char *gamename)
{
/* since print_mame_xml expands the machine driver, we need to set things up */
init_resource_tracking();
cpuintrf_init(NULL);
sndintrf_init(NULL);
print_mame_xml(stdout, drivers, gamename);
@ -559,7 +558,6 @@ int cli_info_listsamples(core_options *options, const char *gamename)
/* since we expand the machine driver, we need to set things up */
init_resource_tracking();
cpuintrf_init(NULL);
sndintrf_init(NULL);
/* iterate over drivers */

6
src/emu/cpu/adsp2100/adsp2100.h
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@ -166,17 +166,17 @@ extern UINT16 adsp2181_idma_data_r(const device_config *device);
INLINE void adsp21xx_set_rx_handler(const device_config *device, adsp21xx_rx_func handler)
{
cpu_set_info_fct(device, CPUINFO_PTR_ADSP2100_RX_HANDLER, (genf *)handler);
device_set_info_fct(device, CPUINFO_PTR_ADSP2100_RX_HANDLER, (genf *)handler);
}
INLINE void adsp21xx_set_tx_handler(const device_config *device, adsp21xx_tx_func handler)
{
cpu_set_info_fct(device, CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)handler);
device_set_info_fct(device, CPUINFO_PTR_ADSP2100_TX_HANDLER, (genf *)handler);
}
INLINE void adsp21xx_set_timer_handler(const device_config *device, adsp21xx_timer_func handler)
{
cpu_set_info_fct(device, CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)handler);
device_set_info_fct(device, CPUINFO_PTR_ADSP2100_TIMER_HANDLER, (genf *)handler);
}

2
src/emu/cpu/cop400/cop410.c
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@ -195,7 +195,7 @@ static CPU_INIT( cop410 )
/* set clock divider */
cpu_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
device_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
/* allocate serial timer */

2
src/emu/cpu/cop400/cop420.c
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@ -198,7 +198,7 @@ static CPU_INIT( cop420 )
/* set clock divider */
cpu_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
device_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
/* allocate serial timer */

2
src/emu/cpu/cop400/cop440.c
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@ -210,7 +210,7 @@ static CPU_INIT( cop444 )
/* set clock divider */
cpu_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
device_set_info_int(device, CPUINFO_INT_CLOCK_DIVIDER, cop400->intf->cki);
/* allocate serial timer */

2
src/emu/cpu/drcfe.c
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@ -147,7 +147,7 @@ drcfe_state *drcfe_init(const device_config *cpu, const drcfe_config *config, vo
drcfe->device = cpu;
drcfe->program = memory_find_address_space(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->pageshift = cpu_get_page_shift(cpu, ADDRESS_SPACE_PROGRAM);
drcfe->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
drcfe->translate = (cpu_translate_func)device_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
#ifdef LSB_FIRST
if (cpu_get_endianness(cpu) == ENDIANNESS_BIG)
#else

10
src/emu/cpu/i8085/i8085.h
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@ -65,27 +65,27 @@ CPU_DISASSEMBLE( i8085 );
INLINE void i8085_set_sod_callback(const device_config *device, i8085_sod_func callback)
{
cpu_set_info_fct(device, CPUINFO_PTR_I8085_SOD_CALLBACK, (genf *)callback);
device_set_info_fct(device, CPUINFO_PTR_I8085_SOD_CALLBACK, (genf *)callback);
}
INLINE void i8085_set_sid_callback(const device_config *device, i8085_sid_func callback)
{
cpu_set_info_fct(device, CPUINFO_PTR_I8085_SID_CALLBACK, (genf *)callback);
device_set_info_fct(device, CPUINFO_PTR_I8085_SID_CALLBACK, (genf *)callback);
}
INLINE void i8085_set_inte_callback(const device_config *device, i8085_inte_func callback)
{
cpu_set_info_fct(device, CPUINFO_PTR_I8085_INTE_CALLBACK, (genf *)callback);
device_set_info_fct(device, CPUINFO_PTR_I8085_INTE_CALLBACK, (genf *)callback);
}
INLINE void i8085_set_status_callback(const device_config *device, i8085_status_func callback)
{
cpu_set_info_fct(device, CPUINFO_PTR_I8085_STATUS_CALLBACK, (genf *)callback);
device_set_info_fct(device, CPUINFO_PTR_I8085_STATUS_CALLBACK, (genf *)callback);
}
INLINE void i8085_set_sid(const device_config *device, int sid)
{
cpu_set_info_int(device, CPUINFO_INT_I8085_SID, sid);
device_set_info_int(device, CPUINFO_INT_I8085_SID, sid);
}
#endif

2
src/emu/cpu/konami/konami.h
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@ -33,7 +33,7 @@ CPU_DISASSEMBLE( konami );
INLINE void konami_configure_set_lines(const device_config *device, konami_set_lines_func func)
{
cpu_set_info_fct(device, CPUINFO_PTR_KONAMI_SETLINES_CALLBACK, (genf *)func);
device_set_info_fct(device, CPUINFO_PTR_KONAMI_SETLINES_CALLBACK, (genf *)func);
}
#endif /* __KONAMI_H__ */

4
src/emu/cpu/powerpc/ppc.h
View File

@ -194,13 +194,13 @@ CPU_GET_INFO( mpc8240 );
INLINE void ppc4xx_spu_set_tx_handler(const device_config *cpu, ppc4xx_spu_tx_handler handler)
{
cpu_set_info_fct(cpu, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)handler);
device_set_info_fct(cpu, CPUINFO_PTR_SPU_TX_HANDLER, (genf *)handler);
}
INLINE void ppc4xx_spu_receive_byte(const device_config *cpu, UINT8 byteval)
{
cpu_set_info_int(cpu, CPUINFO_INT_PPC_RX_DATA, byteval);
device_set_info_int(cpu, CPUINFO_INT_PPC_RX_DATA, byteval);
}

4
src/emu/cpu/powerpc/ppccom.c
View File

@ -1714,7 +1714,7 @@ updateirq:
static READ8_HANDLER( ppc4xx_spu_r )
{
powerpc_state *ppc = cpu_get_info_ptr(space->cpu, CPUINFO_PTR_CONTEXT);
powerpc_state *ppc = device_get_info_ptr(space->cpu, CPUINFO_PTR_CONTEXT);
UINT8 result = 0xff;
switch (offset)
@ -1741,7 +1741,7 @@ static READ8_HANDLER( ppc4xx_spu_r )
static WRITE8_HANDLER( ppc4xx_spu_w )
{
powerpc_state *ppc = cpu_get_info_ptr(space->cpu, CPUINFO_PTR_CONTEXT);
powerpc_state *ppc = device_get_info_ptr(space->cpu, CPUINFO_PTR_CONTEXT);
UINT8 oldstate, newstate;
if (PRINTF_SPU)

2
src/emu/cpu/vtlb.c
View File

@ -70,7 +70,7 @@ vtlb_state *vtlb_alloc(const device_config *cpu, int space, int fixed_entries, i
vtlb->fixed = fixed_entries;
vtlb->pageshift = cpu_get_page_shift(cpu, space);
vtlb->addrwidth = cpu_get_logaddr_width(cpu, space);
vtlb->translate = (cpu_translate_func)cpu_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
vtlb->translate = (cpu_translate_func)device_get_info_fct(cpu, CPUINFO_PTR_TRANSLATE);
/* validate CPU information */
assert((1 << vtlb->pageshift) > VTLB_FLAGS_MASK);

35
src/emu/cpuexec.c
View File

@ -384,16 +384,13 @@ static DEVICE_START( cpu )
for (spacenum = 0; spacenum < ADDRESS_SPACES; spacenum++)
header->space[spacenum] = memory_find_address_space(device, spacenum);
header->set_info = (cpu_set_info_func)cpu_get_info_fct(device, CPUINFO_PTR_SET_INFO);
header->execute = (cpu_execute_func)cpu_get_info_fct(device, CPUINFO_PTR_EXECUTE);
header->burn = (cpu_burn_func)cpu_get_info_fct(device, CPUINFO_PTR_BURN);
header->translate = (cpu_translate_func)cpu_get_info_fct(device, CPUINFO_PTR_TRANSLATE);
header->disassemble = (cpu_disassemble_func)cpu_get_info_fct(device, CPUINFO_PTR_DISASSEMBLE);
header->set_info = (cpu_set_info_func)device_get_info_fct(device, CPUINFO_PTR_SET_INFO);
header->execute = (cpu_execute_func)device_get_info_fct(device, CPUINFO_PTR_EXECUTE);
header->burn = (cpu_burn_func)device_get_info_fct(device, CPUINFO_PTR_BURN);
header->translate = (cpu_translate_func)device_get_info_fct(device, CPUINFO_PTR_TRANSLATE);
header->disassemble = (cpu_disassemble_func)device_get_info_fct(device, CPUINFO_PTR_DISASSEMBLE);
header->dasm_override = NULL;
header->clock_divider = cpu_get_clock_divider(device);
header->clock_multiplier = cpu_get_clock_multiplier(device);
/* fill in the input states and IRQ callback information */
for (line = 0; line < ARRAY_LENGTH(classdata->input); line++)
{
@ -409,7 +406,7 @@ static DEVICE_START( cpu )
classdata->inttrigger = index + TRIGGER_INT;
/* fill in the clock and timing information */
classdata->clock = (UINT64)config->clock * header->clock_multiplier / header->clock_divider;
classdata->clock = (UINT64)config->clock * cpu_get_clock_multiplier(device) / cpu_get_clock_divider(device);
classdata->clockscale = 1.0;
/* allocate timers if we need them */
@ -420,7 +417,7 @@ static DEVICE_START( cpu )
/* initialize this CPU */
num_regs = state_save_get_reg_count(device->machine);
init = (cpu_init_func)cpu_get_info_fct(device, CPUINFO_PTR_INIT);
init = (cpu_init_func)device_get_info_fct(device, CPUINFO_PTR_INIT);
(*init)(device, index, classdata->clock, standard_irq_callback);
num_regs = state_save_get_reg_count(device->machine) - num_regs;
@ -470,7 +467,7 @@ static DEVICE_RESET( cpu )
classdata->totalcycles = 0;
/* then reset the CPU directly */
reset = (cpu_reset_func)cpu_get_info_fct(device, CPUINFO_PTR_RESET);
reset = (cpu_reset_func)device_get_info_fct(device, CPUINFO_PTR_RESET);
if (reset != NULL)
(*reset)(device);
@ -520,7 +517,7 @@ static DEVICE_STOP( cpu )
cpu_exit_func exit;
/* call the CPU's exit function if present */
exit = (cpu_exit_func)cpu_get_info_fct(device, CPUINFO_PTR_EXIT);
exit = (cpu_exit_func)device_get_info_fct(device, CPUINFO_PTR_EXIT);
if (exit != NULL)
(*exit)(device);
}
@ -540,7 +537,7 @@ static DEVICE_SET_INFO( cpu )
if (header != NULL)
set_info = header->set_info;
else
set_info = (cpu_set_info_func)cpu_get_info_fct(device, CPUINFO_PTR_SET_INFO);
set_info = (cpu_set_info_func)device_get_info_fct(device, CPUINFO_PTR_SET_INFO);
switch (state)
{
@ -1181,7 +1178,7 @@ static void compute_perfect_interleave(running_machine *machine)
if (machine->cpu[0] != NULL && machine->cpu[0]->token != NULL)
{
cpu_class_data *classdata = cpu_get_class_data(machine->cpu[0]);
attoseconds_t smallest = classdata->attoseconds_per_cycle * cputype_get_min_cycles(cpu_get_type(machine->cpu[0]));
attoseconds_t smallest = classdata->attoseconds_per_cycle * cpu_get_min_cycles(machine->cpu[0]);
attoseconds_t perfect = ATTOSECONDS_PER_SECOND - 1;
const device_config *cpu;
@ -1378,17 +1375,17 @@ static TIMER_CALLBACK( empty_event_queue )
switch (state)
{
case PULSE_LINE:
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, ASSERT_LINE);
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, CLEAR_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, ASSERT_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, CLEAR_LINE);
break;
case HOLD_LINE:
case ASSERT_LINE:
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, ASSERT_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, ASSERT_LINE);
break;
case CLEAR_LINE:
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, CLEAR_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + param, CLEAR_LINE);
break;
default:
@ -1425,7 +1422,7 @@ static IRQ_CALLBACK( standard_irq_callback )
if (inputline->curstate == HOLD_LINE)
{
LOG(("->set_irq_line('%s',%d,%d)\n", device->tag, irqline, CLEAR_LINE));
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + irqline, CLEAR_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + irqline, CLEAR_LINE);
inputline->curstate = CLEAR_LINE;
}

176
src/emu/cpuintrf.c
View File

@ -35,131 +35,10 @@
/***************************************************************************
GLOBAL VARIABLES
***************************************************************************/
static char temp_string_pool[TEMP_STRING_POOL_ENTRIES][MAX_STRING_LENGTH];
static int temp_string_pool_index;
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/
/*-------------------------------------------------
get_temp_string_buffer - return a pointer to
a temporary string buffer
-------------------------------------------------*/
INLINE char *get_temp_string_buffer(void)
{
char *string = &temp_string_pool[temp_string_pool_index++ % TEMP_STRING_POOL_ENTRIES][0];
string[0] = 0;
return string;
}
/***************************************************************************
GLOBAL MANAGEMENT
***************************************************************************/
/*-------------------------------------------------
cpuintrf_init - initialize global structures
-------------------------------------------------*/
void cpuintrf_init(running_machine *machine)
{
}
/***************************************************************************
LIVE CPU ACCESSORS
***************************************************************************/
/*-------------------------------------------------
cpu_get_info_* - return information about a
live CPU
-------------------------------------------------*/
INT64 cpu_get_info_int(const device_config *device, UINT32 state)
{
const cpu_config *config = device->inline_config;
cpuinfo info;
info.i = 0;
(*config->type)(device, state, &info);
return info.i;
}
void *cpu_get_info_ptr(const device_config *device, UINT32 state)
{
const cpu_config *config = device->inline_config;
cpuinfo info;
info.p = NULL;
(*config->type)(device, state, &info);
return info.p;
}
genf *cpu_get_info_fct(const device_config *device, UINT32 state)
{
const cpu_config *config = device->inline_config;
cpuinfo info;
info.f = NULL;
(*config->type)(device, state, &info);
return info.f;
}
const char *cpu_get_info_string(const device_config *device, UINT32 state)
{
const cpu_config *config = device->inline_config;
cpuinfo info;
info.s = get_temp_string_buffer();
(*config->type)(device, state, &info);
return info.s;
}
/*-------------------------------------------------
cpu_set_info_* - set information about a
live CPU
-------------------------------------------------*/
void cpu_set_info_int(const device_config *device, UINT32 state, INT64 data)
{
cpu_class_header *classheader = cpu_get_class_header(device);
cpuinfo info;
info.i = data;
(*classheader->set_info)(device, state, &info);
}
void cpu_set_info_ptr(const device_config *device, UINT32 state, void *data)
{
cpu_class_header *classheader = cpu_get_class_header(device);
cpuinfo info;
info.p = data;
(*classheader->set_info)(device, state, &info);
}
void cpu_set_info_fct(const device_config *device, UINT32 state, genf *data)
{
cpu_class_header *classheader = cpu_get_class_header(device);
cpuinfo info;
info.f = data;
(*classheader->set_info)(device, state, &info);
}
/*-------------------------------------------------
cpu_get_physical_pc_byte - return the PC,
corrected to a byte offset and translated to
@ -171,7 +50,7 @@ offs_t cpu_get_physical_pc_byte(const device_config *device)
const address_space *space = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
offs_t pc;
pc = memory_address_to_byte(space, cpu_get_info_int(device, CPUINFO_INT_PC));
pc = memory_address_to_byte(space, device_get_info_int(device, CPUINFO_INT_PC));
memory_address_physical(space, TRANSLATE_FETCH, &pc);
return pc;
}
@ -249,57 +128,6 @@ void cpu_set_dasm_override(const device_config *device, cpu_disassemble_func das
/***************************************************************************
CPU TYPE ACCESSORS
***************************************************************************/
/*-------------------------------------------------
cputype_get_info_* - return information about a
given CPU type
-------------------------------------------------*/
INT64 cputype_get_info_int(cpu_type cputype, UINT32 state)
{
cpuinfo info;
assert(cputype != NULL);
info.i = 0;
(*cputype)(NULL, state, &info);
return info.i;
}
void *cputype_get_info_ptr(cpu_type cputype, UINT32 state)
{
cpuinfo info;
assert(cputype != NULL);
info.p = NULL;
(*cputype)(NULL, state, &info);
return info.p;
}
genf *cputype_get_info_fct(cpu_type cputype, UINT32 state)
{
cpuinfo info;
assert(cputype != NULL);
info.f = NULL;
(*cputype)(NULL, state, &info);
return info.f;
}
const char *cputype_get_info_string(cpu_type cputype, UINT32 state)
{
cpuinfo info;
assert(cputype != NULL);
info.s = get_temp_string_buffer();
(*cputype)(NULL, state, &info);
return info.s;
}
/***************************************************************************
DUMMY CPU DEFINITION
***************************************************************************/
@ -307,7 +135,7 @@ const char *cputype_get_info_string(cpu_type cputype, UINT32 state)
typedef struct _dummy_context dummy_context;
struct _dummy_context
{
UINT32 icount;
int icount;
};
static CPU_INIT( dummy ) { }

129
src/emu/cpuintrf.h
View File

@ -128,13 +128,11 @@ enum
/* --- the following bits of info are returned as pointers to functions --- */
CPUINFO_FCT_FIRST = DEVINFO_FCT_FIRST,
/* direct map to device data */
CPUINFO_PTR_RESET = DEVINFO_FCT_RESET, /* R/O: void (*reset)(const device_config *device) */
CPUINFO_PTR_EXIT = DEVINFO_FCT_STOP, /* R/O: void (*exit)(const device_config *device) */
/* CPU-specific additions */
CPUINFO_PTR_SET_INFO = DEVINFO_FCT_CLASS_SPECIFIC, /* R/O: void (*set_info)(const device_config *device, UINT32 state, INT64 data, void *ptr) */
CPUINFO_PTR_INIT, /* R/O: void (*init)(const device_config *device, int index, int clock, int (*irqcallback)(const device_config *device, int)) */
CPUINFO_PTR_RESET, /* R/O: void (*reset)(const device_config *device) */
CPUINFO_PTR_EXIT, /* R/O: void (*exit)(const device_config *device) */
CPUINFO_PTR_EXECUTE, /* R/O: int (*execute)(const device_config *device, int cycles) */
CPUINFO_PTR_BURN, /* R/O: void (*burn)(const device_config *device, int cycles) */
CPUINFO_PTR_DISASSEMBLE, /* R/O: offs_t (*disassemble)(const device_config *device, char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram) */
@ -279,66 +277,41 @@ enum
/* helpers for accessing common CPU state */
#define cpu_get_context_size(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CONTEXT_SIZE)
#define cpu_get_input_lines(cpu) cpu_get_info_int(cpu, CPUINFO_INT_INPUT_LINES)
#define cpu_get_output_lines(cpu) cpu_get_info_int(cpu, CPUINFO_INT_OUTPUT_LINES)
#define cpu_get_default_irq_vector(cpu) cpu_get_info_int(cpu, CPUINFO_INT_DEFAULT_IRQ_VECTOR)
#define cpu_get_endianness(cpu) cpu_get_info_int(cpu, CPUINFO_INT_ENDIANNESS)
#define cpu_get_clock_multiplier(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CLOCK_MULTIPLIER)
#define cpu_get_clock_divider(cpu) cpu_get_info_int(cpu, CPUINFO_INT_CLOCK_DIVIDER)
#define cpu_get_min_opcode_bytes(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MIN_INSTRUCTION_BYTES)
#define cpu_get_max_opcode_bytes(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MAX_INSTRUCTION_BYTES)
#define cpu_get_min_cycles(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MIN_CYCLES)
#define cpu_get_max_cycles(cpu) cpu_get_info_int(cpu, CPUINFO_INT_MAX_CYCLES)
#define cpu_get_databus_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_DATABUS_WIDTH + (space))
#define cpu_get_addrbus_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_ADDRBUS_WIDTH + (space))
#define cpu_get_addrbus_shift(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_ADDRBUS_SHIFT + (space))
#define cpu_get_logaddr_width(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_LOGADDR_WIDTH + (space))
#define cpu_get_page_shift(cpu, space) cpu_get_info_int(cpu, CPUINFO_INT_PAGE_SHIFT + (space))
#define cpu_get_reg(cpu, reg) cpu_get_info_int(cpu, CPUINFO_INT_REGISTER + (reg))
#define cpu_get_context_size(cpu) device_get_info_int(cpu, CPUINFO_INT_CONTEXT_SIZE)
#define cpu_get_input_lines(cpu) device_get_info_int(cpu, CPUINFO_INT_INPUT_LINES)
#define cpu_get_output_lines(cpu) device_get_info_int(cpu, CPUINFO_INT_OUTPUT_LINES)
#define cpu_get_default_irq_vector(cpu) device_get_info_int(cpu, CPUINFO_INT_DEFAULT_IRQ_VECTOR)
#define cpu_get_endianness(cpu) device_get_info_int(cpu, CPUINFO_INT_ENDIANNESS)
#define cpu_get_clock_multiplier(cpu) device_get_info_int(cpu, CPUINFO_INT_CLOCK_MULTIPLIER)
#define cpu_get_clock_divider(cpu) device_get_info_int(cpu, CPUINFO_INT_CLOCK_DIVIDER)
#define cpu_get_min_opcode_bytes(cpu) device_get_info_int(cpu, CPUINFO_INT_MIN_INSTRUCTION_BYTES)
#define cpu_get_max_opcode_bytes(cpu) device_get_info_int(cpu, CPUINFO_INT_MAX_INSTRUCTION_BYTES)
#define cpu_get_min_cycles(cpu) device_get_info_int(cpu, CPUINFO_INT_MIN_CYCLES)
#define cpu_get_max_cycles(cpu) device_get_info_int(cpu, CPUINFO_INT_MAX_CYCLES)
#define cpu_get_databus_width(cpu, space) device_get_info_int(cpu, CPUINFO_INT_DATABUS_WIDTH + (space))
#define cpu_get_addrbus_width(cpu, space) device_get_info_int(cpu, CPUINFO_INT_ADDRBUS_WIDTH + (space))
#define cpu_get_addrbus_shift(cpu, space) device_get_info_int(cpu, CPUINFO_INT_ADDRBUS_SHIFT + (space))
#define cpu_get_logaddr_width(cpu, space) device_get_info_int(cpu, CPUINFO_INT_LOGADDR_WIDTH + (space))
#define cpu_get_page_shift(cpu, space) device_get_info_int(cpu, CPUINFO_INT_PAGE_SHIFT + (space))
#define cpu_get_reg(cpu, reg) device_get_info_int(cpu, CPUINFO_INT_REGISTER + (reg))
#define cpu_get_previouspc(cpu) ((offs_t)cpu_get_reg(cpu, REG_PREVIOUSPC))
#define cpu_get_pc(cpu) ((offs_t)cpu_get_reg(cpu, REG_PC))
#define cpu_get_sp(cpu) cpu_get_reg(cpu, REG_SP)
#define cpu_get_icount_ptr(cpu) (int *)cpu_get_info_ptr(cpu, CPUINFO_PTR_INSTRUCTION_COUNTER)
#define cpu_get_debug_register_list(cpu) cpu_get_info_ptr(cpu, CPUINFO_PTR_DEBUG_REGISTER_LIST)
#define cpu_get_name(cpu) cpu_get_info_string(cpu, CPUINFO_STR_NAME)
#define cpu_get_core_family(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_FAMILY)
#define cpu_get_core_version(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_VERSION)
#define cpu_get_core_file(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_FILE)
#define cpu_get_core_credits(cpu) cpu_get_info_string(cpu, CPUINFO_STR_CORE_CREDITS)
#define cpu_get_flags_string(cpu) cpu_get_info_string(cpu, CPUINFO_STR_FLAGS)
#define cpu_get_irq_string(cpu, irq) cpu_get_info_string(cpu, CPUINFO_STR_IRQ_STATE + (irq))
#define cpu_get_reg_string(cpu, reg) cpu_get_info_string(cpu, CPUINFO_STR_REGISTER + (reg))
#define cpu_set_reg(cpu, reg, val) cpu_set_info_int(cpu, CPUINFO_INT_REGISTER + (reg), (val))
/* helpers for accessing common CPU type state */
#define cputype_get_context_size(cputype) cputype_get_info_int(cputype, CPUINFO_INT_CONTEXT_SIZE)
#define cputype_get_input_lines(cputype) cputype_get_info_int(cputype, CPUINFO_INT_INPUT_LINES)
#define cputype_get_output_lines(cputype) cputype_get_info_int(cputype, CPUINFO_INT_OUTPUT_LINES)
#define cputype_get_default_irq_vector(cputype) cputype_get_info_int(cputype, CPUINFO_INT_DEFAULT_IRQ_VECTOR)
#define cputype_get_endianness(cputype) cputype_get_info_int(cputype, CPUINFO_INT_ENDIANNESS)
#define cputype_get_clock_multiplier(cputype) cputype_get_info_int(cputype, CPUINFO_INT_CLOCK_MULTIPLIER)
#define cputype_get_clock_divider(cputype) cputype_get_info_int(cputype, CPUINFO_INT_CLOCK_DIVIDER)
#define cputype_get_min_instruction_bytes(cputype) cputype_get_info_int(cputype, CPUINFO_INT_MIN_INSTRUCTION_BYTES)
#define cputype_get_max_instruction_bytes(cputype) cputype_get_info_int(cputype, CPUINFO_INT_MAX_INSTRUCTION_BYTES)
#define cputype_get_min_cycles(cputype) cputype_get_info_int(cputype, CPUINFO_INT_MIN_CYCLES)
#define cputype_get_max_cycles(cputype) cputype_get_info_int(cputype, CPUINFO_INT_MAX_CYCLES)
#define cputype_get_databus_width(cputype, space) cputype_get_info_int(cputype, CPUINFO_INT_DATABUS_WIDTH + (space))
#define cputype_get_addrbus_width(cputype, space) cputype_get_info_int(cputype, CPUINFO_INT_ADDRBUS_WIDTH + (space))
#define cputype_get_addrbus_shift(cputype, space) cputype_get_info_int(cputype, CPUINFO_INT_ADDRBUS_SHIFT + (space))
#define cputype_get_logaddr_width(cputype, space) cputype_get_info_int(cputype, CPUINFO_INT_LOGADDR_WIDTH + (space))
#define cputype_get_page_shift(cputype, space) cputype_get_info_int(cputype, CPUINFO_INT_PAGE_SHIFT + (space))
#define cputype_get_debug_register_list(cputype) cputype_get_info_ptr(cputype, CPUINFO_PTR_DEBUG_REGISTER_LIST)
#define cputype_get_name(cputype) cputype_get_info_string(cputype, CPUINFO_STR_NAME)
#define cputype_get_core_family(cputype) cputype_get_info_string(cputype, CPUINFO_STR_CORE_FAMILY)
#define cputype_get_core_version(cputype) cputype_get_info_string(cputype, CPUINFO_STR_CORE_VERSION)
#define cputype_get_core_file(cputype) cputype_get_info_string(cputype, CPUINFO_STR_CORE_FILE)
#define cputype_get_core_credits(cputype) cputype_get_info_string(cputype, CPUINFO_STR_CORE_CREDITS)
#define cpu_get_icount_ptr(cpu) (int *)device_get_info_ptr(cpu, CPUINFO_PTR_INSTRUCTION_COUNTER)
#define cpu_get_debug_register_list(cpu) device_get_info_ptr(cpu, CPUINFO_PTR_DEBUG_REGISTER_LIST)
#define cpu_get_name(cpu) device_get_info_string(cpu, CPUINFO_STR_NAME)
#define cpu_get_core_family(cpu) device_get_info_string(cpu, CPUINFO_STR_CORE_FAMILY)
#define cpu_get_core_version(cpu) device_get_info_string(cpu, CPUINFO_STR_CORE_VERSION)
#define cpu_get_core_file(cpu) device_get_info_string(cpu, CPUINFO_STR_CORE_FILE)
#define cpu_get_core_credits(cpu) device_get_info_string(cpu, CPUINFO_STR_CORE_CREDITS)
#define cpu_get_flags_string(cpu) device_get_info_string(cpu, CPUINFO_STR_FLAGS)
#define cpu_get_irq_string(cpu, irq) device_get_info_string(cpu, CPUINFO_STR_IRQ_STATE + (irq))
#define cpu_get_reg_string(cpu, reg) device_get_info_string(cpu, CPUINFO_STR_REGISTER + (reg))
#define cpu_set_reg(cpu, reg, val) device_set_info_int(cpu, CPUINFO_INT_REGISTER + (reg), (val))
/* helpers for using machine/cputag instead of cpu objects */
#define cputag_reset(mach, tag) cpu_reset(cputag_get_cpu(mach, tag))
#define cputag_reset(mach, tag) device_reset(cputag_get_cpu(mach, tag))
#define cputag_get_index(mach, tag) cpu_get_index(cputag_get_cpu(mach, tag))
#define cputag_get_address_space(mach, tag, space) cpu_get_address_space(cputag_get_cpu(mach, tag), space)
@ -412,7 +385,6 @@ union _cpuinfo
typedef struct _cpu_class_header cpu_class_header;
struct _cpu_class_header
{
int index; /* index of this CPU */
cpu_debug_data * debug; /* debugging data */
const address_space * space[ADDRESS_SPACES]; /* address spaces */
@ -423,10 +395,6 @@ struct _cpu_class_header
cpu_translate_func translate;
cpu_disassemble_func disassemble;
cpu_disassemble_func dasm_override;
/* other frequently-needed information */
UINT32 clock_divider;
UINT32 clock_multiplier;
};
@ -440,10 +408,6 @@ struct _cpu_class_header
#define cpu_next(previous) device_list_next((previous), CPU)
/* signal a reset for a given CPU */
#define cpu_reset device_reset
/* eventually all drivers should include the CPU core's header, which should define these */
CPU_GET_INFO( dummy );
@ -902,29 +866,8 @@ CPU_GET_INFO( cxd8661r );
***************************************************************************/
/* ----- global management ----- */
/* reset the internal CPU tracking */
void cpuintrf_init(running_machine *machine);
/* circular string buffer */
char *cpuintrf_temp_str(void);
/* ----- live CPU accessors ----- */
/* return information about a live CPU */
INT64 cpu_get_info_int(const device_config *cpu, UINT32 state);
void *cpu_get_info_ptr(const device_config *cpu, UINT32 state);
genf *cpu_get_info_fct(const device_config *cpu, UINT32 state);
const char *cpu_get_info_string(const device_config *cpu, UINT32 state);
/* set information about a live CPU */
void cpu_set_info_int(const device_config *cpu, UINT32 state, INT64 data);
void cpu_set_info_ptr(const device_config *cpu, UINT32 state, void *data);
void cpu_set_info_fct(const device_config *cpu, UINT32 state, genf *data);
/* return the PC, corrected to a byte offset and translated to physical space, on a given CPU */
offs_t cpu_get_physical_pc_byte(const device_config *cpu);
@ -936,16 +879,6 @@ void cpu_set_dasm_override(const device_config *cpu, cpu_disassemble_func dasm_o
/* ----- CPU type accessors ----- */
/* return information about a given CPU type */
INT64 cputype_get_info_int(cpu_type cputype, UINT32 state);
void *cputype_get_info_ptr(cpu_type cputype, UINT32 state);
genf *cputype_get_info_fct(cpu_type cputype, UINT32 state);
const char *cputype_get_info_string(cpu_type cputype, UINT32 state);
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/

2
src/emu/debug/debugcmd.c
View File

@ -248,7 +248,7 @@ void debug_command_init(running_machine *machine)
for (cpu = machine->cpu[0]; cpu != NULL; cpu = cpu->typenext)
{
cpu_debug_init_func debug_init;
debug_init = (cpu_debug_init_func)cpu_get_info_fct(cpu, CPUINFO_PTR_DEBUG_INIT);
debug_init = (cpu_debug_init_func)device_get_info_fct(cpu, CPUINFO_PTR_DEBUG_INIT);
if (debug_init != NULL)
(*debug_init)(cpu);
}

6
src/emu/debug/debugcpu.c
View File

@ -206,9 +206,9 @@ void debug_cpu_init(running_machine *machine)
info->opwidth = cpu_get_min_opcode_bytes(info->device);
/* fetch the memory accessors */
info->read = (cpu_read_func)cpu_get_info_fct(info->device, CPUINFO_PTR_READ);
info->write = (cpu_write_func)cpu_get_info_fct(info->device, CPUINFO_PTR_WRITE);
info->readop = (cpu_readop_func)cpu_get_info_fct(info->device, CPUINFO_PTR_READOP);
info->read = (cpu_read_func)device_get_info_fct(info->device, CPUINFO_PTR_READ);
info->write = (cpu_write_func)device_get_info_fct(info->device, CPUINFO_PTR_WRITE);
info->readop = (cpu_readop_func)device_get_info_fct(info->device, CPUINFO_PTR_READOP);
/* allocate a symbol table */
info->symtable = symtable_alloc(global->symtable, (void *)cpu);

1
src/emu/devintrf.c
View File

@ -644,7 +644,6 @@ INT64 device_get_info_int(const device_config *device, UINT32 state)
deviceinfo info;
assert(device != NULL);
assert(device->token != NULL);
assert(device->type != NULL);
assert(state >= DEVINFO_INT_FIRST && state <= DEVINFO_INT_LAST);

2
src/emu/mame.c
View File

@ -25,7 +25,6 @@
- calls init_machine() [mame.c]
init_machine() [mame.c]
- calls cpuintrf_init() [cpuintrf.c] to determine which CPUs are available
- calls sndintrf_init() [sndintrf.c] to determine which sound chips are available
- calls fileio_init() [fileio.c] to initialize file I/O info
- calls config_init() [config.c] to initialize configuration system
@ -1470,7 +1469,6 @@ static void init_machine(running_machine *machine)
time_t newbase;
/* initialize basic can't-fail systems here */
cpuintrf_init(machine);
sndintrf_init(machine);
fileio_init(machine);
config_init(machine);

2
src/emu/memory.c
View File

@ -760,7 +760,7 @@ address_map *address_map_alloc(const device_config *device, const game_driver *d
memset(map, 0, sizeof(*map));
/* append the internal CPU map (first so it takes priority) */
internal_map = (const addrmap_token *)cputype_get_info_ptr(cpuconfig->type, CPUINFO_PTR_INTERNAL_MEMORY_MAP + spacenum);
internal_map = (const addrmap_token *)device_get_info_ptr(device, CPUINFO_PTR_INTERNAL_MEMORY_MAP + spacenum);
if (internal_map != NULL)
map_detokenize(map, driver, device->tag, internal_map);

7
src/emu/validity.c
View File

@ -724,8 +724,8 @@ static int validate_cpu(int drivnum, const machine_config *config, const input_p
int spacenum;
/* check the CPU for incompleteness */
if (cpu_get_info_fct(device, CPUINFO_PTR_RESET) == NULL ||
cpu_get_info_fct(device, CPUINFO_PTR_EXECUTE) == NULL)
if (device_get_info_fct(device, CPUINFO_PTR_RESET) == NULL ||
device_get_info_fct(device, CPUINFO_PTR_EXECUTE) == NULL)
{
mame_printf_error("%s: %s uses an incomplete CPU\n", driver->source_file, driver->name);
error = TRUE;
@ -733,7 +733,7 @@ static int validate_cpu(int drivnum, const machine_config *config, const input_p
}
/* check for CPU-specific validity check */
cpu_validity_check = (cpu_validity_check_func) cpu_get_info_fct(device, CPUINFO_PTR_VALIDITY_CHECK);
cpu_validity_check = (cpu_validity_check_func) device_get_info_fct(device, CPUINFO_PTR_VALIDITY_CHECK);
if (cpu_validity_check != NULL && (*cpu_validity_check)(driver, device->static_config))
error = TRUE;
@ -1620,7 +1620,6 @@ int mame_validitychecks(const game_driver *curdriver)
error = validate_inlines() || error;
/* make sure the CPU and sound interfaces are up and running */
cpuintrf_init(NULL);
sndintrf_init(NULL);
init_resource_tracking();

2
src/mame/audio/leland.c
View File

@ -617,7 +617,7 @@ static IRQ_CALLBACK( int_callback )
if (LOG_INTERRUPTS) logerror("(%f) **** Acknowledged interrupt vector %02X\n", attotime_to_double(timer_get_time(device->machine)), i80186.intr.poll_status & 0x1f);
/* clear the interrupt */
cpu_set_info_int(device, CPUINFO_INT_INPUT_STATE + 0, CLEAR_LINE);
device_set_info_int(device, CPUINFO_INT_INPUT_STATE + 0, CLEAR_LINE);
i80186.intr.pending = 0;
/* clear the request and set the in-service bit */

2
src/mame/audio/taito_en.c
View File

@ -258,7 +258,7 @@ void taito_f3_soundsystem_reset(running_machine *machine)
sound_ram[3]=ROM[0x80003];
/* reset CPU to catch any banking of startup vectors */
cpu_reset(cputag_get_cpu(machine, "audio"));
device_reset(cputag_get_cpu(machine, "audio"));
//cpu_set_input_line(machine->cpu[1], INPUT_LINE_RESET, ASSERT_LINE);
}

2
src/mame/drivers/cham24.c
View File

@ -203,7 +203,7 @@ static MACHINE_RESET( cham24 )
memcpy( &dst[0x8000], &src[0x0f8000], 0x4000 );
memcpy( &dst[0xc000], &src[0x0f8000], 0x4000 );
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
/* reset the ppu */
ppu2c0x_reset( machine, 0, 1 );

2
src/mame/drivers/cps3.c
View File

@ -725,7 +725,7 @@ static DRIVER_INIT( cps3 )
int i;
// set strict verify
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY);
cps3_key1 = -1;
cps3_key2 = -1;

12
src/mame/drivers/ddenlovr.c
View File

@ -6594,7 +6594,7 @@ static INTERRUPT_GEN( quizchq_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise quizchq would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
if ((++count % 60) == 0)
@ -6674,7 +6674,7 @@ static INTERRUPT_GEN( mmpanic_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise the game would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
if ((++count % 60) == 0)
@ -6746,7 +6746,7 @@ static INTERRUPT_GEN( hanakanz_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise quizchq would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
if ((++count % 60) == 0)
@ -6822,7 +6822,7 @@ static INTERRUPT_GEN( mjchuuka_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise quizchq would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
if ((++count % 60) == 0)
@ -6880,7 +6880,7 @@ static INTERRUPT_GEN( mjmyster_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise quizchq would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
switch( cpu_getiloops(device) )
@ -6936,7 +6936,7 @@ static INTERRUPT_GEN( hginga_irq )
/* I haven't found a irq ack register, so I need this kludge to
make sure I don't lose any interrupt generated by the blitter,
otherwise hginga would lock up. */
if (cpu_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
if (device_get_info_int(device,CPUINFO_INT_INPUT_STATE + 0))
return;
if ((++count % 60) == 0)

10
src/mame/drivers/deco_mlc.c
View File

@ -723,13 +723,13 @@ static READ32_HANDLER( avengrgs_speedup_r )
static DRIVER_INIT( avengrgs )
{
// init options
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
// set up speed cheat
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x3234);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x32dc);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x3234);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x32dc);
mainCpuIsArm=0;
memory_install_read32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x01089a0, 0x01089a3, 0, 0, avengrgs_speedup_r );

12
src/mame/drivers/firebeat.c
View File

@ -1764,14 +1764,14 @@ static UINT32 *work_ram;
static MACHINE_START( firebeat )
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x01ffffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x01ffffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}
static ADDRESS_MAP_START( firebeat_map, ADDRESS_SPACE_PROGRAM, 32 )

2
src/mame/drivers/flyball.c
View File

@ -72,7 +72,7 @@ static MACHINE_RESET( flyball )
for (i = 0; i < 0x1000; i++)
rombase[i] = ROM[i ^ 0x1ff];
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
timer_set(machine, video_screen_get_time_until_pos(machine->primary_screen, 0, 0), NULL, 0, flyball_quarter_callback);
}

2
src/mame/drivers/galivan.c
View File

@ -53,7 +53,7 @@ static MACHINE_RESET( galivan )
UINT8 *RAM = memory_region(machine, "main");
memory_set_bankptr(machine, 1,&RAM[0x10000]);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
// layers = 0x60;
}

2
src/mame/drivers/gladiatr.c
View File

@ -271,7 +271,7 @@ static MACHINE_RESET( gladiator )
{
UINT8 *rom = memory_region(machine, "audio") + 0x10000;
memory_set_bankptr(machine, 2,rom);
cpu_reset(machine->cpu[2]);
device_reset(machine->cpu[2]);
}
}

12
src/mame/drivers/gticlub.c
View File

@ -598,14 +598,14 @@ WRITE32_HANDLER( lanc_ram_w )
static MACHINE_START( gticlub )
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}
static ADDRESS_MAP_START( gticlub_map, ADDRESS_SPACE_PROGRAM, 32 )

32
src/mame/drivers/hng64.c
View File

@ -1488,26 +1488,26 @@ static MACHINE_RESET(hyperneo)
activeBuffer = 0 ;
/* set the fastest DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x00ffffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_mainram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x00ffffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_mainram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x04000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x05ffffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_cart);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x04000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x05ffffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, hng_cart);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
}

12
src/mame/drivers/hornet.c
View File

@ -1007,14 +1007,14 @@ static MACHINE_START( hornet )
memset(jvs_sdata, 0, 1024);
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
state_save_register_global(machine, led_reg0);
state_save_register_global(machine, led_reg1);

2
src/mame/drivers/itech8.c
View File

@ -681,7 +681,7 @@ static MACHINE_RESET( itech8 )
if (main_cpu_type == CPU_M6809 || main_cpu_type == CPU_HD6309)
{
memory_set_bankptr(machine, 1, &memory_region(machine, "main")[0x4000]);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
}
/* reset the PIA (if used) */

32
src/mame/drivers/kinst.c
View File

@ -190,26 +190,26 @@ static MACHINE_START( kinst )
}
/* set the fastest DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
}

2
src/mame/drivers/lethal.c
View File

@ -593,7 +593,7 @@ static MACHINE_RESET( lethalen )
memory_set_bankptr(machine, 1, &prgrom[0x10000]);
memory_set_bankptr(machine, 2, &prgrom[0x48000]);
/* force reset again to read proper reset vector */
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
}
static const gfx_layout lethal_6bpp =

2
src/mame/drivers/mediagx.c
View File

@ -957,7 +957,7 @@ static MACHINE_RESET(mediagx)
cpu_set_irq_callback(machine->cpu[0], irq_callback);
memcpy(bios_ram, rom, 0x40000);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
dacl = auto_malloc(65536 * sizeof(INT16));
dacr = auto_malloc(65536 * sizeof(INT16));

6
src/mame/drivers/megadriv.c
View File

@ -6492,7 +6492,7 @@ static void megadriv_init_common(running_machine *machine)
vdp_get_word_from_68k_mem = vdp_get_word_from_68k_mem_default;
cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_TAS_CALLBACK, (void *)megadriv_tas_callback);
device_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_TAS_CALLBACK, (void *)megadriv_tas_callback);
if ((machine->gamedrv->ipt==ipt_megadri6) || (machine->gamedrv->ipt==ipt_ssf2ghw))
{
@ -6706,8 +6706,8 @@ DRIVER_INIT( _32x )
_32x_240mode = 0;
// checking if these help brutal, they don't.
cpu_set_info_int(machine->cpu[2], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_COMPATIBLE_OPTIONS);
cpu_set_info_int(machine->cpu[3], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[2], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[3], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_COMPATIBLE_OPTIONS);
DRIVER_INIT_CALL(megadriv);
}

4
src/mame/drivers/midvunit.c
View File

@ -74,7 +74,7 @@ static MACHINE_RESET( midvunit )
dcs_reset_w(0);
memcpy(ram_base, memory_region(machine, "user1"), 0x20000*4);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
timer[0] = timer_alloc(machine, NULL, NULL);
timer[1] = timer_alloc(machine, NULL, NULL);
@ -87,7 +87,7 @@ static MACHINE_RESET( midvplus )
dcs_reset_w(0);
memcpy(ram_base, memory_region(machine, "user1"), 0x20000*4);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
timer[0] = timer_alloc(machine, NULL, NULL);
timer[1] = timer_alloc(machine, NULL, NULL);

2
src/mame/drivers/midzeus.c
View File

@ -93,7 +93,7 @@ static MACHINE_RESET( midzeus )
{
memcpy(ram_base, memory_region(machine, "user1"), 0x40000*4);
*ram_base <<= 1;
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
cmos_protected = TRUE;
}

2
src/mame/drivers/model2.c
View File

@ -353,7 +353,7 @@ static MACHINE_RESET(model2_scsp)
// copy the 68k vector table into RAM
memcpy(model2_soundram, memory_region(machine, "audio")+0x80000, 16);
cpu_reset(cputag_get_cpu(machine, "audio"));
device_reset(cputag_get_cpu(machine, "audio"));
}
static MACHINE_RESET(model2)

14
src/mame/drivers/model3.c
View File

@ -981,14 +981,14 @@ static void model3_exit(running_machine *machine)
static void configure_fast_ram(running_machine *machine)
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS - PPCDRC_ACCURATE_SINGLES);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x007fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x007fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}
static MACHINE_START(model3_10)
@ -1022,7 +1022,7 @@ static void model3_init(running_machine *machine, int step)
// copy the 68k vector table into RAM
memcpy(model3_soundram, memory_region(machine, "audio")+0x80000, 16);
cpu_reset(cputag_get_cpu(machine, "audio"));
device_reset(cputag_get_cpu(machine, "audio"));
model3_machine_init(step); // step 1.5
model3_tap_reset();

2
src/mame/drivers/mpu4.c
View File

@ -434,7 +434,7 @@ static MACHINE_RESET( mpu4 )
memory_configure_bank(machine, 1, 0, 8, &rom[0x01000], 0x10000);
memory_set_bank(machine, 1,0);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
}
}

2
src/mame/drivers/neogeo.c
View File

@ -1011,7 +1011,7 @@ static MACHINE_RESET( neogeo )
/* reset system control registers */
for (offs = 0; offs < 8; offs++)
system_control_w(space, offs, 0, 0x00ff);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
neogeo_reset_rng();

16
src/mame/drivers/nwk-tr.c
View File

@ -949,14 +949,14 @@ static WRITE32_HANDLER( lanc2_w )
static MACHINE_START( nwktr )
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x003fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, work_ram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}
static ADDRESS_MAP_START( nwktr_map, ADDRESS_SPACE_PROGRAM, 32 )
@ -1162,8 +1162,8 @@ static DRIVER_INIT(nwktr)
K056800_init(machine, sound_irq_callback);
K033906_init(machine);
// cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_SPU_TX_HANDLER, (genf *)jamma_jvs_w);
// cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_SPU_RX_HANDLER, (genf *)jamma_jvs_r);
// device_set_info_fct(machine->cpu[0], CPUINFO_PTR_SPU_TX_HANDLER, (genf *)jamma_jvs_w);
// device_set_info_fct(machine->cpu[0], CPUINFO_PTR_SPU_RX_HANDLER, (genf *)jamma_jvs_r);
adc1213x_init(0, adc12138_input_callback);
lanc2_init();

18
src/mame/drivers/psikyosh.c
View File

@ -1139,13 +1139,13 @@ ROM_END
static DRIVER_INIT( soldivid )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_0;
}
static DRIVER_INIT( s1945ii )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_DEFAULT;
}
@ -1153,13 +1153,13 @@ static DRIVER_INIT( daraku )
{
UINT8 *RAM = memory_region(machine, "main");
memory_set_bankptr(machine, 1,&RAM[0x100000]);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_DARAKU;
}
static DRIVER_INIT( sbomberb )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_DEFAULT;
}
@ -1167,7 +1167,7 @@ static DRIVER_INIT( gunbird2 )
{
UINT8 *RAM = memory_region(machine, "main");
memory_set_bankptr(machine, 1,&RAM[0x100000]);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_DEFAULT;
}
@ -1175,25 +1175,25 @@ static DRIVER_INIT( s1945iii )
{
UINT8 *RAM = memory_region(machine, "main");
memory_set_bankptr(machine, 1,&RAM[0x100000]);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_S1945III;
}
static DRIVER_INIT( dragnblz )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_DRAGNBLZ;
}
static DRIVER_INIT( gnbarich )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_GNBARICH;
}
static DRIVER_INIT( mjgtaste )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
use_factory_eeprom=eeprom_MJGTASTE;
/* needs to install mahjong controls too (can select joystick in test mode tho) */
}

30
src/mame/drivers/seattle.c
View File

@ -511,20 +511,20 @@ static MACHINE_START( seattle )
galileo.timer[3].timer = timer_alloc(machine, galileo_timer_callback, NULL);
/* set the fastest DRC options, but strict verification */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
/* register for save states */
state_save_register_global_array(machine, galileo.reg);
@ -2813,10 +2813,10 @@ static void init_common(running_machine *machine, int ioasic, int serialnum, int
static void add_speedup(running_machine *machine, offs_t pc, UINT32 op)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
}

2
src/mame/drivers/segaorun.c
View File

@ -257,7 +257,7 @@ static MACHINE_RESET( outrun )
segaic16_tilemap_reset(machine, 0);
/* hook the RESET line, which resets CPU #1 */
cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)outrun_reset);
device_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)outrun_reset);
/* start timers to track interrupts */
timer_set(machine, video_screen_get_time_until_pos(machine->primary_screen, 223, 0), NULL, 223, scanline_callback);

2
src/mame/drivers/segaxbd.c
View File

@ -210,7 +210,7 @@ static MACHINE_RESET( xboard )
segaic16_tilemap_reset(machine, 0);
/* hook the RESET line, which resets CPU #1 */
cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)xboard_reset);
device_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)xboard_reset);
/* set up the compare/timer chip */
segaic16_compare_timer_init(0, sound_data_w, timer_ack_callback);

8
src/mame/drivers/stv.c
View File

@ -1971,14 +1971,14 @@ static WRITE32_HANDLER( minit_w )
logerror("cpu %s (PC=%08X) MINIT write = %08x\n", space->cpu->tag, cpu_get_pc(space->cpu),data);
cpuexec_boost_interleave(space->machine, minit_boost_timeslice, ATTOTIME_IN_USEC(minit_boost));
cpuexec_trigger(space->machine, 1000);
cpu_set_info_int(space->machine->cpu[1], CPUINFO_INT_SH2_FRT_INPUT, PULSE_LINE);
device_set_info_int(space->machine->cpu[1], CPUINFO_INT_SH2_FRT_INPUT, PULSE_LINE);
}
static WRITE32_HANDLER( sinit_w )
{
logerror("cpu %s (PC=%08X) SINIT write = %08x\n", space->cpu->tag, cpu_get_pc(space->cpu),data);
cpuexec_boost_interleave(space->machine, sinit_boost_timeslice, ATTOTIME_IN_USEC(sinit_boost));
cpu_set_info_int(space->machine->cpu[0], CPUINFO_INT_SH2_FRT_INPUT, PULSE_LINE);
device_set_info_int(space->machine->cpu[0], CPUINFO_INT_SH2_FRT_INPUT, PULSE_LINE);
}
@ -2329,8 +2329,8 @@ DRIVER_INIT ( stv )
// do strict overwrite verification - maruchan and rsgun crash after coinup without this.
// cottonbm needs strict PCREL
// todo: test what games need this and don't turn it on for them...
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
/* debug .. watch the command buffer rsgun, cottonbm etc. appear to use to communicate between cpus */
memory_install_write32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x60ffc44, 0x60ffc47, 0, 0, w60ffc44_write );

324
src/mame/drivers/stvinit.c
View File

@ -119,15 +119,15 @@ NVRAM_HANDLER( stv )
void install_stvbios_speedups(running_machine *machine)
{
// flushes 0 & 1 on both CPUs are for the BIOS speedups
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60154b2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013aee);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60154b2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013aee);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60154b2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013aee);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60154b2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013aee);
}
DRIVER_INIT(shienryu)
@ -136,11 +136,11 @@ DRIVER_INIT(shienryu)
stv_default_eeprom_length = sizeof(shienryu_default_eeprom);
// master
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60041c6);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60041c6);
// slave
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600440e);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600440e);
DRIVER_INIT_CALL(stv);
}
@ -155,11 +155,11 @@ DRIVER_INIT(prikura)
(loops for 263473 instructions)
*/
// master
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6018640);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6018640);
// slave
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6018c6e);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6018c6e);
DRIVER_INIT_CALL(stv);
@ -187,8 +187,8 @@ DRIVER_INIT(hanagumi)
(loops for 288688 instructions)
*/
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6010160);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6010160);
DRIVER_INIT_CALL(stv);
}
@ -214,11 +214,11 @@ CPU0: Aids Screen
DRIVER_INIT(puyosun)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6021cf0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6021cf0);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60236fe);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60236fe);
DRIVER_INIT_CALL(stv);
@ -238,8 +238,8 @@ CPU0 Data East Logo:
DRIVER_INIT(mausuke)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60461A0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60461A0);
DRIVER_INIT_CALL(stv);
@ -249,10 +249,10 @@ DRIVER_INIT(mausuke)
DRIVER_INIT(cottonbm)
{
// cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
// cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6030ee2);
// cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
// cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6032b52);
// device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
// device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6030ee2);
// device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
// device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6032b52);
DRIVER_INIT_CALL(stv);
@ -261,10 +261,10 @@ DRIVER_INIT(cottonbm)
DRIVER_INIT(cotton2)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6031c7a);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60338ea);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6031c7a);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60338ea);
DRIVER_INIT_CALL(stv);
@ -274,19 +274,19 @@ DRIVER_INIT(cotton2)
DRIVER_INIT(dnmtdeka)
{
// install all 3 speedups on both master and slave
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c90);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c90);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c90);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c90);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
DRIVER_INIT_CALL(stv);
}
@ -294,31 +294,31 @@ DRIVER_INIT(dnmtdeka)
DRIVER_INIT(diehard)
{
// install all 3 speedups on both master and slave
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c98);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c98);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c98);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6027c98);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0xd04);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60051f2);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT(fhboxers)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60041c2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600bb0a);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600b31e);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60041c2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600bb0a);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x600b31e);
DRIVER_INIT_CALL(stv);
}
@ -342,15 +342,15 @@ static READ32_HANDLER( groovef_hack2_r )
DRIVER_INIT( groovef )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6005e7c);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6005e86);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60a4970);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6005e7c);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6005e86);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60a4970);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60060c2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60060c2);
/* prevent game from hanging on startup -- todo: remove these hacks */
memory_install_read32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x60ca6cc, 0x60ca6cf, 0, 0, groovef_hack2_r );
@ -399,12 +399,12 @@ static READ32_HANDLER( danchih_hack_r )
DRIVER_INIT( danchih )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028b28);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028c8e);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602ae26);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028b28);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028c8e);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602ae26);
/* prevent game from hanging on title screen -- todo: remove these hacks */
memory_install_read32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x60ffcbc, 0x60ffcbf, 0, 0, danchih_hack_r );
@ -445,10 +445,10 @@ static READ32_HANDLER( astrass_hack_r )
DRIVER_INIT( astrass )
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60011b8);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605b9da);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60011b8);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605b9da);
memory_install_read32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x06000770, 0x06000773, 0, 0, astrass_hack_r );
@ -459,12 +459,12 @@ DRIVER_INIT( astrass )
DRIVER_INIT(thunt)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602A024);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013EEA);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602AAF8);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602A024);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013EEA);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602AAF8);
DRIVER_INIT_CALL(stv);
@ -473,12 +473,12 @@ DRIVER_INIT(thunt)
DRIVER_INIT(sandor)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602a0f8);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013fbe);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602abcc);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602a0f8);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT+1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013fbe);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602abcc);
DRIVER_INIT_CALL(stv);
minit_boost_timeslice = sinit_boost_timeslice = ATTOTIME_IN_USEC(1);
@ -487,10 +487,10 @@ DRIVER_INIT(sandor)
DRIVER_INIT(grdforce)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6041e32);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6043aa2);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6041e32);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6043aa2);
DRIVER_INIT_CALL(stv);
@ -499,10 +499,10 @@ DRIVER_INIT(grdforce)
DRIVER_INIT(batmanfr)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60121c0);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60125bc);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60121c0);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60125bc);
DRIVER_INIT_CALL(stv);
@ -512,8 +512,8 @@ DRIVER_INIT(batmanfr)
DRIVER_INIT(colmns97)
{
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60298a2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60298a2);
DRIVER_INIT_CALL(stv);
@ -523,10 +523,10 @@ DRIVER_INIT(colmns97)
DRIVER_INIT(winterht)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6098aea);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x609ae4e);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6098aea);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x609ae4e);
DRIVER_INIT_CALL(stv);
@ -535,10 +535,10 @@ DRIVER_INIT(winterht)
DRIVER_INIT(seabass)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602cbfa);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60321ee);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602cbfa);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60321ee);
DRIVER_INIT_CALL(stv);
@ -547,10 +547,10 @@ DRIVER_INIT(seabass)
DRIVER_INIT(vfremix)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602c30c);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x604c332);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602c30c);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x604c332);
DRIVER_INIT_CALL(stv);
@ -559,10 +559,10 @@ DRIVER_INIT(vfremix)
DRIVER_INIT(sss)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6026398);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028cd6);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6026398);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6028cd6);
install_standard_protection(machine);
@ -573,10 +573,10 @@ DRIVER_INIT(sss)
DRIVER_INIT(othellos)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602bcbe);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602d92e);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602bcbe);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602d92e);
DRIVER_INIT_CALL(stv);
@ -586,8 +586,8 @@ DRIVER_INIT(othellos)
DRIVER_INIT(sasissu)
{
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60710be);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60710be);
DRIVER_INIT_CALL(stv);
@ -596,16 +596,16 @@ DRIVER_INIT(sasissu)
DRIVER_INIT(gaxeduel)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6012ee4);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6012ee4);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT(suikoenb)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013f7a);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6013f7a);
DRIVER_INIT_CALL(stv);
}
@ -620,10 +620,10 @@ DRIVER_INIT(sokyugrt)
DRIVER_INIT(znpwfv)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6012ec2);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60175a6);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6012ec2);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x60175a6);
DRIVER_INIT_CALL(stv);
minit_boost_timeslice = sinit_boost_timeslice = ATTOTIME_IN_NSEC(500);
@ -631,10 +631,10 @@ DRIVER_INIT(znpwfv)
DRIVER_INIT(twcup98)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605edde);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6062bca);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605edde);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6062bca);
DRIVER_INIT_CALL(stv);
install_standard_protection(machine);
@ -644,10 +644,10 @@ DRIVER_INIT(twcup98)
DRIVER_INIT(smleague)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6063bf4);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6062bca);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6063bf4);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6062bca);
DRIVER_INIT_CALL(stv);
@ -656,8 +656,8 @@ DRIVER_INIT(smleague)
DRIVER_INIT(finlarch)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6064d60);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6064d60);
DRIVER_INIT_CALL(stv);
@ -665,10 +665,10 @@ DRIVER_INIT(finlarch)
DRIVER_INIT(maruchan)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601ba46);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601ba46);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601ba46);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601ba46);
DRIVER_INIT_CALL(stv);
@ -677,26 +677,26 @@ DRIVER_INIT(maruchan)
DRIVER_INIT(pblbeach)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605eb78);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605eb78);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT(shanhigw)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6020c5c);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6020c5c);
DRIVER_INIT_CALL(stv);
}
DRIVER_INIT(elandore)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x604eac0);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605340a);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x604eac0);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x605340a);
install_standard_protection(machine);
@ -707,10 +707,10 @@ DRIVER_INIT(elandore)
DRIVER_INIT(rsgun)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6034d04);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6036152);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6034d04);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6036152);
install_standard_protection(machine);
@ -734,10 +734,10 @@ DRIVER_INIT(decathlt)
DRIVER_INIT(nameclv3)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601eb4c);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
cpu_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602b80e);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x601eb4c);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_SELECT, FIRST_SPEEDUP_SLOT);
device_set_info_int(machine->cpu[1], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x602b80e);
DRIVER_INIT_CALL(stv);
}

10
src/mame/drivers/suprnova.c
View File

@ -1017,17 +1017,17 @@ static READ32_HANDLER( sengekij_speedup_r ) // 60006ee 600308e
static void init_skns(running_machine *machine)
{
// init DRC to fastest options
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_FASTEST_OPTIONS);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6f8);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, 0x6f8);
memory_install_read32_handler(cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM), 0x6000028, 0x600002b, 0, 0, bios_skip_r );
}
static void set_drc_pcflush(running_machine *machine, UINT32 addr)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, addr);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH2_PCFLUSH_ADDR, addr);
}
static DRIVER_INIT( galpani4 ) { skns_sprite_kludge(-5,-1); init_skns(machine); }

2
src/mame/drivers/tmaster.c
View File

@ -832,7 +832,7 @@ static MACHINE_RESET( galgames )
memory_set_bank(machine, 2, 0); // ram
memory_set_bank(machine, 4, 0); // ram
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
}
static MACHINE_DRIVER_START( galgames )

2
src/mame/drivers/toaplan2.c
View File

@ -308,7 +308,7 @@ static MACHINE_RESET( toaplan2 )
This is important for games with common RAM; the RAM test will fail
when leaving service mode if the sound CPU is not reset.
*/
cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)toaplan2_reset);
device_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)toaplan2_reset);
}
static MACHINE_RESET( ghox )

22
src/mame/drivers/ultrsprt.c
View File

@ -81,20 +81,20 @@ static WRITE32_HANDLER( int_ack_w )
static MACHINE_START( ultrsprt )
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x0007ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, vram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x0007ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, vram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x7f000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x7f01ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x7f000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x7f01ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}

30
src/mame/drivers/vegas.c
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@ -545,20 +545,20 @@ static MACHINE_START( vegas )
dcs_idma_cs = 0;
/* set the fastest DRC options, but strict verification */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY + MIPS3DRC_FLUSH_PC);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, ramsize - 1);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, ramsize - 1);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1);
/* register for save states */
state_save_register_global(machine, nile_irq_state);
@ -2488,10 +2488,10 @@ static void init_common(running_machine *machine, int ioasic, int serialnum)
static void add_speedup(running_machine *machine, offs_t pc, UINT32 op)
{
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_SELECT, speedup_index++);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_PC, pc);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_OPCODE, op);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_HOTSPOT_CYCLES, 250);
}

12
src/mame/drivers/zr107.c
View File

@ -459,14 +459,14 @@ static UINT32 *workram;
static MACHINE_START( zr107 )
{
/* set conservative DRC options */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_DRC_OPTIONS, PPCDRC_COMPATIBLE_OPTIONS);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_END, 0x000fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_PPC_FASTRAM_BASE, workram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_PPC_FASTRAM_READONLY, 0);
}
static ADDRESS_MAP_START( zr107_map, ADDRESS_SPACE_PROGRAM, 32 )

2
src/mame/machine/amiga.c
View File

@ -304,7 +304,7 @@ MACHINE_RESET( amiga )
// const address_space *space = cpu_get_address_space(machine->cpu[0], ADDRESS_SPACE_PROGRAM);
/* set m68k reset function */
cpu_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)amiga_m68k_reset);
device_set_info_fct(machine->cpu[0], CPUINFO_PTR_M68K_RESET_CALLBACK, (genf *)amiga_m68k_reset);
amiga_m68k_reset(machine->cpu[0]);

2
src/mame/machine/balsente.c
View File

@ -189,7 +189,7 @@ MACHINE_RESET( balsente )
memory_configure_bank(machine, 2, 0, numbanks, &memory_region(machine, "main")[0x12000], 0x6000);
memory_set_bank(space->machine, 1, 0);
memory_set_bank(space->machine, 2, 0);
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
/* start a timer to generate interrupts */
scanline_timer = timer_alloc(machine, interrupt_timer, NULL);

14
src/mame/machine/dc.c
View File

@ -237,7 +237,7 @@ int level;
}
level=dc_compute_interrupt_level(machine);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_SH4_IRLn_INPUT, 15-level);
device_set_info_int(machine->cpu[0], CPUINFO_INT_SH4_IRLn_INPUT, 15-level);
}
READ64_HANDLER( dc_sysctrl_r )
@ -279,7 +279,7 @@ WRITE64_HANDLER( dc_sysctrl_w )
ddtdata.direction=0;
ddtdata.channel=2;
ddtdata.mode=25; //011001
cpu_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
device_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
#if DEBUG_SYSCTRL
if ((address >= 0x11000000) && (address <= 0x11FFFFFF))
if (dc_sysctrl_regs[SB_LMMODE0])
@ -386,7 +386,7 @@ WRITE64_HANDLER( dc_maple_w )
ddtdata.direction=0; // 0 source to buffer, 1 buffer to source
ddtdata.channel= -1; // not used
ddtdata.mode= -1; // copy from/to buffer
cpu_set_info_ptr(space->machine->cpu[0], CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA, &ddtdata);
device_set_info_ptr(space->machine->cpu[0], CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA, &ddtdata);
maple_regs[reg] = 0;
endflag=buff[0] & 0x80000000;
@ -418,7 +418,7 @@ WRITE64_HANDLER( dc_maple_w )
ddtdata.direction=0;
ddtdata.channel= -1;
ddtdata.mode=-1;
cpu_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
device_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
chk=0;
for (a=1;a < length;a++)
{
@ -446,7 +446,7 @@ WRITE64_HANDLER( dc_maple_w )
ddtdata.direction=0;
ddtdata.channel= -1;
ddtdata.mode=-1;
cpu_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
device_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
subcommand = buff[0] & 0xff;
#if DEBUG_MAPLE
@ -656,7 +656,7 @@ WRITE64_HANDLER( dc_maple_w )
ddtdata.destination=destination;
ddtdata.buffer=buff;
ddtdata.direction=1;
cpu_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
device_set_info_ptr(space->machine->cpu[0],CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA,&ddtdata);
if (endflag)
{
@ -773,7 +773,7 @@ WRITE64_HANDLER( dc_g1_ctrl_w )
ddtdata.channel= -1; // not used
ddtdata.mode= -1; // copy from/to buffer
mame_printf_verbose("G1CTRL: transfer %x from ROM %08x to sdram %08x\n", g1bus_regs[SB_GDLEN], dmaoffset, g1bus_regs[SB_GDSTAR]);
cpu_set_info_ptr(space->machine->cpu[0], CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA, &ddtdata);
device_set_info_ptr(space->machine->cpu[0], CPUINFO_PTR_SH4_EXTERNAL_DDT_DMA, &ddtdata);
g1bus_regs[SB_GDST]=0;
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_GDROM;
}

18
src/mame/machine/n64.c
View File

@ -465,13 +465,13 @@ WRITE32_HANDLER( n64_sp_reg_w )
{
case 0x00/4: // SP_PC_REG
//printf( "Setting PC to: %08x\n", 0x04001000 | (data & 0xfff ) );
if( cpu_get_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_NEXTPC) != 0xffffffff )
if( device_get_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_NEXTPC) != 0xffffffff )
{
cpu_set_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_NEXTPC, 0x04001000 | (data & 0xfff));
device_set_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_NEXTPC, 0x04001000 | (data & 0xfff));
}
else
{
cpu_set_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_PC, 0x04001000 | (data & 0xfff));
device_set_info_int(space->machine->cpu[1], CPUINFO_INT_REGISTER + RSP_PC, 0x04001000 | (data & 0xfff));
}
break;
@ -1628,14 +1628,14 @@ void n64_machine_reset(running_machine *machine)
cic_status = 0;
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS + MIPS3DRC_STRICT_VERIFY);
/* configure fast RAM regions for DRC */
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
cpu_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rdram);
cpu_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_END, 0x007fffff);
device_set_info_ptr(machine->cpu[0], CPUINFO_PTR_MIPS3_FASTRAM_BASE, rdram);
device_set_info_int(machine->cpu[0], CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0);
audio_timer = timer_alloc(machine, audio_timer_callback, NULL);
timer_adjust_oneshot(audio_timer, attotime_never, 0);

2
src/mame/machine/namcos1.c
View File

@ -873,7 +873,7 @@ MACHINE_RESET( namcos1 )
namcos1_bankswitch(machine, 1, 0x0e01, 0xff);
/* reset Cpu 0 and stop all other CPUs */
cpu_reset(machine->cpu[0]);
device_reset(machine->cpu[0]);
cpu_set_input_line(machine->cpu[1], INPUT_LINE_RESET, ASSERT_LINE);
cpu_set_input_line(machine->cpu[2], INPUT_LINE_RESET, ASSERT_LINE);
cpu_set_input_line(machine->cpu[3], INPUT_LINE_RESET, ASSERT_LINE);

6
src/mame/machine/s16fd.c
View File

@ -150,11 +150,11 @@ void fd1094_machine_init(const device_config *device)
fd1094_setstate_and_decrypt(FD1094_STATE_RESET);
fd1094_kludge_reset_values();
cpu_set_info_fct(device, CPUINFO_PTR_M68K_CMPILD_CALLBACK, (genf *)fd1094_cmp_callback);
cpu_set_info_fct(device, CPUINFO_PTR_M68K_RTE_CALLBACK, (genf *)fd1094_rte_callback);
device_set_info_fct(device, CPUINFO_PTR_M68K_CMPILD_CALLBACK, (genf *)fd1094_cmp_callback);
device_set_info_fct(device, CPUINFO_PTR_M68K_RTE_CALLBACK, (genf *)fd1094_rte_callback);
cpu_set_irq_callback(device, fd1094_int_callback);
cpu_reset(device);
device_reset(device);
}
static STATE_POSTLOAD( fd1094_postload )

6
src/mame/machine/s24fd.c
View File

@ -132,11 +132,11 @@ void s24_fd1094_machine_init(void)
s24_fd1094_setstate_and_decrypt(FD1094_STATE_RESET);
s24_fd1094_kludge_reset_values();
cpu_set_info_fct(Machine->cpu[1], CPUINFO_PTR_M68K_CMPILD_CALLBACK, (genf *)s24_fd1094_cmp_callback);
cpu_set_info_fct(Machine->cpu[1], CPUINFO_PTR_M68K_RTE_CALLBACK, (genf *)s24_fd1094_rte_callback);
device_set_info_fct(Machine->cpu[1], CPUINFO_PTR_M68K_CMPILD_CALLBACK, (genf *)s24_fd1094_cmp_callback);
device_set_info_fct(Machine->cpu[1], CPUINFO_PTR_M68K_RTE_CALLBACK, (genf *)s24_fd1094_rte_callback);
cpu_set_irq_callback(Machine->cpu[1], s24_fd1094_int_callback);
cpu_reset(Machine->cpu[1]);
device_reset(Machine->cpu[1]);
}
static STATE_POSTLOAD( s24_fd1094_postload )