mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
notes (nw)
This commit is contained in:
David Haywood
parent
8167704ef0
commit
565b835ee1
@ -60,13 +60,18 @@ M82 - board made for Major Title, Z80 has a rom, no MCU
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M84 - 2 PCB stack
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functionally same as M82 but without the extra sprite hw??
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M84-A-A (bottom board)
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M84-A-A (bottom board) (most games)
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supports
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4 program roms
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8 tile roms
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1 snd prg, 1 voice rom
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CPUs and some customs etc.
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M84-D-B (bottom board) (found on lightning swords / kengo)
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redesigned version of above but
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for V35 CPU? (seems to lack the UPD71059C interrupt
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controller which isn't needed when with the V35)
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M84-C-A (top board) (listed as for Hammering Harry)
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4 sprite roms (in a row)
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6 larger chips with detail removed
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@ -91,6 +96,7 @@ M84 - 2 PCB stack
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M85 - Pound for Pound uses this, possibly just M84 with
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a modified sound section?
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- not Jamma, trackball input only
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Year Board Protected?
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@ -882,7 +888,7 @@ READ16_MEMBER(m72_state::poundfor_trackball_r)
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}
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#define CPU1_MEMORY(NAME,ROMSIZE,WORKRAM) \
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#define M72_CPU1_MEMORY(NAME,ROMSIZE,WORKRAM) \
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static ADDRESS_MAP_START( NAME##_map, AS_PROGRAM, 16 , m72_state ) \
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AM_RANGE(0x00000, ROMSIZE-1) AM_ROM \
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AM_RANGE(WORKRAM, WORKRAM+0x3fff) AM_RAM /* work RAM */ \
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@ -896,50 +902,55 @@ static ADDRESS_MAP_START( NAME##_map, AS_PROGRAM, 16 , m72_state ) \
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ADDRESS_MAP_END
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/* ROMSIZE WORKRAM */
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CPU1_MEMORY( m72, 0x80000, 0xa0000 )
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CPU1_MEMORY( rtype, 0x40000, 0x40000 )
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CPU1_MEMORY( xmultiplm72, 0x80000, 0x80000 )
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CPU1_MEMORY( dbreedm72, 0x80000, 0x90000 )
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/* ROMSIZE WORKRAM */
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M72_CPU1_MEMORY( m72, 0x80000, 0xa0000 )
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M72_CPU1_MEMORY( rtype, 0x40000, 0x40000 )
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M72_CPU1_MEMORY( xmultiplm72, 0x80000, 0x80000 )
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M72_CPU1_MEMORY( dbreedm72, 0x80000, 0x90000 )
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static ADDRESS_MAP_START( xmultipl_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0x9c000, 0x9ffff) AM_RAM /* work RAM */
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xc8000, 0xc8bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xcc000, 0xccbff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0xd8000, 0xdbfff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( dbreed_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0x88000, 0x8bfff) AM_RAM /* work RAM */
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xc8000, 0xc8bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xcc000, 0xccbff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0xd8000, 0xdbfff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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#define M81_CPU1_MEMORY(NAME,WORKRAM) \
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static ADDRESS_MAP_START( NAME##_map, AS_PROGRAM, 16 , m72_state ) \
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AM_RANGE(0x00000, 0x7ffff) AM_ROM \
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AM_RANGE(WORKRAM, WORKRAM+0x3fff) AM_RAM /* work RAM */ \
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */ \
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram") \
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AM_RANGE(0xc8000, 0xc8bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram") \
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AM_RANGE(0xcc000, 0xccbff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2") \
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1") \
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AM_RANGE(0xd8000, 0xdbfff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2") \
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AM_RANGE(0xffff0, 0xfffff) AM_ROM \
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ADDRESS_MAP_END \
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static ADDRESS_MAP_START( rtype2_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0xb0000, 0xb0001) AM_WRITE(irq_line_w)
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AM_RANGE(0xbc000, 0xbc001) AM_WRITE(dmaon_w)
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xc8000, 0xc8bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0xd4000, 0xd7fff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xd8000, 0xd8bff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xe0000, 0xe3fff) AM_RAM /* work RAM */
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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/* WORKRAM */
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M81_CPU1_MEMORY( xmultipl, 0x9c000 )
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M81_CPU1_MEMORY( dbreed, 0x88000 )
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M81_CPU1_MEMORY( hharry, 0xa0000 )
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static ADDRESS_MAP_START( majtitle_map, AS_PROGRAM, 16, m72_state )
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#define M84_CPU1_MEMORY(NAME,VIDEORAM,PALETTERAM1,PALETTERAM2) \
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static ADDRESS_MAP_START( NAME##_map, AS_PROGRAM, 16 , m72_state ) \
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AM_RANGE(0x00000, 0x7ffff) AM_ROM \
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AM_RANGE(0xb0000, 0xb0001) AM_WRITE(irq_line_w) \
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AM_RANGE(0xb4000, 0xb4001) AM_WRITENOP /* ??? */ \
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AM_RANGE(0xbc000, 0xbc001) AM_WRITE(dmaon_w) \
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */ \
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram") \
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AM_RANGE(VIDEORAM+0x0000, VIDEORAM+0x3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1") \
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AM_RANGE(VIDEORAM+0x4000, VIDEORAM+0x7fff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2") \
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AM_RANGE(PALETTERAM1, PALETTERAM1+0xbff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram") \
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AM_RANGE(PALETTERAM2, PALETTERAM2+0xbff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2") \
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AM_RANGE(0xe0000, 0xe3fff) AM_RAM /* work RAM */ \
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AM_RANGE(0xffff0, 0xfffff) AM_ROM \
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ADDRESS_MAP_END \
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M84_CPU1_MEMORY( rtype2, 0xd0000, 0xc8000, 0xd8000 )
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M84_CPU1_MEMORY( hharryu, 0xd0000, 0xa0000, 0xa8000 )
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M84_CPU1_MEMORY( kengo, 0x80000, 0xa0000, 0xa8000 )
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static ADDRESS_MAP_START( m82_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0xa0000, 0xa03ff) AM_RAM AM_SHARE("majtitle_rowscr")
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AM_RANGE(0xa4000, 0xa4bff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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@ -955,46 +966,8 @@ static ADDRESS_MAP_START( majtitle_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( hharry_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0xa0000, 0xa3fff) AM_RAM /* work RAM */
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xc8000, 0xc8bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xcc000, 0xccbff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0xd8000, 0xdbfff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( hharryu_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0xa0000, 0xa0bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xa8000, 0xa8bff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xb0000, 0xb0001) AM_WRITE(irq_line_w)
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AM_RANGE(0xbc000, 0xbc001) AM_WRITE(dmaon_w)
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AM_RANGE(0xb0ffe, 0xb0fff) AM_WRITEONLY /* leftover from protection?? */
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xd0000, 0xd3fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0xd4000, 0xd7fff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xe0000, 0xe3fff) AM_RAM /* work RAM */
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( kengo_map, AS_PROGRAM, 16, m72_state )
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AM_RANGE(0x00000, 0x7ffff) AM_ROM
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AM_RANGE(0xa0000, 0xa0bff) AM_READWRITE(palette1_r, palette1_w) AM_SHARE("paletteram")
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AM_RANGE(0xa8000, 0xa8bff) AM_READWRITE(palette2_r, palette2_w) AM_SHARE("paletteram2")
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AM_RANGE(0xb0000, 0xb0001) AM_WRITE(irq_line_w)
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AM_RANGE(0xb4000, 0xb4001) AM_WRITENOP /* ??? */
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AM_RANGE(0xbc000, 0xbc001) AM_WRITE(dmaon_w)
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AM_RANGE(0xc0000, 0xc03ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0x80000, 0x83fff) AM_RAM_WRITE(videoram1_w) AM_SHARE("videoram1")
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AM_RANGE(0x84000, 0x87fff) AM_RAM_WRITE(videoram2_w) AM_SHARE("videoram2")
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AM_RANGE(0xe0000, 0xe3fff) AM_RAM /* work RAM */
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AM_RANGE(0xffff0, 0xfffff) AM_ROM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( m72_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x00, 0x01) AM_READ_PORT("IN0")
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@ -1012,7 +985,7 @@ static ADDRESS_MAP_START( m72_portmap, AS_IO, 16, m72_state )
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/* { 0xc0, 0xc0 trigger sample, filled by init_ function */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( rtype2_portmap, AS_IO, 16, m72_state )
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static ADDRESS_MAP_START( m84_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x00, 0x01) AM_READ_PORT("IN0")
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AM_RANGE(0x02, 0x03) AM_READ_PORT("IN1")
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AM_RANGE(0x04, 0x05) AM_READ_PORT("DSW")
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@ -1025,6 +998,20 @@ static ADDRESS_MAP_START( rtype2_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x86, 0x87) AM_WRITE(scrollx2_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( m84_v33_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x00, 0x01) AM_READ_PORT("IN0")
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AM_RANGE(0x02, 0x03) AM_READ_PORT("IN1")
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AM_RANGE(0x04, 0x05) AM_READ_PORT("DSW")
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AM_RANGE(0x00, 0x01) AM_DEVWRITE("m72", m72_audio_device, sound_command_w)
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AM_RANGE(0x02, 0x03) AM_WRITE(rtype2_port02_w)
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AM_RANGE(0x80, 0x81) AM_WRITE(scrolly1_w)
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AM_RANGE(0x82, 0x83) AM_WRITE(scrollx1_w)
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AM_RANGE(0x84, 0x85) AM_WRITE(scrolly2_w)
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AM_RANGE(0x86, 0x87) AM_WRITE(scrollx2_w)
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// AM_RANGE(0x8c, 0x8f) AM_WRITENOP /* ??? */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( poundfor_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x02, 0x03) AM_READ_PORT("IN1")
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AM_RANGE(0x04, 0x05) AM_READ_PORT("DSW")
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@ -1070,18 +1057,6 @@ static ADDRESS_MAP_START( m81_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x86, 0x87) AM_WRITE(scrollx2_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( kengo_portmap, AS_IO, 16, m72_state )
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AM_RANGE(0x00, 0x01) AM_READ_PORT("IN0")
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AM_RANGE(0x02, 0x03) AM_READ_PORT("IN1")
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AM_RANGE(0x04, 0x05) AM_READ_PORT("DSW")
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AM_RANGE(0x00, 0x01) AM_DEVWRITE("m72", m72_audio_device, sound_command_w)
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AM_RANGE(0x02, 0x03) AM_WRITE(rtype2_port02_w)
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AM_RANGE(0x80, 0x81) AM_WRITE(scrolly1_w)
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AM_RANGE(0x82, 0x83) AM_WRITE(scrollx1_w)
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AM_RANGE(0x84, 0x85) AM_WRITE(scrolly2_w)
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AM_RANGE(0x86, 0x87) AM_WRITE(scrollx2_w)
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// AM_RANGE(0x8c, 0x8f) AM_WRITENOP /* ??? */
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( sound_ram_map, AS_PROGRAM, 8, m72_state )
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@ -1989,7 +1964,7 @@ static MACHINE_CONFIG_START( rtype2, m72_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", V30,MASTER_CLOCK/2/2) /* 16 MHz external freq (8MHz internal) */
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MCFG_CPU_PROGRAM_MAP(rtype2_map)
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MCFG_CPU_IO_MAP(rtype2_portmap)
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MCFG_CPU_IO_MAP(m84_portmap)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("upd71059c", pic8259_device, inta_cb)
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MCFG_CPU_ADD("soundcpu", Z80, SOUND_CLOCK)
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@ -2032,7 +2007,7 @@ static MACHINE_CONFIG_START( cosmccop, m72_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", V35,MASTER_CLOCK/2)
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MCFG_CPU_PROGRAM_MAP(kengo_map)
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MCFG_CPU_IO_MAP(kengo_portmap)
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MCFG_CPU_IO_MAP(m84_v33_portmap)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("upd71059c", pic8259_device, inta_cb)
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MCFG_CPU_ADD("soundcpu", Z80, SOUND_CLOCK)
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@ -2078,7 +2053,7 @@ static MACHINE_CONFIG_START( m82, m72_state )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", V30,MASTER_CLOCK/2/2) /* 16 MHz external freq (8MHz internal) */
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MCFG_CPU_PROGRAM_MAP(majtitle_map)
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MCFG_CPU_PROGRAM_MAP(m82_map)
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MCFG_CPU_IO_MAP(m82_portmap)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("upd71059c", pic8259_device, inta_cb)
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