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Changed faked divider constant to match bugfix in SCC driver, still need to figure out the actual PCLK
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@ -184,7 +184,8 @@
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#endif
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#define BAUDGEN_CLOCK XTAL_19_6608MHz /* Raltron */
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#define SCC_CLOCK (BAUDGEN_CLOCK / 4) /* Giving 4.9152MHz as documentation says */
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// TODO: figure out the correct divider circuit
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#define SCC_CLOCK (BAUDGEN_CLOCK / 5) /* Giving 9600 but not the 4.9152MHz the documentation says... */
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class hk68v10_state : public driver_device
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{
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public:
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