Changed faked divider constant to match bugfix in SCC driver, still need to figure out the actual PCLK

This commit is contained in:
Joakim Larsson Edstrom 2016-06-02 11:35:32 +02:00
parent ab7faf82a1
commit 5681768bf7

View File

@ -184,7 +184,8 @@
#endif
#define BAUDGEN_CLOCK XTAL_19_6608MHz /* Raltron */
#define SCC_CLOCK (BAUDGEN_CLOCK / 4) /* Giving 4.9152MHz as documentation says */
// TODO: figure out the correct divider circuit
#define SCC_CLOCK (BAUDGEN_CLOCK / 5) /* Giving 9600 but not the 4.9152MHz the documentation says... */
class hk68v10_state : public driver_device
{
public: