mirror of
https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
a310.c/archimds.c: Reduce tagmap lookups (nw)
This commit is contained in:
Wilbert Pol
parent
cb294f862b
commit
56b3f1cd0e
@ -8,6 +8,9 @@
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#define _ARCHIMEDES_H_
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#include "machine/aakart.h"
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#include "sound/dac.h"
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#include "machine/i2cmem.h"
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#include "machine/wd17xx.h"
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// interrupt definitions. these are for the real Archimedes computer - arcade
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// and gambling knockoffs likely are a bit different.
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@ -40,9 +43,14 @@ class archimedes_state : public driver_device
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{
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public:
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archimedes_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_kart(*this, "kart")
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{ }
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: driver_device(mconfig, type, tag)
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, m_kart(*this, "kart")
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, m_maincpu(*this, "maincpu")
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, m_i2cmem(*this, "i2cmem")
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, m_wd1772(*this, "wd1772")
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, m_region_maincpu(*this, "maincpu")
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, m_region_vram(*this, "vram")
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{ }
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optional_device<aakart_device> m_kart;
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void archimedes_init();
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@ -78,6 +86,15 @@ public:
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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protected:
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required_device<cpu_device> m_maincpu;
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optional_device<device_t> m_i2cmem;
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optional_device<device_t> m_wd1772;
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required_memory_region m_region_maincpu;
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required_memory_region m_region_vram;
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dac_device *m_dac[8];
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private:
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static const device_timer_id TIMER_VBLANK = 0;
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@ -28,11 +28,8 @@
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#include "emu.h"
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#include "cpu/arm/arm.h"
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#include "sound/dac.h"
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#include "includes/archimds.h"
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#include "machine/i2cmem.h"
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#include "debugger.h"
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#include "machine/wd17xx.h"
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static const int page_sizes[4] = { 4096, 8192, 16384, 32768 };
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static const UINT32 pixel_rate[4] = { 8000000, 12000000, 16000000, 24000000};
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@ -45,11 +42,14 @@ void archimedes_state::archimedes_request_irq_a(int mask)
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m_ioc_regs[IRQ_STATUS_A] |= mask;
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if (m_ioc_regs[IRQ_STATUS_A] & m_ioc_regs[IRQ_MASK_A])
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machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, ASSERT_LINE);
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{
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m_maincpu->set_input_line(ARM_IRQ_LINE, ASSERT_LINE);
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}
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if ((m_ioc_regs[IRQ_STATUS_A] & m_ioc_regs[IRQ_MASK_A]) == 0)
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machine().device("maincpu")->execute().set_input_line(ARM_IRQ_LINE, CLEAR_LINE);
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{
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m_maincpu->set_input_line(ARM_IRQ_LINE, CLEAR_LINE);
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}
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}
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void archimedes_state::archimedes_request_irq_b(int mask)
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@ -58,7 +58,7 @@ void archimedes_state::archimedes_request_irq_b(int mask)
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if (m_ioc_regs[IRQ_STATUS_B] & m_ioc_regs[IRQ_MASK_B])
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{
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generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_IRQ_LINE, 1);
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generic_pulse_irq_line(m_maincpu, ARM_IRQ_LINE, 1);
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}
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}
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@ -68,7 +68,7 @@ void archimedes_state::archimedes_request_fiq(int mask)
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if (m_ioc_regs[FIQ_STATUS] & m_ioc_regs[FIQ_MASK])
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{
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generic_pulse_irq_line(machine().device("maincpu")->execute(), ARM_FIRQ_LINE, 1);
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generic_pulse_irq_line(m_maincpu, ARM_FIRQ_LINE, 1);
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}
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}
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@ -113,8 +113,8 @@ void archimedes_state::vidc_vblank()
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/* TODO: what type of DMA this is, burst or cycle steal? Docs doesn't explain it (4 usec is the DRAM refresh). */
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void archimedes_state::vidc_video_tick()
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{
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address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
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static UINT8 *vram = machine().root_device().memregion("vram")->base();
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address_space &space = m_maincpu->space(AS_PROGRAM);
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static UINT8 *vram = m_region_vram->base();
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UINT32 size;
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size = m_vidc_vidend-m_vidc_vidstart+0x10;
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@ -131,11 +131,10 @@ void archimedes_state::vidc_video_tick()
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/* audio DMA */
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void archimedes_state::vidc_audio_tick()
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{
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address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
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address_space &space = m_maincpu->space(AS_PROGRAM);
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UINT8 ulaw_comp;
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INT16 res;
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UINT8 ch;
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static const char *const dac_port[8] = { "dac0", "dac1", "dac2", "dac3", "dac4", "dac5", "dac6", "dac7" };
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static const INT16 mulawTable[256] =
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{
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-32124,-31100,-30076,-29052,-28028,-27004,-25980,-24956,
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@ -180,7 +179,7 @@ void archimedes_state::vidc_audio_tick()
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res = mulawTable[ulaw_comp];
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machine().device<dac_device>(dac_port[ch & 7])->write_signed16(res^0x8000);
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m_dac[ch & 7]->write_signed16(res^0x8000);
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}
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m_vidc_sndcur+=8;
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@ -194,7 +193,9 @@ void archimedes_state::vidc_audio_tick()
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{
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m_snd_timer->adjust(attotime::never);
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for(ch=0;ch<8;ch++)
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machine().device<dac_device>(dac_port[ch & 7])->write_signed16(0x8000);
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{
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m_dac[ch & 7]->write_signed16(0x8000);
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}
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}
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}
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}
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@ -259,6 +260,8 @@ void archimedes_state::archimedes_reset()
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void archimedes_state::archimedes_init()
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{
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static const char *const dac_names[8] = { "dac0", "dac1", "dac2", "dac3", "dac4", "dac5", "dac6", "dac7" };
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m_memc_pagesize = 0;
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m_vbl_timer = timer_alloc(TIMER_VBLANK);
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@ -276,6 +279,11 @@ void archimedes_state::archimedes_init()
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m_vid_timer = timer_alloc(TIMER_VIDEO);
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m_snd_timer = timer_alloc(TIMER_AUDIO);
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m_snd_timer->adjust(attotime::never);
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for ( int i = 0; i < 8; i++ )
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{
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m_dac[i] = machine().device<dac_device>(dac_names[i]);
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}
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}
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READ32_MEMBER(archimedes_state::archimedes_memc_logical_r)
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@ -287,7 +295,7 @@ READ32_MEMBER(archimedes_state::archimedes_memc_logical_r)
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{
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UINT32 *rom;
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rom = (UINT32 *)machine().root_device().memregion("maincpu")->base();
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rom = (UINT32 *)m_region_maincpu->base();
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return rom[offset & 0x1fffff];
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}
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@ -353,7 +361,7 @@ READ32_MEMBER(archimedes_state::aristmk5_drame_memc_logical_r)
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{
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UINT32 *rom;
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rom = (UINT32 *)machine().root_device().memregion("maincpu")->base();
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rom = (UINT32 *)m_region_maincpu->base();
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return rom[offset & 0x1fffff];
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}
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@ -394,8 +402,8 @@ READ32_MEMBER(archimedes_state::aristmk5_drame_memc_logical_r)
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void archimedes_state::archimedes_driver_init()
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{
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m_archimedes_memc_physmem = reinterpret_cast<UINT32 *>(machine().root_device().memshare("physicalram")->ptr());
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// address_space &space = machine.device<arm_device>("maincpu")->space(AS_PROGRAM);
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m_archimedes_memc_physmem = reinterpret_cast<UINT32 *>(memshare("physicalram")->ptr());
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// address_space &space = m_maincpu->space(AS_PROGRAM);
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// space.set_direct_update_handler(direct_update_delegate(FUNC(a310_setopbase), &machine));
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}
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@ -446,20 +454,23 @@ void archimedes_state::latch_timer_cnt(int tmr)
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READ32_MEMBER( archimedes_state::ioc_ctrl_r )
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{
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if(IOC_LOG)
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logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], m_ioc_regs[offset&0x1f], space.device() .safe_pc( ),offset & 0x1f);
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logerror("IOC: R %s = %02x (PC=%x) %02x\n", ioc_regnames[offset&0x1f], m_ioc_regs[offset&0x1f], m_maincpu->pc(),offset & 0x1f);
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switch (offset & 0x1f)
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{
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case CONTROL:
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{
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UINT8 i2c_data;
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UINT8 i2c_data = 1;
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static UINT8 flyback; //internal name for vblank here
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int vert_pos;
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vert_pos = machine().primary_screen->vpos();
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flyback = (vert_pos <= m_vidc_regs[VIDC_VDSR] || vert_pos >= m_vidc_regs[VIDC_VDER]) ? 0x80 : 0x00;
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i2c_data = (i2cmem_sda_read(space.machine().device("i2cmem")) & 1);
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if ( m_i2cmem )
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{
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i2c_data = (i2cmem_sda_read(m_i2cmem) & 1);
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}
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return (flyback) | (m_ioc_regs[CONTROL] & 0x7c) | (m_i2c_clk<<1) | i2c_data;
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}
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@ -524,8 +535,11 @@ WRITE32_MEMBER( archimedes_state::ioc_ctrl_w )
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{
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case CONTROL: // I2C bus control
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//logerror("IOC I2C: CLK %d DAT %d\n", (data>>1)&1, data&1);
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i2cmem_sda_write(machine().device("i2cmem"), data & 0x01);
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i2cmem_scl_write(machine().device("i2cmem"), (data & 0x02) >> 1);
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if ( m_i2cmem )
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{
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i2cmem_sda_write(m_i2cmem, data & 0x01);
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i2cmem_scl_write(m_i2cmem, (data & 0x02) >> 1);
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}
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m_i2c_clk = (data & 2) >> 1;
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break;
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@ -632,7 +646,6 @@ WRITE32_MEMBER( archimedes_state::ioc_ctrl_w )
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READ32_MEMBER(archimedes_state::archimedes_ioc_r)
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{
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UINT32 ioc_addr;
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device_t *fdc = (device_t *)space.machine().device("wd1772");
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ioc_addr = offset*4;
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@ -649,9 +662,9 @@ READ32_MEMBER(archimedes_state::archimedes_ioc_r)
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{
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case 0: return ioc_ctrl_r(space,offset,mem_mask);
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case 1:
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if (fdc) {
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if (m_wd1772) {
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logerror("17XX: R @ addr %x mask %08x\n", offset*4, mem_mask);
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return wd17xx_data_r(fdc, space, offset&0xf);
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return wd17xx_data_r(m_wd1772, space, offset&0xf);
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} else {
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logerror("Read from FDC device?\n");
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return 0;
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@ -666,7 +679,7 @@ READ32_MEMBER(archimedes_state::archimedes_ioc_r)
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logerror("IOC: Internal Podule Read\n");
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return 0xffff;
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case 5:
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if (fdc) {
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if (m_wd1772) {
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switch(ioc_addr & 0xfffc)
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{
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case 0x50: return 0; //fdc type, new model returns 5 here
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@ -688,7 +701,6 @@ READ32_MEMBER(archimedes_state::archimedes_ioc_r)
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WRITE32_MEMBER(archimedes_state::archimedes_ioc_w)
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{
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UINT32 ioc_addr;
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device_t *fdc = (device_t *)space.machine().device("wd1772");
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ioc_addr = offset*4;
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@ -705,9 +717,9 @@ WRITE32_MEMBER(archimedes_state::archimedes_ioc_w)
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{
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case 0: ioc_ctrl_w(space,offset,data,mem_mask); return;
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case 1:
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if (fdc) {
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if (m_wd1772) {
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logerror("17XX: %x to addr %x mask %08x\n", data, offset*4, mem_mask);
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wd17xx_data_w(fdc, space, offset&0xf, data&0xff);
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wd17xx_data_w(m_wd1772, space, offset&0xf, data&0xff);
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} else {
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logerror("Write to FDC device?\n");
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}
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@ -722,20 +734,20 @@ WRITE32_MEMBER(archimedes_state::archimedes_ioc_w)
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logerror("IOC: Internal Podule Write\n");
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return;
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case 5:
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if (fdc) {
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if (m_wd1772) {
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switch(ioc_addr & 0xfffc)
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{
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case 0x18: // latch B
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wd17xx_dden_w(fdc, BIT(data, 1));
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wd17xx_dden_w(m_wd1772, BIT(data, 1));
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return;
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case 0x40: // latch A
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if (data & 1) { wd17xx_set_drive(fdc,0); }
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if (data & 2) { wd17xx_set_drive(fdc,1); }
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if (data & 4) { wd17xx_set_drive(fdc,2); }
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if (data & 8) { wd17xx_set_drive(fdc,3); }
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if (data & 1) { wd17xx_set_drive(m_wd1772,0); }
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if (data & 2) { wd17xx_set_drive(m_wd1772,1); }
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if (data & 4) { wd17xx_set_drive(m_wd1772,2); }
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if (data & 8) { wd17xx_set_drive(m_wd1772,3); }
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wd17xx_set_side(fdc,(data & 0x10)>>4);
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wd17xx_set_side(m_wd1772,(data & 0x10)>>4);
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//bit 5 is motor on
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return;
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}
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@ -70,8 +70,10 @@ class a310_state : public archimedes_state
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{
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public:
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a310_state(const machine_config &mconfig, device_type type, const char *tag)
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: archimedes_state(mconfig, type, tag),
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m_physram(*this, "physicalram") { }
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: archimedes_state(mconfig, type, tag)
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, m_physram(*this, "physicalram")
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, m_ram(*this, RAM_TAG)
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{ }
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required_shared_ptr<UINT32> m_physram;
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@ -82,6 +84,9 @@ public:
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DECLARE_DRIVER_INIT(a310);
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virtual void machine_start();
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virtual void machine_reset();
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protected:
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required_device<ram_device> m_ram;
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};
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@ -114,9 +119,9 @@ WRITE32_MEMBER(a310_state::a310_psy_wram_w)
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DRIVER_INIT_MEMBER(a310_state,a310)
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{
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UINT32 ram_size = machine().device<ram_device>(RAM_TAG)->size();
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UINT32 ram_size = m_ram->size();
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machine().device("maincpu")->memory().space(AS_PROGRAM).install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), this), write32_delegate(FUNC(a310_state::a310_psy_wram_w), this));
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m_maincpu->space(AS_PROGRAM).install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), this), write32_delegate(FUNC(a310_state::a310_psy_wram_w), this));
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archimedes_driver_init();
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}
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