nscsi: Add dump and skeleton device for Sony CDU561-25 CD-ROM drive [Bitsavers]

scripts/src/bus.lua

@@ -2507,6 +2507,8 @@ if (BUSES["NSCSI"]~=null) then
 		MAME_DIR .. "src/devices/bus/nscsi/cdu75s.h",
 		MAME_DIR .. "src/devices/bus/nscsi/cdu415.cpp",
 		MAME_DIR .. "src/devices/bus/nscsi/cdu415.h",
+		MAME_DIR .. "src/devices/bus/nscsi/cdu561.cpp",
+		MAME_DIR .. "src/devices/bus/nscsi/cdu561.h",
 		MAME_DIR .. "src/devices/bus/nscsi/cw7501.cpp",
 		MAME_DIR .. "src/devices/bus/nscsi/cw7501.h",
 		MAME_DIR .. "src/devices/bus/nscsi/devices.cpp",

src/devices/bus/nscsi/cdu561.cpp

@@ -0,0 +1,84 @@
+// license:BSD-3-Clause
+// copyright-holders:AJR
+/*******************************************************************************
+
+    Skeleton device for Sony CDU561-52 CD-ROM drive.
+
+    PCB: MAIN 1-644-812-13
+
+    Microcontroller:
+    - Mitsubishi M37732S4AFP
+
+    Memories:
+    - TI TMS27C010A-12 EPROM or equivalent
+    - Mosel MS62256CLL-10FC or Sony CXK58257AM-10L 32,768x8 Static RAM
+    - Mosel MS514256A-70VC 262,144x4 Fast Page Mode DRAM (x2; near CXD1198)
+    - Fujitsu MB81C79A-45 or Sony CXK5971AM-35 8,192x9 Static RAM (near CXD1186)
+
+    Other major digital ICs:
+    - Sony CXD1185CQ SCSI Controller
+    - Sony CXD1186Q CD-ROM Decoder
+    - Sony CXD1198AQ CD-ROM Subcode Decoder
+    - Sony CXD2500BQ CD Digital Signal Processor
+    - Sony CXD2568M
+    - Sony CXD8416Q
+
+    Linear ICs:
+    - Sony CXA1372AQ RF Signal Processing Servo Amplifier for CD Player
+    - Sony CXA1571M RF Amplifier for CD Player
+    - Toshiba TA8406P Dual Power Operational Amplifier (x3)
+
+    XTALs:
+    - D169 (near CXD2500B)
+    - 24.00MX (near CXD1198)
+
+*******************************************************************************/
+
+#include "emu.h"
+#include "cdu561.h"
+
+#include "cpu/m37710/m37710.h"
+#include "machine/cxd1185.h"
+
+DEFINE_DEVICE_TYPE(CDU561_25, cdu561_25_device, "cdu561_25", "Sony CDU561-25")
+
+cdu561_25_device::cdu561_25_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+	: device_t(mconfig, CDU561_25, tag, owner, clock)
+	, nscsi_slot_card_interface(mconfig, *this, "scsic")
+{
+}
+
+void cdu561_25_device::device_start()
+{
+}
+
+void cdu561_25_device::mem_map(address_map &map)
+{
+	map(0x000880, 0x007fff).ram();
+	map(0x008000, 0x01ffff).rom().region("eprom", 0x8000);
+	map(0x020000, 0x02ffff).rom().region("eprom", 0);
+	map(0x030000, 0x03000f).noprw(); // CXD1186?
+	map(0x050000, 0x05000f).m("scsic", FUNC(cxd1185_device::map));
+	map(0x070000, 0x070001).nopr(); // ?
+}
+
+void cdu561_25_device::device_add_mconfig(machine_config &config)
+{
+	m37732s4_device &mcu(M37732S4(config, "mcu", 24_MHz_XTAL / 2));
+	mcu.set_addrmap(AS_PROGRAM, &cdu561_25_device::mem_map);
+
+	CXD1185(config, "scsic", 24_MHz_XTAL / 2);
+}
+
+ROM_START(cdu561_25)
+	ROM_REGION16_LE(0x20000, "eprom", 0)
+	ROM_SYSTEM_BIOS(0, "19a", "apl1.9a")
+	ROMX_LOAD("apl1.9a_83fb.ic302", 0x00000, 0x20000, CRC(0efc50eb) SHA1(8bfd6ebc0863017914808e8282a5914cdc828f56), ROM_BIOS(0))
+	ROM_SYSTEM_BIOS(1, "18f", "apl1.8F")
+	ROMX_LOAD("apl1.8f_d905.ic302", 0x00000, 0x20000, CRC(3ea92e48) SHA1(2f409fd59c5f09d22e00b39f4b0b57e16316090d), ROM_BIOS(1))
+ROM_END
+
+const tiny_rom_entry *cdu561_25_device::device_rom_region() const
+{
+	return ROM_NAME(cdu561_25);
+}

src/devices/bus/nscsi/cdu561.h

@@ -0,0 +1,29 @@
+// license:BSD-3-Clause
+// copyright-holders:AJR
+
+#ifndef MAME_BUS_NSCSI_CDU561_H
+#define MAME_BUS_NSCSI_CDU561_H
+
+#pragma once
+
+#include "machine/nscsi_bus.h"
+
+class cdu561_25_device : public device_t, public nscsi_slot_card_interface
+{
+public:
+	cdu561_25_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	static constexpr feature_type unemulated_features() { return feature::DISK; }
+
+protected:
+	virtual void device_start() override;
+	virtual void device_add_mconfig(machine_config &config) override;
+	virtual const tiny_rom_entry *device_rom_region() const override;
+
+private:
+	void mem_map(address_map &map);
+};
+
+DECLARE_DEVICE_TYPE(CDU561_25, cdu561_25_device)
+
+#endif // MAME_BUS_NSCSI_CDU561_25_H

src/devices/bus/nscsi/devices.cpp

@@ -9,6 +9,7 @@
 #include "bus/nscsi/cdrn820s.h"
 #include "bus/nscsi/cdu75s.h"
 #include "bus/nscsi/cdu415.h"
+#include "bus/nscsi/cdu561.h"
 #include "bus/nscsi/cw7501.h"
 #include "bus/nscsi/hd.h"
 #include "bus/nscsi/s1410.h"
@@ -25,6 +26,7 @@ void default_scsi_devices(device_slot_interface &device)
 	device.option_add("cdd2000", CDD2000);
 	device.option_add("cdu75s", CDU75S);
 	device.option_add("cdu415", CDU415);
+	device.option_add("cdu561_25", CDU561_25);
 	device.option_add("smoc501", SMOC501);
 	device.option_add("aplcd150", APPLECD150);
 };

src/devices/cpu/m37710/m37710.cpp

@@ -83,6 +83,7 @@ DEFINE_DEVICE_TYPE(M37702S1, m37702s1_device, "m37702s1", "Mitsubishi M37702S1")
 DEFINE_DEVICE_TYPE(M37710S4, m37710s4_device, "m37710s4", "Mitsubishi M37710S4")
 DEFINE_DEVICE_TYPE(M37720S1, m37720s1_device, "m37720s1", "Mitsubishi M37720S1")
 DEFINE_DEVICE_TYPE(M37730S2, m37730s2_device, "m37730s2", "Mitsubishi M37730S2")
+DEFINE_DEVICE_TYPE(M37732S4, m37732s4_device, "m37732s4", "Mitsubishi M37732S4")
 
 
 // On-board RAM, ROM, and peripherals
@@ -311,6 +312,26 @@ void m37730s2_device::map(address_map &map)
 	map(0x000080, 0x00047f).ram();
 }
 
+// M37732S4: 2048 bytes internal RAM, no internal ROM
+void m37732s4_device::map(address_map &map)
+{
+	map(0x000000, 0x000001).noprw();
+	map(0x00000a, 0x00007f).noprw();
+	map(0x00000a, 0x000015).rw(FUNC(m37732s4_device::port_r<4>), FUNC(m37732s4_device::port_w<4>)).umask16(0x00ff);
+	map(0x00000a, 0x00000d).rw(FUNC(m37732s4_device::port_r<5>), FUNC(m37732s4_device::port_w<5>)).umask16(0xff00);
+	map(0x00005e, 0x00005e).rw(FUNC(m37732s4_device::proc_mode_r), FUNC(m37732s4_device::proc_mode_w));
+	map(0x000060, 0x000060).w(FUNC(m37732s4_device::watchdog_timer_w));
+	map(0x000061, 0x000061).rw(FUNC(m37732s4_device::watchdog_freq_r), FUNC(m37732s4_device::watchdog_freq_w));
+	map(0x000062, 0x000062).rw(FUNC(m37732s4_device::waveform_mode_r), FUNC(m37732s4_device::waveform_mode_w));
+	map(0x000064, 0x000065).w(FUNC(m37732s4_device::pulse_output_w));
+	ad_register_map(map);
+	uart0_register_map(map);
+	uart1_register_map(map);
+	timer_register_map(map);
+	irq_register_map(map);
+	map(0x000080, 0x00087f).ram();
+}
+
 // many other combinations of RAM and ROM size exist
 
 
@@ -357,6 +378,11 @@ m37730s2_device::m37730s2_device(const machine_config &mconfig, const char *tag,
 {
 }
 
+m37732s4_device::m37732s4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: m37710_cpu_device(mconfig, M37732S4, tag, owner, clock, address_map_constructor(FUNC(m37732s4_device::map), this))
+{
+}
+
 std::vector<std::pair<int, const address_space_config *>> m37710_cpu_device::memory_space_config() const
 {
 	return std::vector<std::pair<int, const address_space_config *>> {

src/devices/cpu/m37710/m37710.h

@@ -2186,11 +2186,21 @@ protected:
 	void map(address_map &map);
 };
 
+class m37732s4_device : public m37710_cpu_device
+{
+public:
+	// construction/destruction
+	m37732s4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+protected:
+	void map(address_map &map);
+};
+
 DECLARE_DEVICE_TYPE(M37702M2, m37702m2_device)
 DECLARE_DEVICE_TYPE(M37702S1, m37702s1_device)
 DECLARE_DEVICE_TYPE(M37710S4, m37710s4_device)
 DECLARE_DEVICE_TYPE(M37720S1, m37720s1_device)
 DECLARE_DEVICE_TYPE(M37730S2, m37730s2_device)
+DECLARE_DEVICE_TYPE(M37732S4, m37732s4_device)
 
 
 /* ======================================================================== */