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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
Changed 'std::ostream *' in disassemble_t to be 'std::ostream &'
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c5c68788fa
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@ -189,57 +189,57 @@ static void i960_disassemble(disassemble_t *diss)
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switch(mnemonic[op].type)
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{
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case 0: // not yet implemented
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util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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case 1: // memory access
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switch(modeh)
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{
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case 0:
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util::stream_format(*diss->stream, "%-8s%s,0x%lx",NEM,REG_DST, iCode&0xfff);
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util::stream_format(diss->stream, "%-8s%s,0x%lx",NEM,REG_DST, iCode&0xfff);
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break;
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case 1:
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switch (model)
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{
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case 0:
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util::stream_format(*diss->stream, "%-8s%s,(%s)",NEM,REG_DST, REG_ABASE);
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util::stream_format(diss->stream, "%-8s%s,(%s)",NEM,REG_DST, REG_ABASE);
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break;
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case 3:
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util::stream_format(*diss->stream, "%-8s%s,(%s)[%s*%ld]",NEM,REG_DST, REG_ABASE,REG_REG2,(iCode>>7)&0x7);
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util::stream_format(diss->stream, "%-8s%s,(%s)[%s*%ld]",NEM,REG_DST, REG_ABASE,REG_REG2,(iCode>>7)&0x7);
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break;
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default:
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util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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}
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break;
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case 2:
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util::stream_format(*diss->stream, "%-8s%s,0x%lx(%s)",NEM,REG_DST, iCode&0xfff,REG_ABASE);
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util::stream_format(diss->stream, "%-8s%s,0x%lx(%s)",NEM,REG_DST, iCode&0xfff,REG_ABASE);
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break;
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case 3:
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switch (model)
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{
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case 0:
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util::stream_format(*diss->stream, "%-8s%s,0x%x",NEM,REG_DST, READ32(diss,4));
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util::stream_format(diss->stream, "%-8s%s,0x%x",NEM,REG_DST, READ32(diss,4));
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diss->IPinc = 8;
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break;
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case 1:
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util::stream_format(*diss->stream, "%-8s%s,0x%x(%s)",NEM,REG_DST, READ32(diss,4),REG_ABASE);
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util::stream_format(diss->stream, "%-8s%s,0x%x(%s)",NEM,REG_DST, READ32(diss,4),REG_ABASE);
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diss->IPinc = 8;
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break;
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case 2:
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util::stream_format(*diss->stream, "%-8s%s,0x%x[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_REG2,(iCode>>7)&0x7);
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util::stream_format(diss->stream, "%-8s%s,0x%x[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_REG2,(iCode>>7)&0x7);
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diss->IPinc = 8;
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break;
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case 3:
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util::stream_format(*diss->stream, "%-8s%s,0x%x(%s)[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_ABASE,REG_REG2,(iCode>>7)&0x7);
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util::stream_format(diss->stream, "%-8s%s,0x%x(%s)[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_ABASE,REG_REG2,(iCode>>7)&0x7);
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diss->IPinc = 8;
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break;
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default:
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util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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}
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break;
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default:
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util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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}
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break;
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@ -253,8 +253,8 @@ static void i960_disassemble(disassemble_t *diss)
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i++;
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}
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if (mnem_reg[i].type == opc) util::stream_format(*diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,1));
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else util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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if (mnem_reg[i].type == opc) util::stream_format(diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,1));
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else util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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case 3:
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i = 0;
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@ -266,27 +266,27 @@ static void i960_disassemble(disassemble_t *diss)
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i++;
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}
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if (mnem_reg[i].type == opc) util::stream_format(*diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,0));
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else util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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if (mnem_reg[i].type == opc) util::stream_format(diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,0));
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else util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
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break;
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case 6: // bitpos and branch type
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util::stream_format(*diss->stream, "%-8s%ld,%s,0x%lx",NEM, COBRSRC1, REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
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util::stream_format(diss->stream, "%-8s%ld,%s,0x%lx",NEM, COBRSRC1, REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
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break;
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case 7: // compare and branch type
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util::stream_format(*diss->stream, "%-8s%s,%s,0x%lx",NEM,REG_COBR_SRC1,REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
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util::stream_format(diss->stream, "%-8s%s,%s,0x%lx",NEM,REG_COBR_SRC1,REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
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break;
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case 8: // target type
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util::stream_format(*diss->stream, "%-8s%08lx",NEM,((((long)iCode&0x00fffffc)<<8)>>8) + (diss->IP));
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util::stream_format(diss->stream, "%-8s%08lx",NEM,((((long)iCode&0x00fffffc)<<8)>>8) + (diss->IP));
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break;
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case 9: // no operands
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util::stream_format(*diss->stream, "%s",NEM);
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util::stream_format(diss->stream, "%s",NEM);
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break;
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case 10: // TEST type: register only
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util::stream_format(*diss->stream, "%s %s", NEM, REG_DST);
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util::stream_format(diss->stream, "%s %s", NEM, REG_DST);
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break;
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default:
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*diss->stream << "???";
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diss->stream << "???";
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break;
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}
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}
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@ -295,11 +295,7 @@ static void i960_disassemble(disassemble_t *diss)
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static offs_t internal_disasm_i960(cpu_device *device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options)
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{
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disassemble_t dis;
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dis.IP = pc;
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dis.stream = &stream;
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dis.oprom = oprom;
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disassemble_t dis(stream, pc, oprom);
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i960_disassemble(&dis);
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@ -5,7 +5,10 @@
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struct disassemble_t
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{
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std::ostream *stream; // output stream
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disassemble_t(std::ostream &s, unsigned long ip, const uint8_t *opr)
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: stream(s), IP(ip), oprom(opr) { }
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std::ostream &stream; // output stream
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unsigned long IP;
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unsigned long IPinc;
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const uint8_t *oprom;
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