Changed 'std::ostream *' in disassemble_t to be 'std::ostream &'

This commit is contained in:
Nathan Woods 2016-11-16 06:51:51 -05:00
parent c5c68788fa
commit 57000fa11a
2 changed files with 27 additions and 28 deletions

View File

@ -189,57 +189,57 @@ static void i960_disassemble(disassemble_t *diss)
switch(mnemonic[op].type)
{
case 0: // not yet implemented
util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
case 1: // memory access
switch(modeh)
{
case 0:
util::stream_format(*diss->stream, "%-8s%s,0x%lx",NEM,REG_DST, iCode&0xfff);
util::stream_format(diss->stream, "%-8s%s,0x%lx",NEM,REG_DST, iCode&0xfff);
break;
case 1:
switch (model)
{
case 0:
util::stream_format(*diss->stream, "%-8s%s,(%s)",NEM,REG_DST, REG_ABASE);
util::stream_format(diss->stream, "%-8s%s,(%s)",NEM,REG_DST, REG_ABASE);
break;
case 3:
util::stream_format(*diss->stream, "%-8s%s,(%s)[%s*%ld]",NEM,REG_DST, REG_ABASE,REG_REG2,(iCode>>7)&0x7);
util::stream_format(diss->stream, "%-8s%s,(%s)[%s*%ld]",NEM,REG_DST, REG_ABASE,REG_REG2,(iCode>>7)&0x7);
break;
default:
util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
}
break;
case 2:
util::stream_format(*diss->stream, "%-8s%s,0x%lx(%s)",NEM,REG_DST, iCode&0xfff,REG_ABASE);
util::stream_format(diss->stream, "%-8s%s,0x%lx(%s)",NEM,REG_DST, iCode&0xfff,REG_ABASE);
break;
case 3:
switch (model)
{
case 0:
util::stream_format(*diss->stream, "%-8s%s,0x%x",NEM,REG_DST, READ32(diss,4));
util::stream_format(diss->stream, "%-8s%s,0x%x",NEM,REG_DST, READ32(diss,4));
diss->IPinc = 8;
break;
case 1:
util::stream_format(*diss->stream, "%-8s%s,0x%x(%s)",NEM,REG_DST, READ32(diss,4),REG_ABASE);
util::stream_format(diss->stream, "%-8s%s,0x%x(%s)",NEM,REG_DST, READ32(diss,4),REG_ABASE);
diss->IPinc = 8;
break;
case 2:
util::stream_format(*diss->stream, "%-8s%s,0x%x[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_REG2,(iCode>>7)&0x7);
util::stream_format(diss->stream, "%-8s%s,0x%x[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_REG2,(iCode>>7)&0x7);
diss->IPinc = 8;
break;
case 3:
util::stream_format(*diss->stream, "%-8s%s,0x%x(%s)[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_ABASE,REG_REG2,(iCode>>7)&0x7);
util::stream_format(diss->stream, "%-8s%s,0x%x(%s)[%s*%ld]",NEM,REG_DST, READ32(diss,4),REG_ABASE,REG_REG2,(iCode>>7)&0x7);
diss->IPinc = 8;
break;
default:
util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
}
break;
default:
util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
}
break;
@ -253,8 +253,8 @@ static void i960_disassemble(disassemble_t *diss)
i++;
}
if (mnem_reg[i].type == opc) util::stream_format(*diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,1));
else util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
if (mnem_reg[i].type == opc) util::stream_format(diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,1));
else util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
case 3:
i = 0;
@ -266,27 +266,27 @@ static void i960_disassemble(disassemble_t *diss)
i++;
}
if (mnem_reg[i].type == opc) util::stream_format(*diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,0));
else util::stream_format(*diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
if (mnem_reg[i].type == opc) util::stream_format(diss->stream, "%-8s%s", mnem_reg[i].mnem,dis_decode_reg(iCode,tmpStr,0));
else util::stream_format(diss->stream, "%s %02x:%01x %08lx %1x %1x",mnemonic[op].mnem,op,op2,iCode, modeh, model);
break;
case 6: // bitpos and branch type
util::stream_format(*diss->stream, "%-8s%ld,%s,0x%lx",NEM, COBRSRC1, REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
util::stream_format(diss->stream, "%-8s%ld,%s,0x%lx",NEM, COBRSRC1, REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
break;
case 7: // compare and branch type
util::stream_format(*diss->stream, "%-8s%s,%s,0x%lx",NEM,REG_COBR_SRC1,REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
util::stream_format(diss->stream, "%-8s%s,%s,0x%lx",NEM,REG_COBR_SRC1,REG_COBR_SRC2,((((long)iCode&0x00fffffc)<<19)>>19) + (diss->IP));
break;
case 8: // target type
util::stream_format(*diss->stream, "%-8s%08lx",NEM,((((long)iCode&0x00fffffc)<<8)>>8) + (diss->IP));
util::stream_format(diss->stream, "%-8s%08lx",NEM,((((long)iCode&0x00fffffc)<<8)>>8) + (diss->IP));
break;
case 9: // no operands
util::stream_format(*diss->stream, "%s",NEM);
util::stream_format(diss->stream, "%s",NEM);
break;
case 10: // TEST type: register only
util::stream_format(*diss->stream, "%s %s", NEM, REG_DST);
util::stream_format(diss->stream, "%s %s", NEM, REG_DST);
break;
default:
*diss->stream << "???";
diss->stream << "???";
break;
}
}
@ -295,11 +295,7 @@ static void i960_disassemble(disassemble_t *diss)
static offs_t internal_disasm_i960(cpu_device *device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options)
{
disassemble_t dis;
dis.IP = pc;
dis.stream = &stream;
dis.oprom = oprom;
disassemble_t dis(stream, pc, oprom);
i960_disassemble(&dis);

View File

@ -5,7 +5,10 @@
struct disassemble_t
{
std::ostream *stream; // output stream
disassemble_t(std::ostream &s, unsigned long ip, const uint8_t *opr)
: stream(s), IP(ip), oprom(opr) { }
std::ostream &stream; // output stream
unsigned long IP;
unsigned long IPinc;
const uint8_t *oprom;