diff --git a/src/lib/netlist/devices/nld_4006.cpp b/src/lib/netlist/devices/nld_4006.cpp
index 24d7f4bb9a9..9e7602560e9 100644
--- a/src/lib/netlist/devices/nld_4006.cpp
+++ b/src/lib/netlist/devices/nld_4006.cpp
@@ -15,7 +15,6 @@ namespace netlist
 	NETLIB_OBJECT(CD4006)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4006, "CD4XXX")
-		//NETLIB_FAMILY("CD4XXX")
 		, m_CLOCK(*this, "CLOCK")
 		, m_I(*this, {"D1", "D2", "D3", "D4"})
 		, m_Q(*this, {"D1P4", "D1P4S", "D2P4", "D2P5", "D3P4", "D4P4", "D3P5"})
diff --git a/src/lib/netlist/devices/nld_4020.cpp b/src/lib/netlist/devices/nld_4020.cpp
index 0a5d72aae56..59eebd209ce 100644
--- a/src/lib/netlist/devices/nld_4020.cpp
+++ b/src/lib/netlist/devices/nld_4020.cpp
@@ -16,7 +16,6 @@ namespace netlist
 	NETLIB_OBJECT(CD4020_sub)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4020_sub, "CD4XXX")
-		//NETLIB_FAMILY()
 		, m_IP(*this, "IP")
 		, m_Q(*this, {"Q1", "_Q2", "_Q3", "Q4", "Q5", "Q6", "Q7", "Q8", "Q9",
 				"Q10", "Q11", "Q12", "Q13", "Q14"})
@@ -60,7 +59,6 @@ namespace netlist
 	NETLIB_OBJECT(CD4020)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4020, "CD4XXX")
-		//NETLIB_FAMILY()
 		, m_sub(*this, "sub")
 		, m_RESET(*this, "RESET")
 		{
diff --git a/src/lib/netlist/devices/nld_4066.cpp b/src/lib/netlist/devices/nld_4066.cpp
index 254a1a93de3..ba6b5ac5e36 100644
--- a/src/lib/netlist/devices/nld_4066.cpp
+++ b/src/lib/netlist/devices/nld_4066.cpp
@@ -31,7 +31,6 @@ namespace netlist
 	NETLIB_OBJECT(CD4066_GATE)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE, "CD4XXX")
-		//NETLIB_FAMILY("CD4XXX")
 		, m_supply(*this, "VDD", "VSS")
 		, m_R(*this, "R")
 		, m_control(*this, "CTL")
@@ -84,7 +83,6 @@ namespace netlist
 	NETLIB_OBJECT(CD4066_GATE_DYNAMIC)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE_DYNAMIC, "CD4XXX")
-		//NETLIB_FAMILY("CD4XXX")
 		, m_supply(*this, "VDD", "VSS")
 		, m_R(*this, "R", true)
 		, m_DUM1(*this, "_DUM1", true)
diff --git a/src/lib/netlist/devices/nld_4316.cpp b/src/lib/netlist/devices/nld_4316.cpp
index 81d7c981295..270d82e7019 100644
--- a/src/lib/netlist/devices/nld_4316.cpp
+++ b/src/lib/netlist/devices/nld_4316.cpp
@@ -14,7 +14,6 @@ namespace netlist { namespace devices {
 	NETLIB_OBJECT(CD4316_GATE)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(CD4316_GATE, "CD4XXX")
-		//NETLIB_FAMILY("CD4XXX")
 		, m_supply(*this, "VDD", "VSS")
 		, m_R(*this, "_R")
 		, m_S(*this, "S")
diff --git a/src/lib/netlist/devices/nld_74123.cpp b/src/lib/netlist/devices/nld_74123.cpp
index 7477d3bd40c..5b667934f31 100644
--- a/src/lib/netlist/devices/nld_74123.cpp
+++ b/src/lib/netlist/devices/nld_74123.cpp
@@ -230,7 +230,6 @@ namespace netlist
 	NETLIB_OBJECT(4538_dip)
 	{
 		NETLIB_CONSTRUCTOR_MODEL(4538_dip, "CD4XXX")
-		//NETLIB_FAMILY()
 		, m_A(*this, "A")
 		, m_B(*this, "B")
 		{
diff --git a/src/lib/netlist/devices/nlid_proxy.cpp b/src/lib/netlist/devices/nlid_proxy.cpp
index 65e2f5f9a74..8e22157811e 100644
--- a/src/lib/netlist/devices/nlid_proxy.cpp
+++ b/src/lib/netlist/devices/nlid_proxy.cpp
@@ -23,8 +23,6 @@ namespace netlist
 		, m_tp(nullptr)
 		, m_tn(nullptr)
 	{
-		//set_logic_family(inout_proxied->logic_family());
-
 		if (logic_family() == nullptr)
 		{
 			// FIXME convert to error
diff --git a/src/lib/netlist/nl_errstr.h b/src/lib/netlist/nl_errstr.h
index 938bb94e3c8..149de8566b8 100644
--- a/src/lib/netlist/nl_errstr.h
+++ b/src/lib/netlist/nl_errstr.h
@@ -86,7 +86,8 @@ namespace netlist
 	PERRMSGV(MF_NOT_FOUND_IN_SOURCE_COLLECTION,     1, "unable to find {1} in sources collection")
 
 	PERRMSGV(MW_OVERWRITING_PARAM_1_OLD_2_NEW_3,    3, "Overwriting {1} old <{2}> new <{3}>")
-	PERRMSGV(MW_CONNECTING_1_TO_ITSELF,             1, "Connecting {1} to itself. This may be right, though")
+	PERRMSGV(MW_CONNECTING_1_TO_ITSELF,             1, "Connecting net {1} to itself.")
+	PERRMSGV(MW_CONNECTING_1_TO_2_SAME_NET,         3, "Connecting terminals {1} and {2} which are already both on net {3}")
 	PERRMSGV(ME_NC_PIN_1_WITH_CONNECTIONS,          1, "Found NC (not connected) terminal {1} with connections")
 	PERRMSGV(MI_ANALOG_OUTPUT_1_WITHOUT_CONNECTIONS,1, "Found analog output {1} without connections")
 	PERRMSGV(MI_LOGIC_OUTPUT_1_WITHOUT_CONNECTIONS, 1, "Found logic output {1} without connections")
diff --git a/src/lib/netlist/nl_setup.cpp b/src/lib/netlist/nl_setup.cpp
index 893f9df6a09..f98440a7b3f 100755
--- a/src/lib/netlist/nl_setup.cpp
+++ b/src/lib/netlist/nl_setup.cpp
@@ -768,7 +768,11 @@ void setup_t::connect_terminal_output(terminal_t &in, detail::core_terminal_t &o
 		log().debug("connect_terminal_output: {1} {2}\n", in.name(), out.name());
 		// no proxy needed, just merge existing terminal net
 		if (in.has_net())
+		{
+			if (&out.net() == &in.net())
+				log().warning(MW_CONNECTING_1_TO_2_SAME_NET(in.name(), out.name(), in.net().name()));
 			merge_nets(out.net(), in.net());
+		}
 		else
 			out.net().add_terminal(in);
 	}
@@ -1193,6 +1197,41 @@ unique_pool_ptr<devices::nld_base_a_to_d_proxy> logic_family_std_proxy_t::create
 }
 
 
+/// \brief Class representing the logic families.
+///
+///  This is the model representation of the logic families. This is a
+///  netlist specific model. Examples give values for TTL family
+///
+//
+///   |NL? |name  |parameter                                                  |units| TTL   |
+///   |:--:|:-----|:----------------------------------------------------------|:----|------:|
+///   | Y  |IVL   |Input voltage low threshold relative to supply voltage     |     |1.0e-14|
+///   | Y  |IVH   |Input voltage high threshold relative to supply voltage    |     |      0|
+///   | Y  |OVL   |Output voltage minimum voltage relative to supply voltage  |     |1.0e-14|
+///   | Y  |OVL   |Output voltage maximum voltage relative to supply voltage  |     |1.0e-14|
+///   | Y  |ORL   |Output output resistance for logic 0                       |     |      0|
+///   | Y  |ORH   |Output output resistance for logic 1                       |     |      0|
+///
+class family_model_t
+{
+public:
+	family_model_t(param_model_t &model)
+	: m_IVL(model, "IVL")
+	, m_IVH(model, "IVH")
+	, m_OVL(model, "OVL")
+	, m_OVH(model, "OVH")
+	, m_ORL(model, "ORL")
+	, m_ORH(model, "ORH")
+	{}
+
+	param_model_t::value_t m_IVL;    //!< Input voltage low threshold relative to supply voltage
+	param_model_t::value_t m_IVH;    //!< Input voltage high threshold relative to supply voltage
+	param_model_t::value_t m_OVL;    //!< Output voltage minimum voltage relative to supply voltage
+	param_model_t::value_t m_OVH;    //!< Output voltage maximum voltage relative to supply voltage
+	param_model_t::value_t m_ORL;    //!< Output output resistance for logic 0
+	param_model_t::value_t m_ORH;    //!< Output output resistance for logic 1
+};
+
 const logic_family_desc_t *setup_t::family_from_model(const pstring &model)
 {