mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
rsp.c: Modernised cpu core (nw)
This commit is contained in:
Wilbert Pol
parent
dba1a3fdf1
commit
57341a41c2
File diff suppressed because it is too large
Load Diff
@ -16,8 +16,14 @@
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#ifndef __RSP_H__
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#define __RSP_H__
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#include "cpu/drcfe.h"
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#include "cpu/drcuml.h"
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#define USE_SIMD (0)
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#define SIMUL_SIMD (0)
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#define RSP_LOG_UML (0)
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#define RSP_LOG_NATIVE (0)
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#if USE_SIMD
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#include <tmmintrin.h>
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@ -71,15 +77,6 @@ enum
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RSP_V24, RSP_V25, RSP_V26, RSP_V27, RSP_V28, RSP_V29, RSP_V30, RSP_V31
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};
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/***************************************************************************
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PUBLIC FUNCTIONS
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***************************************************************************/
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void rspdrc_flush_drc_cache(device_t *device);
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void rspdrc_set_options(device_t *device, UINT32 options);
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void rspdrc_add_dmem(device_t *device, UINT32 *base);
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void rspdrc_add_imem(device_t *device, UINT32 *base);
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/***************************************************************************
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HELPER MACROS
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***************************************************************************/
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@ -92,9 +89,9 @@ void rspdrc_add_imem(device_t *device, UINT32 *base);
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#define RDREG ((op >> 11) & 31)
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#define SHIFT ((op >> 6) & 31)
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#define RSVAL (rsp->r[RSREG])
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#define RTVAL (rsp->r[RTREG])
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#define RDVAL (rsp->r[RDREG])
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#define RSVAL (m_rsp_state->r[RSREG])
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#define RTVAL (m_rsp_state->r[RTREG])
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#define RDVAL (m_rsp_state->r[RDREG])
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#define FRREG ((op >> 21) & 31)
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#define FTREG ((op >> 16) & 31)
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@ -144,135 +141,417 @@ union ACCUMULATOR_REG
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};
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#define MCFG_RSP_DP_REG_R_CB(_devcb) \
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devcb = &rsp_cpu_device::static_set_dp_reg_r_callback(*device, DEVCB_##_devcb);
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devcb = &rsp_device::static_set_dp_reg_r_callback(*device, DEVCB_##_devcb);
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#define MCFG_RSP_DP_REG_W_CB(_devcb) \
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devcb = &rsp_cpu_device::static_set_dp_reg_w_callback(*device, DEVCB_##_devcb);
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devcb = &rsp_device::static_set_dp_reg_w_callback(*device, DEVCB_##_devcb);
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#define MCFG_RSP_SP_REG_R_CB(_devcb) \
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devcb = &rsp_cpu_device::static_set_sp_reg_r_callback(*device, DEVCB_##_devcb);
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devcb = &rsp_device::static_set_sp_reg_r_callback(*device, DEVCB_##_devcb);
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#define MCFG_RSP_SP_REG_W_CB(_devcb) \
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devcb = &rsp_cpu_device::static_set_sp_reg_w_callback(*device, DEVCB_##_devcb);
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devcb = &rsp_device::static_set_sp_reg_w_callback(*device, DEVCB_##_devcb);
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#define MCFG_RSP_SP_SET_STATUS_CB(_devcb) \
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devcb = &rsp_cpu_device::static_set_status_callback(*device, DEVCB_##_devcb);
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devcb = &rsp_device::static_set_status_callback(*device, DEVCB_##_devcb);
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class rsp_cpu_device : public legacy_cpu_device
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class rsp_frontend;
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class rsp_device : public cpu_device
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{
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protected:
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// construction/destruction
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rsp_cpu_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
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friend class rsp_frontend;
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public:
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// construction/destruction
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rsp_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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void resolve_cb();
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template<class _Object> static devcb_base &static_set_dp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).dp_reg_r_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_dp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).dp_reg_w_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_sp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_reg_r_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_sp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_reg_w_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_status_callback(device_t &device, _Object object) { return downcast<rsp_cpu_device &>(device).sp_set_status_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_dp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_dp_reg_r_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_dp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_dp_reg_w_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_sp_reg_r_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_reg_r_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_sp_reg_w_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_reg_w_func.set_callback(object); }
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template<class _Object> static devcb_base &static_set_status_callback(device_t &device, _Object object) { return downcast<rsp_device &>(device).m_sp_set_status_func.set_callback(object); }
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void rspdrc_flush_drc_cache();
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void rspdrc_set_options(UINT32 options);
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void rspdrc_add_dmem(UINT32 *base);
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void rspdrc_add_imem(UINT32 *base);
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void ccfunc_read8();
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void ccfunc_read16();
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void ccfunc_read32();
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void ccfunc_write8();
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void ccfunc_write16();
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void ccfunc_write32();
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void ccfunc_get_cop0_reg();
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void ccfunc_set_cop0_reg();
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void ccfunc_unimplemented_opcode();
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void ccfunc_sp_set_status_cb();
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void ccfunc_unimplemented();
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#if USE_SIMD
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void ccfunc_rsp_lbv_simd();
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void ccfunc_rsp_lsv_simd();
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void ccfunc_rsp_llv_simd();
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void ccfunc_rsp_ldv_simd();
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void ccfunc_rsp_lqv_simd();
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void ccfunc_rsp_lrv_simd();
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void ccfunc_rsp_lpv_simd();
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void ccfunc_rsp_luv_simd();
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void ccfunc_rsp_lhv_simd();
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void ccfunc_rsp_lfv_simd();
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void ccfunc_rsp_lwv_simd();
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void ccfunc_rsp_ltv_simd();
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void ccfunc_rsp_sbv_simd();
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void ccfunc_rsp_ssv_simd();
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void ccfunc_rsp_slv_simd();
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void ccfunc_rsp_sdv_simd();
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void ccfunc_rsp_sqv_simd();
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void ccfunc_rsp_srv_simd();
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void ccfunc_rsp_spv_simd();
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void ccfunc_rsp_suv_simd();
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void ccfunc_rsp_shv_simd();
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void ccfunc_rsp_sfv_simd();
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void ccfunc_rsp_swv_simd();
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void ccfunc_rsp_stv_simd();
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void ccfunc_rsp_vmulf_simd();
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void ccfunc_rsp_vmulu_simd();
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void ccfunc_rsp_vmudl_simd();
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void ccfunc_rsp_vmudm_simd();
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void ccfunc_rsp_vmudn_simd();
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void ccfunc_rsp_vmudh_simd();
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void ccfunc_rsp_vmacf_simd();
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void ccfunc_rsp_vmacu_simd();
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void ccfunc_rsp_vmadl_simd();
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void ccfunc_rsp_vmadm_simd();
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void ccfunc_rsp_vmadn_simd();
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void ccfunc_rsp_vmadh_simd();
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void ccfunc_rsp_vadd_simd();
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void ccfunc_rsp_vsub_simd();
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void ccfunc_rsp_vabs_simd();
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void ccfunc_rsp_vaddc_simd();
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void ccfunc_rsp_vsubc_simd();
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void ccfunc_rsp_vsaw_simd();
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void ccfunc_rsp_vlt_simd();
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void ccfunc_rsp_veq_simd();
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void ccfunc_rsp_vne_simd();
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void ccfunc_rsp_vge_simd();
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void ccfunc_rsp_vcl_simd();
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void ccfunc_rsp_vch_simd();
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void ccfunc_rsp_vcr_simd();
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void ccfunc_rsp_vmrg_simd();
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void ccfunc_rsp_vand_simd();
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void ccfunc_rsp_vnand_simd();
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void ccfunc_rsp_vor_simd();
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void ccfunc_rsp_vnor_simd();
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void ccfunc_rsp_vxor_simd();
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void ccfunc_rsp_vnxor_simd();
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void ccfunc_rsp_vrcp_simd();
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void ccfunc_rsp_vrcpl_simd();
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void ccfunc_rsp_vrcph_simd();
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void ccfunc_rsp_vmov_simd();
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void ccfunc_rsp_vrsql_simd();
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void ccfunc_rsp_vrsqh_simd();
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void ccfunc_mfc2_simd();
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void ccfunc_cfc2_simd();
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void ccfunc_mtc2_simd();
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void ccfunc_ctc2_simd();
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#endif
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#if (!USE_SIMD || SIMUL_SIMD)
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void ccfunc_rsp_lbv_scalar();
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void ccfunc_rsp_lsv_scalar();
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void ccfunc_rsp_llv_scalar();
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void ccfunc_rsp_ldv_scalar();
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void ccfunc_rsp_lqv_scalar();
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void ccfunc_rsp_lrv_scalar();
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void ccfunc_rsp_lpv_scalar();
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void ccfunc_rsp_luv_scalar();
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void ccfunc_rsp_lhv_scalar();
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void ccfunc_rsp_lfv_scalar();
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void ccfunc_rsp_lwv_scalar();
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void ccfunc_rsp_ltv_scalar();
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void ccfunc_rsp_sbv_scalar();
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void ccfunc_rsp_ssv_scalar();
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void ccfunc_rsp_slv_scalar();
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void ccfunc_rsp_sdv_scalar();
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void ccfunc_rsp_sqv_scalar();
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void ccfunc_rsp_srv_scalar();
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void ccfunc_rsp_spv_scalar();
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void ccfunc_rsp_suv_scalar();
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void ccfunc_rsp_shv_scalar();
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void ccfunc_rsp_sfv_scalar();
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void ccfunc_rsp_swv_scalar();
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void ccfunc_rsp_stv_scalar();
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void ccfunc_rsp_vmulf_scalar();
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void ccfunc_rsp_vmulu_scalar();
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void ccfunc_rsp_vmudl_scalar();
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void ccfunc_rsp_vmudm_scalar();
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void ccfunc_rsp_vmudn_scalar();
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void ccfunc_rsp_vmudh_scalar();
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void ccfunc_rsp_vmacf_scalar();
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void ccfunc_rsp_vmacu_scalar();
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void ccfunc_rsp_vmadl_scalar();
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void ccfunc_rsp_vmadm_scalar();
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void ccfunc_rsp_vmadn_scalar();
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void ccfunc_rsp_vmadh_scalar();
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void ccfunc_rsp_vadd_scalar();
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void ccfunc_rsp_vsub_scalar();
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void ccfunc_rsp_vabs_scalar();
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void ccfunc_rsp_vaddc_scalar();
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void ccfunc_rsp_vsubc_scalar();
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void ccfunc_rsp_vsaw_scalar();
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void ccfunc_rsp_vlt_scalar();
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void ccfunc_rsp_veq_scalar();
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void ccfunc_rsp_vne_scalar();
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void ccfunc_rsp_vge_scalar();
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void ccfunc_rsp_vcl_scalar();
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void ccfunc_rsp_vch_scalar();
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void ccfunc_rsp_vcr_scalar();
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void ccfunc_rsp_vmrg_scalar();
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void ccfunc_rsp_vand_scalar();
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void ccfunc_rsp_vnand_scalar();
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void ccfunc_rsp_vor_scalar();
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void ccfunc_rsp_vnor_scalar();
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void ccfunc_rsp_vxor_scalar();
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void ccfunc_rsp_vnxor_scalar();
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void ccfunc_rsp_vrcp_scalar();
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void ccfunc_rsp_vrcpl_scalar();
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void ccfunc_rsp_vrcph_scalar();
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void ccfunc_rsp_vmov_scalar();
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void ccfunc_rsp_vrsql_scalar();
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void ccfunc_rsp_vrsqh_scalar();
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void ccfunc_mfc2_scalar();
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void ccfunc_cfc2_scalar();
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void ccfunc_mtc2_scalar();
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void ccfunc_ctc2_scalar();
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#endif
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#if USE_SIMD && SIMUL_SIMD
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void ccfunc_backup_regs();
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void ccfunc_restore_regs();
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void ccfunc_verify_regs();
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#endif
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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virtual void device_stop();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 1; }
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virtual UINT32 execute_input_lines() const { return 1; }
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virtual UINT32 execute_default_irq_vector() const { return 0; }
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virtual void execute_run();
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virtual void execute_set_input(int inputnum, int state) { }
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry);
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virtual void state_export(const device_state_entry &entry);
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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private:
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address_space_config m_program_config;
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/* fast RAM info */
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struct fast_ram_info
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{
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offs_t start; /* start of the RAM block */
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offs_t end; /* end of the RAM block */
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UINT8 readonly; /* TRUE if read-only */
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void * base; /* base in memory where the RAM lives */
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};
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devcb_read32 dp_reg_r_func;
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devcb_write32 dp_reg_w_func;
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devcb_read32 sp_reg_r_func;
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devcb_write32 sp_reg_w_func;
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devcb_write32 sp_set_status_func;
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};
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/* internal compiler state */
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struct compiler_state
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{
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UINT32 cycles; /* accumulated cycles */
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UINT8 checkints; /* need to check interrupts before next instruction */
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UINT8 checksoftints; /* need to check software interrupts before next instruction */
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uml::code_label labelnum; /* index for local labels */
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};
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struct rspimp_state;
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struct rsp_state
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{
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FILE *exec_output;
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/* core state */
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drc_cache m_cache; /* pointer to the DRC code cache */
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drcuml_state * m_drcuml; /* DRC UML generator state */
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rsp_frontend * m_drcfe; /* pointer to the DRC front-end state */
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UINT32 m_drcoptions; /* configurable DRC options */
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UINT32 pc;
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UINT32 r[35];
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VECTOR_REG v[32];
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UINT16 vflag[6][8];
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/* internal stuff */
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UINT8 m_cache_dirty; /* true if we need to flush the cache */
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/* parameters for subroutines */
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UINT64 m_numcycles; /* return value from gettotalcycles */
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const char * m_format; /* format string for print_debug */
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UINT32 m_arg2; /* print_debug argument 3 */
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UINT32 m_arg3; /* print_debug argument 4 */
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UINT32 m_vres[8]; /* used for temporary vector results */
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/* register mappings */
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uml::parameter m_regmap[34]; /* parameter to register mappings for all 32 integer registers */
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/* subroutines */
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uml::code_handle * m_entry; /* entry point */
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uml::code_handle * m_nocode; /* nocode exception handler */
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uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */
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uml::code_handle * m_read8; /* read byte */
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uml::code_handle * m_write8; /* write byte */
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uml::code_handle * m_read16; /* read half */
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uml::code_handle * m_write16; /* write half */
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uml::code_handle * m_read32; /* read word */
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uml::code_handle * m_write32; /* write word */
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struct internal_rsp_state
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{
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UINT32 pc;
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UINT32 r[35];
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UINT32 arg0;
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UINT32 arg1;
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UINT32 jmpdest;
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int icount;
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};
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internal_rsp_state *m_rsp_state;
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FILE *m_exec_output;
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VECTOR_REG m_v[32];
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UINT16 m_vflag[6][8];
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#if SIMUL_SIMD
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UINT32 old_r[35];
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UINT8 old_dmem[4096];
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UINT32 m_old_r[35];
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UINT8 m_old_dmem[4096];
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UINT32 scalar_r[35];
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UINT8 scalar_dmem[4096];
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UINT32 m_scalar_r[35];
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UINT8 m_scalar_dmem[4096];
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INT32 old_reciprocal_res;
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UINT32 old_reciprocal_high;
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INT32 old_dp_allowed;
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INT32 m_old_reciprocal_res;
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UINT32 m_old_reciprocal_high;
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INT32 m_old_dp_allowed;
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INT32 scalar_reciprocal_res;
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UINT32 scalar_reciprocal_high;
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INT32 scalar_dp_allowed;
|
||||
INT32 m_scalar_reciprocal_res;
|
||||
UINT32 m_scalar_reciprocal_high;
|
||||
INT32 m_scalar_dp_allowed;
|
||||
|
||||
INT32 simd_reciprocal_res;
|
||||
UINT32 simd_reciprocal_high;
|
||||
INT32 simd_dp_allowed;
|
||||
INT32 m_simd_reciprocal_res;
|
||||
UINT32 m_simd_reciprocal_high;
|
||||
INT32 m_simd_dp_allowed;
|
||||
#endif
|
||||
|
||||
#if USE_SIMD
|
||||
// Mirror of v[] for now, to be used in parallel as
|
||||
// more vector ops are transitioned over
|
||||
__m128i xv[32];
|
||||
__m128i xvflag[6];
|
||||
__m128i m_xv[32];
|
||||
__m128i m_xvflag[6];
|
||||
#endif
|
||||
UINT32 sr;
|
||||
UINT32 step_count;
|
||||
UINT32 m_sr;
|
||||
UINT32 m_step_count;
|
||||
|
||||
ACCUMULATOR_REG accum[8];
|
||||
ACCUMULATOR_REG m_accum[8];
|
||||
#if USE_SIMD
|
||||
__m128i accum_h;
|
||||
__m128i accum_m;
|
||||
__m128i accum_l;
|
||||
__m128i accum_ll;
|
||||
__m128i m_accum_h;
|
||||
__m128i m_accum_m;
|
||||
__m128i m_accum_l;
|
||||
__m128i m_accum_ll;
|
||||
#endif
|
||||
INT32 reciprocal_res;
|
||||
UINT32 reciprocal_high;
|
||||
INT32 dp_allowed;
|
||||
INT32 m_reciprocal_res;
|
||||
UINT32 m_reciprocal_high;
|
||||
INT32 m_dp_allowed;
|
||||
|
||||
UINT32 ppc;
|
||||
UINT32 nextpc;
|
||||
UINT32 m_ppc;
|
||||
UINT32 m_nextpc;
|
||||
|
||||
device_irq_acknowledge_delegate irq_callback;
|
||||
rsp_cpu_device *device;
|
||||
address_space *program;
|
||||
direct_read_data *direct;
|
||||
int icount;
|
||||
address_space *m_program;
|
||||
protected:
|
||||
direct_read_data *m_direct;
|
||||
|
||||
UINT32 *dmem32;
|
||||
UINT16 *dmem16;
|
||||
UINT8 *dmem8;
|
||||
private:
|
||||
UINT32 *m_dmem32;
|
||||
UINT16 *m_dmem16;
|
||||
UINT8 *m_dmem8;
|
||||
|
||||
UINT32 *imem32;
|
||||
UINT16 *imem16;
|
||||
UINT8 *imem8;
|
||||
UINT32 *m_imem32;
|
||||
UINT16 *m_imem16;
|
||||
UINT8 *m_imem8;
|
||||
|
||||
rspimp_state* impstate;
|
||||
UINT32 m_debugger_temp;
|
||||
bool m_isdrc;
|
||||
|
||||
devcb_read32 m_dp_reg_r_func;
|
||||
devcb_write32 m_dp_reg_w_func;
|
||||
devcb_read32 m_sp_reg_r_func;
|
||||
devcb_write32 m_sp_reg_w_func;
|
||||
devcb_write32 m_sp_set_status_func;
|
||||
|
||||
UINT8 READ8(UINT32 address);
|
||||
UINT16 READ16(UINT32 address);
|
||||
UINT32 READ32(UINT32 address);
|
||||
void WRITE8(UINT32 address, UINT8 data);
|
||||
void WRITE16(UINT32 address, UINT16 data);
|
||||
void WRITE32(UINT32 address, UINT32 data);
|
||||
UINT32 get_cop0_reg(int reg);
|
||||
void set_cop0_reg(int reg, UINT32 data);
|
||||
void unimplemented_opcode(UINT32 op);
|
||||
void handle_lwc2(UINT32 op);
|
||||
void handle_swc2(UINT32 op);
|
||||
UINT16 SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive);
|
||||
UINT16 SATURATE_ACCUM1(int accum, UINT16 negative, UINT16 positive);
|
||||
void handle_vector_ops(UINT32 op);
|
||||
#if USE_SIMD
|
||||
UINT16 VEC_ACCUM_H(int x);
|
||||
UINT16 VEC_ACCUM_M(int x);
|
||||
UINT16 VEC_ACCUM_L(int x);
|
||||
UINT16 VEC_ACCUM_LL(int x);
|
||||
UINT16 VEC_CARRY_FLAG(const int x);
|
||||
UINT16 VEC_COMPARE_FLAG(const int x);
|
||||
UINT16 VEC_CLIP1_FLAG(const int x);
|
||||
UINT16 VEC_ZERO_FLAG(const int x);
|
||||
UINT16 VEC_CLIP2_FLAG(const int x);
|
||||
UINT16 VEC_SATURATE_ACCUM(int accum, int slice, UINT16 negative, UINT16 positive);
|
||||
#endif
|
||||
void load_fast_iregs(drcuml_block *block);
|
||||
void save_fast_iregs(drcuml_block *block);
|
||||
UINT8 DM_READ8(UINT32 address);
|
||||
UINT16 DM_READ16(UINT32 address);
|
||||
UINT32 DM_READ32(UINT32 address);
|
||||
void DM_WRITE8(UINT32 address, UINT8 data);
|
||||
void DM_WRITE16(UINT32 address, UINT16 data);
|
||||
void DM_WRITE32(UINT32 address, UINT32 data);
|
||||
void rspcom_init();
|
||||
int generate_lwc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_swc2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void execute_run_drc();
|
||||
void code_flush_cache();
|
||||
void code_compile_block(offs_t pc);
|
||||
void static_generate_entry_point();
|
||||
void static_generate_nocode_handler();
|
||||
void static_generate_out_of_cycles();
|
||||
void static_generate_memory_accessor(int size, int iswrite, const char *name, uml::code_handle *&handleptr);
|
||||
void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
|
||||
void generate_checksum_block(drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
|
||||
void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT8 linkreg);
|
||||
int generate_vector_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_special(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_regimm(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_cop2(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
int generate_cop0(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
|
||||
void log_add_disasm_comment(drcuml_block *block, UINT32 pc, UINT32 op);
|
||||
};
|
||||
|
||||
CPU_GET_INFO( rsp_int );
|
||||
|
||||
class rsp_int_device : public rsp_cpu_device
|
||||
{
|
||||
public:
|
||||
rsp_int_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
extern const device_type RSP_INT;
|
||||
|
||||
CPU_GET_INFO( rsp_drc );
|
||||
|
||||
class rsp_drc_device : public rsp_cpu_device
|
||||
{
|
||||
public:
|
||||
rsp_drc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
extern const device_type RSP_DRC;
|
||||
|
||||
extern const device_type RSP;
|
||||
|
||||
extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
|
||||
|
||||
#endif /* __RSP_H__ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -22,9 +22,9 @@
|
||||
// rsp_frontend - constructor
|
||||
//-------------------------------------------------
|
||||
|
||||
rsp_frontend::rsp_frontend(rsp_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
|
||||
: drc_frontend(*state.device, window_start, window_end, max_sequence),
|
||||
m_context(state)
|
||||
rsp_frontend::rsp_frontend(rsp_device &rsp, UINT32 window_start, UINT32 window_end, UINT32 max_sequence)
|
||||
: drc_frontend(rsp, window_start, window_end, max_sequence),
|
||||
m_rsp(rsp)
|
||||
{
|
||||
}
|
||||
|
||||
@ -39,7 +39,7 @@ bool rsp_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
|
||||
UINT32 op, opswitch;
|
||||
|
||||
// fetch the opcode
|
||||
op = desc.opptr.l[0] = m_context.direct->read_decrypted_dword(desc.physpc | 0x1000);
|
||||
op = desc.opptr.l[0] = m_rsp.m_direct->read_decrypted_dword(desc.physpc | 0x1000);
|
||||
|
||||
// all instructions are 4 bytes and default to a single cycle each
|
||||
desc.length = 4;
|
||||
|
||||
@ -36,7 +36,7 @@ class rsp_frontend : public drc_frontend
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
rsp_frontend(rsp_state &state, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
|
||||
rsp_frontend(rsp_device &rsp, UINT32 window_start, UINT32 window_end, UINT32 max_sequence);
|
||||
|
||||
protected:
|
||||
// required overrides
|
||||
@ -50,7 +50,7 @@ private:
|
||||
bool describe_cop2(UINT32 op, opcode_desc &desc);
|
||||
|
||||
// internal state
|
||||
rsp_state &m_context;
|
||||
rsp_device &m_rsp;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -2417,10 +2417,11 @@ void n64_state::machine_start()
|
||||
/* configure fast RAM regions for DRC */
|
||||
dynamic_cast<mips3_device *>(machine().device("maincpu"))->mips3drc_add_fastram(0x00000000, 0x007fffff, FALSE, rdram);
|
||||
|
||||
rspdrc_set_options(machine().device("rsp"), RSPDRC_STRICT_VERIFY);
|
||||
rspdrc_flush_drc_cache(machine().device("rsp"));
|
||||
rspdrc_add_dmem(machine().device("rsp"), rsp_dmem);
|
||||
rspdrc_add_imem(machine().device("rsp"), rsp_imem);
|
||||
rsp_device *rsp = machine().device<rsp_device>("rsp");
|
||||
rsp->rspdrc_set_options(RSPDRC_STRICT_VERIFY);
|
||||
rsp->rspdrc_flush_drc_cache();
|
||||
rsp->rspdrc_add_dmem(rsp_dmem);
|
||||
rsp->rspdrc_add_imem(rsp_imem);
|
||||
|
||||
/* add a hook for battery save */
|
||||
machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(n64_state::n64_machine_stop),this));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user