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Merge pull request #4512 from tyfighter/master

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MIPS3: Add minimal support for revealing the Secondary Cache Line siz…
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R. Belmont 2019-01-16 09:26:29 -05:00 committed by GitHub
commit 57abfa52de
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3 changed files with 10 additions and 0 deletions
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1
src/devices/cpu/mips/mips3.cpp
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@ -166,6 +166,7 @@ mips3_device::mips3_device(const machine_config &mconfig, device_type type, cons
, m_dword_xor(data_bits == 64 ? (m_bigendian ? DWORD_XOR_BE(0) : DWORD_XOR_LE(0)) : 0)
, c_icache_size(0)
, c_dcache_size(0)
, c_secondary_cache_line_size(0)
, m_fastram_select(0)
, m_debugger_temp(0)
, m_drc_cache(DRC_CACHE_SIZE + sizeof(internal_mips3_state) + 0x800000)

2
src/devices/cpu/mips/mips3.h
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@ -297,6 +297,7 @@ public:
void set_icache_size(size_t icache_size) { c_icache_size = icache_size; }
void set_dcache_size(size_t dcache_size) { c_dcache_size = dcache_size; }
void set_secondary_cache_line_size(uint8_t secondary_cache_line_size) { c_secondary_cache_line_size = secondary_cache_line_size; }
void set_system_clock(uint32_t system_clock) { c_system_clock = system_clock; }
TIMER_CALLBACK_MEMBER(compare_int_callback);
@ -442,6 +443,7 @@ protected:
/* cache memory */
size_t c_icache_size;
size_t c_dcache_size;
uint8_t c_secondary_cache_line_size;
/* MMU */
mips3_tlb_entry m_tlb[MIPS3_MAX_TLB_ENTRIES];

7
src/devices/cpu/mips/mips3com.cpp
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@ -273,6 +273,13 @@ uint32_t mips3_device::compute_config_register()
else if (c_icache_size <= 0x40000) configreg |= 6 << 9;
else configreg |= 7 << 9;
if (c_secondary_cache_line_size != 0) {
configreg &= ~((0xf << 20) | (1 << 17));
if (c_secondary_cache_line_size <= 0x10) configreg |= 0 << 22;
else if (c_secondary_cache_line_size <= 0x20) configreg |= 1 << 22;
else if (c_secondary_cache_line_size <= 0x40) configreg |= 2 << 22;
else configreg |= 3 << 22;
}
/* set the system clock divider */
int divisor = 2;
if (c_system_clock != 0)