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z80: use LOGMASKED instead of a macro for each log type,

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xtal: add 3.58MHz
This commit is contained in:
hap 2024-09-02 12:48:56 +02:00
parent b9aecfae45
commit 580e0a9638
8 changed files with 21 additions and 25 deletions
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2
src/devices/cpu/z80/nsc800.cpp
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@ -16,8 +16,6 @@
//#define VERBOSE (LOG_INT) //#define VERBOSE (LOG_INT)
#include "logmacro.h" #include "logmacro.h"
#define LOGINT(...) LOGMASKED(LOG_INT, __VA_ARGS__)
// device type definition // device type definition
DEFINE_DEVICE_TYPE(NSC800, nsc800_device, "nsc800", "National Semiconductor NSC800") DEFINE_DEVICE_TYPE(NSC800, nsc800_device, "nsc800", "National Semiconductor NSC800")

1
src/devices/cpu/z80/r800.cpp
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@ -26,7 +26,6 @@ TODO:
//#define VERBOSE (LOG_INT) //#define VERBOSE (LOG_INT)
#include "logmacro.h" #include "logmacro.h"
#define LOGINT(...) LOGMASKED(LOG_INT, __VA_ARGS__)
//************************************************************************** //**************************************************************************
// GLOBAL VARIABLES // GLOBAL VARIABLES

11
src/devices/cpu/z80/z80.cpp
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@ -33,8 +33,6 @@ TODO:
#define VERBOSE (LOG_UNDOC) #define VERBOSE (LOG_UNDOC)
#include "logmacro.h" #include "logmacro.h"
#define LOGINT(...) LOGMASKED(LOG_INT, __VA_ARGS__)
#define LOGUNDOC(...) LOGMASKED(LOG_UNDOC, __VA_ARGS__)
bool z80_device::tables_initialised = false; bool z80_device::tables_initialised = false;
u8 z80_device::SZ[] = {}; // zero and sign flags u8 z80_device::SZ[] = {}; // zero and sign flags
@ -468,14 +466,15 @@ void z80_device::set_f(u8 f)
void z80_device::illegal_1() void z80_device::illegal_1()
{ {
LOGUNDOC("ill. opcode $%02x $%02x ($%04x)\n", LOGMASKED(LOG_UNDOC, "ill. opcode $%02x $%02x ($%04x)\n",
m_opcodes.read_byte(translate_memory_address((PC - 1) & 0xffff)), m_opcodes.read_byte(translate_memory_address(PC)), PC - 1); m_opcodes.read_byte(translate_memory_address((PC - 1) & 0xffff)),
m_opcodes.read_byte(translate_memory_address(PC)), PC - 1);
} }
void z80_device::illegal_2() void z80_device::illegal_2()
{ {
LOGUNDOC("ill. opcode $ed $%02x\n", LOGMASKED(LOG_UNDOC, "ill. opcode $ed $%02x\n",
m_opcodes.read_byte(translate_memory_address((PC - 1) & 0xffff))); m_opcodes.read_byte(translate_memory_address((PC - 1) & 0xffff)));
} }
/**************************************************************************** /****************************************************************************

20
src/devices/cpu/z80/z80.lst
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@ -148,7 +148,7 @@ macro ret_cond
macro retn macro retn
call pop call pop
PC = TDAT; LOGINT("RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2; PC = TDAT; LOGMASKED(LOG_INT, "RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2;
macro z80n:retn macro z80n:retn
m_out_retn_seen_cb(0); m_out_retn_seen_cb(0);
@ -159,7 +159,7 @@ macro z80n:retn
} else { } else {
PC = TDAT; PC = TDAT;
} }
LOGINT("RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2; LOGMASKED(LOG_INT, "RETN m_iff1:%d m_iff2:%d\n", m_iff1, m_iff2); WZ = PC; m_iff1 = m_iff2;
macro reti macro reti
call pop call pop
@ -536,7 +536,7 @@ macro take_interrupt
// fetch the IRQ vector // fetch the IRQ vector
device_z80daisy_interface *intf = daisy_get_irq_device(); device_z80daisy_interface *intf = daisy_get_irq_device();
m_tmp_irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback(0, m_pc.w); m_tmp_irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback(0, m_pc.w);
LOGINT("single INT m_tmp_irq_vector $%02x\n", m_tmp_irq_vector); LOGMASKED(LOG_INT, "single INT m_tmp_irq_vector $%02x\n", m_tmp_irq_vector);
} }
// 'interrupt latency' cycles // 'interrupt latency' cycles
+ 2 + 2
@ -553,10 +553,10 @@ macro take_interrupt
TADR = m_tmp_irq_vector; TADR = m_tmp_irq_vector;
call rm16 call rm16
PC = TDAT; PC = TDAT;
LOGINT("IM2 [$%04x] = $%04x\n", m_tmp_irq_vector, PC); LOGMASKED(LOG_INT, "IM2 [$%04x] = $%04x\n", m_tmp_irq_vector, PC);
} else if (m_im == 1) { } else if (m_im == 1) {
// Interrupt mode 1. RST 38h // Interrupt mode 1. RST 38h
LOGINT("'%s' IM1 $0038\n", tag()); LOGMASKED(LOG_INT, "'%s' IM1 $0038\n", tag());
// RST $38 // RST $38
+ 5 + 5
TDAT = PC; TDAT = PC;
@ -566,7 +566,7 @@ macro take_interrupt
/* Interrupt mode 0. We check for CALL and JP instructions, /* Interrupt mode 0. We check for CALL and JP instructions,
if neither of these were found we assume a 1 byte opcode if neither of these were found we assume a 1 byte opcode
was placed on the databus */ was placed on the databus */
LOGINT("IM0 $%04x\n", m_tmp_irq_vector); LOGMASKED(LOG_INT, "IM0 $%04x\n", m_tmp_irq_vector);
// check for nop // check for nop
if (m_tmp_irq_vector != 0x00) { if (m_tmp_irq_vector != 0x00) {
@ -580,16 +580,16 @@ macro take_interrupt
// JP $xxxx cycles // JP $xxxx cycles
+ 10 + 10
PC = m_tmp_irq_vector & 0xffff; PC = m_tmp_irq_vector & 0xffff;
} else if (m_tmp_irq_vector == 0xfb) {
// rst (or other opcodes?)
+ 4
ei();
} else if ((m_tmp_irq_vector & 0xc7) == 0xc7) { } else if ((m_tmp_irq_vector & 0xc7) == 0xc7) {
// RST $xx cycles // RST $xx cycles
+ 5 + 5
TDAT = PC; TDAT = PC;
call wm16_sp call wm16_sp
PC = m_tmp_irq_vector & 0x0038; PC = m_tmp_irq_vector & 0x0038;
} else if (m_tmp_irq_vector == 0xfb) {
// EI cycles
+ 4
ei();
} else { } else {
logerror("take_interrupt: unexpected opcode in im0 mode: 0x%02x\n", m_tmp_irq_vector); logerror("take_interrupt: unexpected opcode in im0 mode: 0x%02x\n", m_tmp_irq_vector);
} }

1
src/devices/cpu/z80/z80n.cpp
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@ -15,7 +15,6 @@
//#define VERBOSE (LOG_INT) //#define VERBOSE (LOG_INT)
#include "logmacro.h" #include "logmacro.h"
#define LOGINT(...) LOGMASKED(LOG_INT, __VA_ARGS__)
DEFINE_DEVICE_TYPE(Z80N, z80n_device, "z80n", "Z80N") DEFINE_DEVICE_TYPE(Z80N, z80n_device, "z80n", "Z80N")

1
src/emu/xtal.cpp
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@ -102,6 +102,7 @@ const double XTAL::known_xtals[] = {
3'579'000, // 3.579_MHz_XTAL BeebOPL 3'579'000, // 3.579_MHz_XTAL BeebOPL
3'579'545, // 3.579545_MHz_XTAL NTSC color subcarrier, extremely common, used on 100's of PCBs (Keytronic custom part #48-300-010 is equivalent) 3'579'545, // 3.579545_MHz_XTAL NTSC color subcarrier, extremely common, used on 100's of PCBs (Keytronic custom part #48-300-010 is equivalent)
3'579'575, // 3.579575_MHz_XTAL Atari 2600 NTSC 3'579'575, // 3.579575_MHz_XTAL Atari 2600 NTSC
3'580'000, // 3.58_MHz_XTAL Resonator - Ritam Monty
3'680'000, // 3.68_MHz_XTAL Resonator - Baud rate clock for the 6551 in the MTU-130 3'680'000, // 3.68_MHz_XTAL Resonator - Baud rate clock for the 6551 in the MTU-130
3'686'400, // 3.6864_MHz_XTAL Baud rate clock for MC68681 and similar UARTs 3'686'400, // 3.6864_MHz_XTAL Baud rate clock for MC68681 and similar UARTs
3'840'000, // 3.84_MHz_XTAL Fairlight CMI Alphanumeric Keyboard 3'840'000, // 3.84_MHz_XTAL Fairlight CMI Alphanumeric Keyboard

4
src/mame/handheld/hh_hmcs40.cpp
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@ -71,7 +71,7 @@ known chips:
@A89 HD38820 1984, Bandai Pair Match (PT-460) (2/2) @A89 HD38820 1984, Bandai Pair Match (PT-460) (2/2)
A34 HD44801 1981, SciSys Mini Chess -> saitek/minichess.cpp A34 HD44801 1981, SciSys Mini Chess -> saitek/minichess.cpp
A50 HD44801 1981, CXG Sensor Computachess -> cxg/scptchess.cpp A50 HD44801 1981, CXG Sensor Computachess -> cxg/computachess.cpp
A75 HD44801 1982, Alpha 8201 protection MCU -> alpha/alpha8201.* A75 HD44801 1982, Alpha 8201 protection MCU -> alpha/alpha8201.*
*A85 HD44801 1982, SciSys Travel Sensor / Travel Mate / Chesspartner 5000/6000 *A85 HD44801 1982, SciSys Travel Sensor / Travel Mate / Chesspartner 5000/6000
*A92 HD44801 1982, SciSys Play Bridge Computer *A92 HD44801 1982, SciSys Play Bridge Computer
@ -79,7 +79,7 @@ known chips:
B42 HD44801 1983, Alpha 8303 protection MCU (see 8201) B42 HD44801 1983, Alpha 8303 protection MCU (see 8201)
*B43 HD44801 1983, Alpha 8304 protection MCU (see 8201) *B43 HD44801 1983, Alpha 8304 protection MCU (see 8201)
C57 HD44801 1985, Alpha 8505 protection MCU (see 8201) C57 HD44801 1985, Alpha 8505 protection MCU (see 8201)
C89 HD44801 1985, CXG Portachess (1985 version) -> cxg/scptchess.cpp C89 HD44801 1985, CXG Portachess (1985 version) -> cxg/computachess.cpp
*A86 HD44820 1983, Chess King Pocket Micro / Mighty Midget *A86 HD44820 1983, Chess King Pocket Micro / Mighty Midget
*B63 HD44820 1985, CXG Pocket Chess (12 buttons) *B63 HD44820 1985, CXG Pocket Chess (12 buttons)

6
src/mame/handheld/monty.cpp
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@ -19,7 +19,7 @@ is blue and says Master Monty at the top. Both of these versions are hand-upgra
by adding chips and wires to the inside of the game. by adding chips and wires to the inside of the game.
Hardware notes: Hardware notes:
- Z80 @ ~3.58MHz - Z80, 3.58MT ceramic resonator
- 2KB SRAM, 16KB ROM(32KB on mmonty) - 2KB SRAM, 16KB ROM(32KB on mmonty)
- 2*16KB ROM sockets for vocabulary expansion - 2*16KB ROM sockets for vocabulary expansion
- 2*SED1503F, 40*32 LCD screen, beeper - 2*SED1503F, 40*32 LCD screen, beeper
@ -66,7 +66,7 @@ protected:
private: private:
required_device<z80_device> m_maincpu; required_device<z80_device> m_maincpu;
required_device_array<sed1503_device, 2> m_lcd; required_device_array<sed1503_device, 2> m_lcd;
required_device<dac_bit_interface> m_dac; required_device<dac_1bit_device> m_dac;
required_ioport_array<6> m_inputs; required_ioport_array<6> m_inputs;
u64 m_lcd_data[32] = { }; u64 m_lcd_data[32] = { };
@ -233,7 +233,7 @@ INPUT_PORTS_END
void monty_state::monty(machine_config &config) void monty_state::monty(machine_config &config)
{ {
// Basic machine hardware // Basic machine hardware
Z80(config, m_maincpu, 3.579545_MHz_XTAL); // Ceramic resonator labeled 3.58MT Z80(config, m_maincpu, 3.58_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &monty_state::monty_mem); m_maincpu->set_addrmap(AS_PROGRAM, &monty_state::monty_mem);
m_maincpu->set_addrmap(AS_IO, &monty_state::monty_io); m_maincpu->set_addrmap(AS_IO, &monty_state::monty_io);
m_maincpu->halt_cb().set(FUNC(monty_state::halt_changed)); m_maincpu->halt_cb().set(FUNC(monty_state::halt_changed));