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https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
f2mc16: First pass with working IRQs. [R. Belmont]
This commit is contained in:
arbee
parent
775b486c73
commit
5864e92aa5
@ -105,6 +105,12 @@ void f2mc16_device::device_reset()
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m_dpr = 0x01;
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m_dtb = 0;
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for (int &entry : m_vector_level)
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{
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entry = 7;
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}
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m_outstanding_irqs = 0;
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m_pc = read_16_vector(0xffffdc);
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m_pcb = read_8_vector(0xffffde);
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@ -205,12 +211,23 @@ void f2mc16_device::execute_run()
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{
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while (m_icount > 0)
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{
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if (m_outstanding_irqs)
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{
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int cpulevel = m_ps >> 13;
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for (int irq = 0; irq < 256; irq++)
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{
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if (m_vector_level[irq] < cpulevel)
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{
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take_irq(irq, m_vector_level[irq]);
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break;
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}
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}
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}
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u8 opcode = read_8((m_pcb<<16) | m_pc);
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debugger_instruction_hook((m_pcb<<16) | m_pc);
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// m_icount--;
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switch (opcode)
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{
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case 0x00: // NOP
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@ -322,8 +339,39 @@ void f2mc16_device::execute_run()
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m_icount -= 2;
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break;
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// ASRW A
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case 0x0e:
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// stream << "ASRW A";
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m_tmp16 = m_acc & 0xffff;
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// T is set if either carry or T are set beforehand
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if ((m_ps & F_C) || (m_ps & F_T))
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{
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m_ps |= F_T;
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}
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// C becomes the previous LSB
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m_ps &= ~F_C;
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if (m_tmp16 & 1)
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{
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m_ps |= F_C;
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}
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if (m_tmp16 & 0x8000)
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{
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m_tmp16 >>= 1;
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m_tmp16 |= 0x8000;
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}
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else
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{
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m_tmp16 >>= 1;
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m_tmp16 &= ~0x8000;
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}
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setNZ_16(m_tmp16);
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m_acc &= 0xffff0000;
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m_acc |= m_tmp16;
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m_pc++;
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m_icount -= 2;
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break;
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// LSRW A
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@ -633,8 +681,13 @@ void f2mc16_device::execute_run()
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m_icount -= 2;
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break;
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// NOT A
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case 0x37:
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// stream << "NOT A";
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m_acc ^= 0xff;
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setNZ_8(m_acc & 0xff);
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m_ps &= ~F_V;
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m_pc++;
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m_icount -= 2;
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break;
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// ADDW A, #imm16
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@ -697,8 +750,13 @@ void f2mc16_device::execute_run()
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m_icount -= 2;
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break;
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// NOTW A
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case 0x3f:
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// stream << "NOTW A";
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m_acc ^= 0xffff;
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setNZ_16(m_acc & 0xffff);
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m_ps &= ~F_V;
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m_pc++;
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m_icount -= 2;
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break;
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// MOV A, dir
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@ -1004,8 +1062,44 @@ void f2mc16_device::execute_run()
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// stream << "RET";
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break;
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// RETI
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case 0x6b:
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// stream << "RETI";
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// there's an IRQ chaining facility, let's do it
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if (m_outstanding_irqs)
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{
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int cpulevel = m_ps >> 13;
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for (int irq = 0; irq < 256; irq++)
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{
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if (m_vector_level[irq] < cpulevel)
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{
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m_ps = read_16((m_ssb << 16) | m_ssp);
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m_ps |= F_S;
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m_ps &= ~0x7000;
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m_ps |= (m_vector_level[irq] & 7) << 13;
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u32 uVecAddr = 0xfffffc - (irq * 4);
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m_pc = read_16(uVecAddr);
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m_pcb = read_8(uVecAddr + 2);
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break;
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}
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}
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}
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else
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{
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m_ps = pull_16_ssp();
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m_pc = pull_16_ssp();
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m_tmp16 = pull_16_ssp();
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m_pcb = m_tmp16 & 0xff;
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m_dtb = m_tmp16 >> 8;
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m_tmp16 = pull_16_ssp();
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m_adb = m_tmp16 & 0xff;
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m_dpr = m_tmp16 >> 8;
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m_acc = 0;
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m_acc = pull_16_ssp();
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m_acc |= (pull_16_ssp() << 16);
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m_icount -= 17;
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}
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break;
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case 0x6c: // bit operation instructions
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@ -2111,10 +2205,9 @@ void f2mc16_device::opcodes_ea76(u8 operand)
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m_icount -= 10;
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break;
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// ORW A, @RWx
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// ORW A, RWx
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case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
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m_tmp16 = read_rwX(operand & 7);
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m_tmp16 = read_16(getRWbank(operand & 7, m_tmp16));
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m_acc |= m_tmp16;
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setNZ_16(m_acc & 0xffff);
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m_ps &= ~F_V;
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@ -2169,3 +2262,38 @@ void f2mc16_device::opcodes_ea78(u8 operand)
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void f2mc16_device::execute_set_input(int inputnum, int state)
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{
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}
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void f2mc16_device::set_irq(int vector, int level)
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{
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m_outstanding_irqs++;
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m_vector_level[vector] = level;
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//printf("set_irq: vec %d level %d\n", vector, level);
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}
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void f2mc16_device::clear_irq(int vector)
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{
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m_outstanding_irqs--;
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m_vector_level[vector] = 7;
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//printf("clear_irq: vec %d\n", vector);
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}
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// note: this function must not use m_tmp16 unless you change RETI
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void f2mc16_device::take_irq(int vector, int level)
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{
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//printf("take_irq: vector %d, level %d, old PC = %02x%04x\n", vector, level, m_pcb, m_pc);
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push_16_ssp(m_acc>>16);
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push_16_ssp(m_acc & 0xffff);
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push_16_ssp((m_dpr<<8) | m_adb);
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push_16_ssp((m_dtb<<8) | m_pcb);
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push_16_ssp(m_pc);
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push_16_ssp(m_ps);
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m_ps |= F_S;
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m_ps &= ~0x7000;
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m_ps |= (level & 7) << 13;
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u32 uVecAddr = 0xfffffc - (vector * 4);
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m_pc = read_16(uVecAddr);
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m_pcb = read_8(uVecAddr + 2);
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//printf("New PC = %02x%04x\n", m_pcb, m_pc);
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}
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@ -14,6 +14,8 @@
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class f2mc16_device : public cpu_device
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{
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public:
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friend class mb9061x_device;
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enum
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{
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F2MC16_PC, F2MC16_PS, F2MC16_USP, F2MC16_SSP, F2MC16_ACC,
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@ -223,6 +225,12 @@ private:
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}
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}
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inline void push_16_ssp(u16 val)
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{
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m_ssp-=2;
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write_16((m_ssb << 16) | m_ssp, val);
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}
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inline void push_32(u32 val)
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{
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if (m_ps & F_S)
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@ -271,6 +279,14 @@ private:
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return rv;
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}
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inline u16 pull_16_ssp()
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{
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u16 rv = read_16((m_ssb << 16) | m_ssp);
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m_ssp += 2;
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return rv;
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}
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inline u32 pull_32()
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{
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u32 rv = 0;
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@ -431,6 +447,13 @@ private:
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void opcodes_ea76(u8 operand);
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void opcodes_ea77(u8 operand);
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void opcodes_ea78(u8 operand);
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void set_irq(int vector, int level);
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void clear_irq(int vector);
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void take_irq(int vector, int level);
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int m_vector_level[256];
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int m_outstanding_irqs;
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};
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DECLARE_DEVICE_TYPE(F2MC16, f2mc16_device)
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@ -1192,7 +1192,7 @@ offs_t f2mc16_disassembler::disassemble(std::ostream &stream, offs_t pc, const d
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break;
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case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
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util::stream_format(stream, "ORW A, @RW%d", (operand & 0x1));
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util::stream_format(stream, "ORW A, RW%d", (operand & 0x1));
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bytes = 2;
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break;
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@ -39,6 +39,9 @@ mb9061x_device::mb9061x_device(const machine_config &mconfig, device_type type,
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void mb9061x_device::device_start()
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{
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f2mc16_device::device_start();
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m_tbtc_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(mb9061x_device::tbtc_tick), this));
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m_tbtc_timer->adjust(attotime::never);
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}
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@ -65,6 +68,8 @@ void mb9061x_device::execute_set_input(int inputnum, int state)
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/* MB90610 - "Evaluation device" with extra RAM */
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void mb90610_device::mb90610_map(address_map &map)
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{
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map(0x00a9, 0x00a9).rw(FUNC(mb9061x_device::tbtc_r), FUNC(mb9061x_device::tbtc_w));
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map(0x00b0, 0x00bf).rw(FUNC(mb9061x_device::intc_r), FUNC(mb9061x_device::intc_w));
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map(0x0100, 0x10ff).ram(); // 4K of internal RAM from 0x100 to 0x1100
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}
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@ -78,9 +83,107 @@ mb90610_device::mb90610_device(const machine_config &mconfig, device_type type,
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{
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}
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/* TBTC: timebase counter */
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enum
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{
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TBTC_TEST = 0x80, // test, must always write 1
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TBTC_TBIE = 0x10, // interrupt enable
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TBTC_TBOF = 0x08, // expire flag
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TBTC_TBR = 0x04, // write 0 to restart
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TBTC_TBC1 = 0x02, // rate select bit 1
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TBTC_TBC0 = 0x01 // rate select bit 0
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};
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READ8_MEMBER(mb9061x_device::tbtc_r)
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{
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return m_tbtc;
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}
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WRITE8_MEMBER(mb9061x_device::tbtc_w)
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{
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static const float periods[4] = { 1.024, 4.096, 16.384, 131.072 };
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//printf("%02x to TBTC\n", data);
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if ((!(data & TBTC_TBR)) || ((data & (TBTC_TBC1|TBTC_TBC0)) != (m_tbtc & (TBTC_TBC1|TBTC_TBC0))))
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{
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m_tbtc_timer->adjust(attotime(0, ATTOSECONDS_IN_MSEC(periods[data & (TBTC_TBC1|TBTC_TBC0)])));
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if (!(data & TBTC_TBR))
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{
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intc_clear_irq(11, 0x22);
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}
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}
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if (!(data & TBTC_TBOF) && (m_tbtc & TBTC_TBOF))
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{
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intc_clear_irq(11, 0x22);
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}
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m_tbtc = data;
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}
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/* INTC: Interrupt controller */
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TIMER_CALLBACK_MEMBER(mb9061x_device::tbtc_tick)
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{
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//printf("TBTC tick\n");
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m_tbtc_timer->adjust(attotime::never);
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m_tbtc |= TBTC_TBOF;
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if (m_tbtc & TBTC_TBIE)
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{
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intc_trigger_irq(11, 0x22);
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}
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}
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READ8_MEMBER(mb9061x_device::intc_r)
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{
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return m_intc[offset];
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}
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WRITE8_MEMBER(mb9061x_device::intc_w)
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{
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//printf("INTC ICR %d to %02x\n", offset, data);
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m_intc[offset] = data;
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}
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void mb9061x_device::intc_trigger_irq(int icr, int vector)
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{
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int level = m_intc[icr] & 7;
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//printf("trigger_irq: ICR %d, level %d\n", icr, level);
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// Extended Intelligent I/O Service?
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if (m_intc[icr] & 8)
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{
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fatalerror("MB9061X: ICR %d (vector %x) calls for EI2OS, not implemented\n", icr, vector);
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}
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else
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{
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if (level != 7)
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{
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set_irq(vector, level);
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}
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}
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}
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void mb9061x_device::intc_clear_irq(int icr, int vector)
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{
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int level = m_intc[icr] & 7;
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// Make sure this isn't the Extended Intelligent I/O Service
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if (!(m_intc[icr] & 8))
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{
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if (level != 7)
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{
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clear_irq(vector);
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}
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}
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}
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/* MB90611 - Production version of this series */
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void mb90611_device::mb90611_map(address_map &map)
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{
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map(0x00a9, 0x00a9).rw(FUNC(mb9061x_device::tbtc_r), FUNC(mb9061x_device::tbtc_w));
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map(0x00b0, 0x00bf).rw(FUNC(mb9061x_device::intc_r), FUNC(mb9061x_device::intc_w));
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map(0x0100, 0x04ff).ram(); // 1K of internal RAM from 0x100 to 0x500
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}
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@ -25,6 +25,12 @@ class mb9061x_device : public f2mc16_device
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public:
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const address_space_config m_program_config;
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// interrupts handled by the interrupt controller
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enum
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{
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ICR0 = 0, ICR1, ICR2, ICR3, ICR4, ICR5, ICR6, ICR7, ICR8, ICR9, ICR10, ICR11, ICR12, ICR13, ICR14, ICR15
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};
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protected:
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// construction/destruction
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mb9061x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor internal_map);
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@ -36,6 +42,21 @@ protected:
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virtual space_config_vector memory_space_config() const override;
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private:
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// TBC
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TIMER_CALLBACK_MEMBER(tbtc_tick);
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READ8_MEMBER(tbtc_r);
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WRITE8_MEMBER(tbtc_w);
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// INTC
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READ8_MEMBER(intc_r);
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WRITE8_MEMBER(intc_w);
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void intc_trigger_irq(int icr, int vector);
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void intc_clear_irq(int icr, int vector);
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u8 m_tbtc;
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emu_timer *m_tbtc_timer;
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u8 m_intc[0x10];
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};
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class mb90610_device : public mb9061x_device
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