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https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
next: fix the vblank disables [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
1a442c0a84
commit
59e7d9a63b
@ -277,7 +277,7 @@ const char *next_state::dma_targets[0x20] = {
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const int next_state::dma_irqs[0x20] = {
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-1, 26, -1, -1, 23, 25, -1, -1, 22, 24, -1, -1, 21, 20, -1, -1,
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-1, 28, -1, -1, -1, 27, -1, -1, -2, -1, -1, -1, 18, 19, -1, -1
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-1, 28, -1, -1, -1, 27, -1, -1, 5, -1, -1, -1, 18, 19, -1, -1
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};
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const bool next_state::dma_has_saved[0x20] = {
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@ -528,7 +528,7 @@ void next_state::dma_do_ctrl_w(int slot, UINT8 data)
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{
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const char *name = dma_name(slot);
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#if 0
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fprintf(stderr, "dma_ctrl_w %s %02x (%08x)\n", name, data, maincpu->safe_pc());
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fprintf(stderr, "dma_ctrl_w %s %02x (%08x)\n", name, data, maincpu->pc());
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fprintf(stderr, " ->%s%s%s%s%s%s%s\n",
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data & DMA_SETENABLE ? " enable" : "",
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@ -803,6 +803,35 @@ WRITE_LINE_MEMBER(next_state::scsi_drq)
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dma_drq_w(1, state);
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}
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WRITE8_MEMBER(next_state::ramdac_w)
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{
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switch(offset) {
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case 0:
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switch(data) {
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case 0x05:
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if(screen_color)
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irq_set(13, false);
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else
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irq_set(5, false);
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vbl_enabled = false;
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break;
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case 0x06:
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vbl_enabled = true;
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break;
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default:
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fprintf(stderr, "ramdac_w %d, %02x\n", offset, data);
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break;
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}
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break;
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default:
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fprintf(stderr, "ramdac_w %d, %02x\n", offset, data);
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break;
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}
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}
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void next_state::setup(UINT32 _scr1, int size_x, int size_y, int skip, bool color)
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{
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scr1 = _scr1;
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@ -863,17 +892,18 @@ void next_state::machine_reset()
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timer_data = 0;
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timer_next_data = 0;
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timer_ctrl = 0;
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vbl_enabled = true;
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dma_drq_w(4, true); // soundout
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}
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void next_state::vblank_w(screen_device &screen, bool vblank_state)
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{
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#if 1
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if(vbl_enabled) {
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if(screen_color)
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irq_set(13, vblank_state);
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else
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irq_set(5, vblank_state);
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#endif
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}
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}
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static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state )
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@ -900,8 +930,6 @@ static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x02016004, 0x02016007) AM_MIRROR(0x300000) AM_READWRITE(timer_ctrl_r, timer_ctrl_w)
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AM_RANGE(0x02018000, 0x02018003) AM_MIRROR(0x300000) AM_DEVREADWRITE8("scc", scc8530_t, reg_r, reg_w, 0xffffffff)
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// AM_RANGE(0x02018004, 0x02018007) AM_MIRROR(0x300000) SCC CLK
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// AM_RANGE(0x02018100, 0x02018103) AM_MIRROR(0x300000) Color RAMDAC
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// AM_RANGE(0x02018104, 0x02018107) AM_MIRROR(0x300000) Color CSR
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// AM_RANGE(0x02018190, 0x02018197) AM_MIRROR(0x300000) warp 9c DRAM timing
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// AM_RANGE(0x02018198, 0x0201819f) AM_MIRROR(0x300000) warp 9c VRAM timing
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AM_RANGE(0x0201a000, 0x0201a003) AM_MIRROR(0x300000) AM_READ(event_counter_r) // EVENTC
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@ -918,7 +946,7 @@ static ADDRESS_MAP_START( next_mem, AS_PROGRAM, 32, next_state )
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// AM_RANGE(0x1c000000, 0x1c03ffff) main RAM w AB function
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( next_0b_nofdc_mem, AS_PROGRAM, 32, next_state )
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static ADDRESS_MAP_START( next_0b_m_nofdc_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram")
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AM_IMPORT_FROM(next_mem)
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@ -931,20 +959,28 @@ static ADDRESS_MAP_START( next_fdc_mem, AS_PROGRAM, 32, next_state )
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AM_IMPORT_FROM(next_mem)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( next_0b_mem, AS_PROGRAM, 32, next_state )
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static ADDRESS_MAP_START( next_0b_m_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x0b000000, 0x0b03ffff) AM_RAM AM_SHARE("vram")
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AM_IMPORT_FROM(next_fdc_mem)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( next_0c_mem, AS_PROGRAM, 32, next_state )
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static ADDRESS_MAP_START( next_0c_m_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_SHARE("vram")
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AM_IMPORT_FROM(next_fdc_mem)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( next_2c_mem, AS_PROGRAM, 32, next_state )
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static ADDRESS_MAP_START( next_0c_c_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x0c000000, 0x0c1fffff) AM_RAM AM_SHARE("vram")
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AM_RANGE(0x02018180, 0x02018183) AM_MIRROR(0x300000) AM_WRITE8(ramdac_w, 0xffffffff)
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AM_IMPORT_FROM(next_fdc_mem)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( next_2c_c_mem, AS_PROGRAM, 32, next_state )
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AM_RANGE(0x2c000000, 0x2c1fffff) AM_RAM AM_SHARE("vram")
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AM_RANGE(0x02018180, 0x02018183) AM_MIRROR(0x300000) AM_WRITE8(ramdac_w, 0xffffffff)
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AM_IMPORT_FROM(next_fdc_mem)
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ADDRESS_MAP_END
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@ -1017,7 +1053,7 @@ MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( next, next_base )
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MCFG_CPU_ADD("maincpu", M68030, XTAL_25MHz)
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MCFG_CPU_PROGRAM_MAP(next_0b_nofdc_mem)
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MCFG_CPU_PROGRAM_MAP(next_0b_m_nofdc_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( next_fdc_base, next_base )
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@ -1032,39 +1068,39 @@ MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nexts, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz)
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MCFG_CPU_PROGRAM_MAP(next_0b_mem)
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MCFG_CPU_PROGRAM_MAP(next_0b_m_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nexts2, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz)
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MCFG_CPU_PROGRAM_MAP(next_0b_mem)
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MCFG_CPU_PROGRAM_MAP(next_0b_m_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nextsc, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_25MHz)
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MCFG_CPU_PROGRAM_MAP(next_2c_mem)
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MCFG_CPU_PROGRAM_MAP(next_2c_c_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nextst, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz)
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MCFG_CPU_PROGRAM_MAP(next_0b_mem)
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MCFG_CPU_PROGRAM_MAP(next_0b_m_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nextstc, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz)
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MCFG_CPU_PROGRAM_MAP(next_0c_mem)
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MCFG_CPU_PROGRAM_MAP(next_0c_c_mem)
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MCFG_SCREEN_MODIFY("screen")
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MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nextct, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz)
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MCFG_CPU_PROGRAM_MAP(next_0c_mem)
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MCFG_CPU_PROGRAM_MAP(next_0c_m_mem)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( nextctc, next_fdc_base )
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MCFG_CPU_ADD("maincpu", M68040, XTAL_33MHz)
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MCFG_CPU_PROGRAM_MAP(next_0c_mem)
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MCFG_CPU_PROGRAM_MAP(next_0c_c_mem)
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MCFG_SCREEN_MODIFY("screen")
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MCFG_SCREEN_VISIBLE_AREA(0, 832-1, 0, 624-1)
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MACHINE_CONFIG_END
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@ -75,6 +75,7 @@ public:
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DECLARE_WRITE32_MEMBER( timer_data_w );
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DECLARE_READ32_MEMBER( timer_ctrl_r );
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DECLARE_WRITE32_MEMBER( timer_ctrl_w );
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DECLARE_WRITE8_MEMBER( ramdac_w );
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UINT32 scr1;
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UINT32 scr2;
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@ -152,6 +153,7 @@ protected:
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int screen_sx, screen_sy, screen_skip;
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bool screen_color;
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bool vbl_enabled;
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virtual void machine_start();
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virtual void machine_reset();
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@ -171,6 +173,7 @@ protected:
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void dma_check_end(int slot, bool eof);
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void dma_done(int slot);
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void dma_end(int slot);
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public:
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DECLARE_DRIVER_INIT(nexts2);
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DECLARE_DRIVER_INIT(next);
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