mirror of
https://github.com/holub/mame
synced 2025-04-18 22:49:58 +03:00
h8_sci: Disable logging by default & don't log debugger reads.
Only start sending data via DMA if transmitter is enabled. Clear TEND when sending data via DMA. TDRE, RDRF, ORER, PER and FER flags can be cleared to 0 only if they have first been read while set to 1. Only set TEND when there is no more data to send. Receiver is started only on high to low rxd in asynchronous mode, when receiving and sending in synchronous mode when data is sent, or continuously when receiving without sending in synchronous mode. Set rx status to idle when stopping clock in rx_async_step(). Remove double invert when calculating parity in rx_async_step(). Remove redundant check for synchronous mode in rx_async_step().
This commit is contained in:
smf-
parent
bae7420375
commit
5a25c8887a
@ -5,7 +5,6 @@
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#include "h8_sci.h"
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#include "h8.h"
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#include "h8_intc.h"
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#define LOG_REGS (1 << 1U) // Register writes
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#define LOG_RREGS (1 << 2U) // Register reads
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@ -15,8 +14,8 @@
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#define LOG_STATE (1 << 6U) // State machine states
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#define LOG_TICK (1 << 7U) // Clock ticks
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#define VERBOSE (LOG_DATA)
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//#define VERBOSE (LOG_DATA)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(H8_SCI, h8_sci_device, "h8_sci", "H8 Serial Communications Interface")
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@ -70,7 +69,7 @@ h8_sci_device::h8_sci_device(const machine_config &mconfig, const char *tag, dev
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m_external_to_internal_ratio(0), m_internal_to_external_ratio(0), m_sync_timer(nullptr), m_id(0), m_eri_int(0), m_rxi_int(0), m_txi_int(0), m_tei_int(0),
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m_tx_state(0), m_rx_state(0), m_tx_bit(0), m_rx_bit(0), m_clock_state(0), m_tx_parity(0), m_rx_parity(0), m_tx_clock_counter(0), m_rx_clock_counter(0),
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m_clock_mode(INTERNAL_ASYNC), m_ext_clock_value(false), m_rx_value(true),
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m_rdr(0), m_tdr(0), m_smr(0), m_scr(0), m_ssr(0), m_brr(0), m_rsr(0), m_tsr(0), m_clock_event(0), m_divider(0)
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m_rdr(0), m_tdr(0), m_smr(0), m_scr(0), m_ssr(0), m_ssr_read(0), m_brr(0), m_rsr(0), m_tsr(0), m_clock_event(0), m_divider(0)
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{
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m_external_clock_period = attotime::never;
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}
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@ -94,11 +93,14 @@ void h8_sci_device::smr_w(u8 data)
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m_cpu->pc());
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clock_update();
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sync_rx_start();
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}
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u8 h8_sci_device::smr_r()
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{
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LOGMASKED(LOG_RREGS, "smr_r %02x (%06x)\n", m_smr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "smr_r %02x (%06x)\n", m_smr, m_cpu->pc());
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return m_smr;
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}
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@ -111,13 +113,15 @@ void h8_sci_device::brr_w(u8 data)
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u8 h8_sci_device::brr_r()
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{
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LOGMASKED(LOG_RREGS, "brr_r %02x (%06x)\n", m_brr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "brr_r %02x (%06x)\n", m_brr, m_cpu->pc());
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return m_brr;
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}
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bool h8_sci_device::is_sync_start() const
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void h8_sci_device::sync_rx_start()
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{
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return (m_smr & SMR_CA) && ((m_scr & (SCR_TE|SCR_RE)) == (SCR_TE|SCR_RE));
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if (m_rx_state == ST_IDLE && (m_smr & SMR_CA) && (m_scr & SCR_RE) && !(m_scr & SCR_TE) && !has_recv_error())
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rx_start();
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}
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bool h8_sci_device::has_recv_error() const
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@ -146,8 +150,8 @@ void h8_sci_device::scr_w(u8 data)
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clock_stop(CLK_RX);
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}
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if((delta & SCR_RE) && (m_scr & SCR_RE) && m_rx_state == ST_IDLE && !has_recv_error() && !is_sync_start())
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rx_start();
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if((delta & (SCR_RE | SCR_TE)))
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sync_rx_start();
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if((delta & SCR_TIE) && (m_scr & SCR_TIE) && (m_ssr & SSR_TDRE))
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m_intc->internal_interrupt(m_txi_int);
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if((delta & SCR_TEIE) && (m_scr & SCR_TEIE) && (m_ssr & SSR_TEND))
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@ -160,7 +164,8 @@ void h8_sci_device::scr_w(u8 data)
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u8 h8_sci_device::scr_r()
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{
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LOGMASKED(LOG_RREGS, "scr_r %02x (%06x)\n", m_scr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "scr_r %02x (%06x)\n", m_scr, m_cpu->pc());
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return m_scr;
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}
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@ -168,8 +173,8 @@ void h8_sci_device::tdr_w(u8 data)
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{
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LOGMASKED(LOG_REGS, "tdr_w %02x (%06x)\n", data, m_cpu->pc());
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m_tdr = data;
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if(m_cpu->access_is_dma()) {
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m_ssr &= ~SSR_TDRE;
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if ((m_cpu->access_is_dma()) && (m_scr & SCR_TE)) {
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m_ssr &= ~(SSR_TDRE | SSR_TEND);
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if(m_tx_state == ST_IDLE)
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tx_start();
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}
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@ -177,37 +182,38 @@ void h8_sci_device::tdr_w(u8 data)
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u8 h8_sci_device::tdr_r()
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{
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LOGMASKED(LOG_RREGS, "tdr_r %02x (%06x)\n", m_tdr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "tdr_r %02x (%06x)\n", m_tdr, m_cpu->pc());
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return m_tdr;
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}
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void h8_sci_device::ssr_w(u8 data)
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{
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if(!(m_scr & SCR_TE)) {
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data |= SSR_TDRE;
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m_ssr |= SSR_TDRE;
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}
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if((m_ssr & SSR_TDRE) && !(data & SSR_TDRE))
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m_ssr &= ~SSR_TEND;
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m_ssr = ((m_ssr & ~SSR_MPBT) | (data & SSR_MPBT)) & (data | (SSR_TEND|SSR_MPB|SSR_MPBT));
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if ((m_scr & SCR_TE) && (m_ssr & m_ssr_read & SSR_TDRE) && !(data & SSR_TDRE))
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m_ssr &= ~(SSR_TDRE | SSR_TEND);
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m_ssr = (m_ssr & (~m_ssr_read | data | SSR_TDRE | SSR_TEND | SSR_MPB) & ~SSR_MPBT) | (data & SSR_MPBT);
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LOGMASKED(LOG_REGS, "ssr_w %02x -> %02x (%06x)\n", data, m_ssr, m_cpu->pc());
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if(m_tx_state == ST_IDLE && !(m_ssr & SSR_TDRE))
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tx_start();
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if((m_scr & SCR_RE) && m_rx_state == ST_IDLE && !has_recv_error() && !is_sync_start())
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rx_start();
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sync_rx_start();
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}
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u8 h8_sci_device::ssr_r()
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{
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LOGMASKED(LOG_RREGS, "ssr_r %02x (%06x)\n", m_ssr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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{
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LOGMASKED(LOG_RREGS, "ssr_r %02x (%06x)\n", m_ssr, m_cpu->pc());
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m_ssr_read = m_ssr;
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}
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return m_ssr;
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}
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u8 h8_sci_device::rdr_r()
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{
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LOGMASKED(LOG_RREGS, "rdr_r %02x (%06x)\n", m_rdr, m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "rdr_r %02x (%06x)\n", m_rdr, m_cpu->pc());
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if(!machine().side_effects_disabled() && m_cpu->access_is_dma())
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m_ssr &= ~SSR_RDRF;
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@ -221,7 +227,8 @@ void h8_sci_device::scmr_w(u8 data)
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u8 h8_sci_device::scmr_r()
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{
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LOGMASKED(LOG_RREGS, "scmr_r (%06x)\n", m_cpu->pc());
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if (!machine().side_effects_disabled())
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LOGMASKED(LOG_RREGS, "scmr_r (%06x)\n", m_cpu->pc());
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return 0x00;
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}
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@ -360,9 +367,10 @@ void h8_sci_device::do_rx_w(int state)
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if(m_rx_clock_counter == 1 || m_rx_clock_counter == 15)
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m_rx_clock_counter = 0;
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if(m_rx_state == ST_IDLE && !(m_smr & SMR_CA) && (m_scr & SCR_RE) && m_rx_value && !state)
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rx_start();
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m_rx_value = state;
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if(!m_rx_value && !(m_clock_state & CLK_RX) && m_rx_state != ST_IDLE)
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clock_start(CLK_RX);
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}
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void h8_sci_device::do_clk_w(int state)
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@ -507,7 +515,7 @@ void h8_sci_device::tx_start()
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m_tx_bit = 1;
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}
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clock_start(CLK_TX);
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if(m_rx_state == ST_IDLE && !has_recv_error() && is_sync_start())
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if(m_rx_state == ST_IDLE && (m_smr & SMR_CA) && (m_scr & SCR_TE) && (m_scr & SCR_RE) && !has_recv_error())
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rx_start();
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}
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@ -584,13 +592,14 @@ void h8_sci_device::tx_async_step()
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m_tx_bit = 0;
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clock_stop(CLK_TX);
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m_cpu->do_sci_tx(m_id, 1);
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m_ssr |= SSR_TEND;
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if(m_scr & SCR_TEIE)
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m_intc->internal_interrupt(m_tei_int);
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// if there's more to send, start the transmitter
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if((m_scr & SCR_TE) && !(m_ssr & SSR_TDRE))
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tx_start();
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else
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m_ssr |= SSR_TEND;
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break;
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default:
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@ -620,13 +629,14 @@ void h8_sci_device::tx_sync_step()
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m_tx_state = ST_IDLE;
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clock_stop(CLK_TX);
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m_cpu->do_sci_tx(m_id, 1);
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m_ssr |= SSR_TEND;
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if(m_scr & SCR_TEIE)
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m_intc->internal_interrupt(m_tei_int);
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// if there's more to send, start the transmitter
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if((m_scr & SCR_TE) && !(m_ssr & SSR_TDRE))
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tx_start();
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else
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m_ssr |= SSR_TEND;
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} else {
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m_cpu->do_sci_tx(m_id, m_tsr & 1);
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m_tsr >>= 1;
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@ -642,13 +652,11 @@ void h8_sci_device::rx_start()
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if(m_smr & SMR_CA) {
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m_rx_state = ST_BIT;
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m_rx_bit = 8;
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clock_start(CLK_RX);
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} else {
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m_rx_state = ST_START;
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m_rx_bit = 1;
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if(!m_rx_value)
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clock_start(CLK_RX);
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}
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clock_start(CLK_RX);
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}
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void h8_sci_device::rx_done()
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@ -672,12 +680,11 @@ void h8_sci_device::rx_done()
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else
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m_intc->internal_interrupt(m_rxi_int);
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}
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if((m_scr & SCR_RE) && !has_recv_error() && !is_sync_start())
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rx_start();
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else {
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clock_stop(CLK_RX);
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m_rx_state = ST_IDLE;
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}
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m_rx_state = ST_IDLE;
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clock_stop(CLK_RX);
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sync_rx_start();
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}
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void h8_sci_device::rx_async_tick()
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@ -694,6 +701,7 @@ void h8_sci_device::rx_async_step()
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switch(m_rx_state) {
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case ST_START:
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if(m_rx_value) {
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m_rx_state = ST_IDLE;
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clock_stop(CLK_RX);
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break;
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}
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@ -702,7 +710,6 @@ void h8_sci_device::rx_async_step()
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break;
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case ST_BIT:
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m_rx_parity ^= m_rx_value;
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m_rsr >>= 1;
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if(m_rx_value) {
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m_rx_parity = !m_rx_parity;
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@ -710,9 +717,7 @@ void h8_sci_device::rx_async_step()
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}
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m_rx_bit--;
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if(!m_rx_bit) {
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if(m_smr & SMR_CA)
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rx_done();
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else if(m_smr & SMR_PE) {
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if(m_smr & SMR_PE) {
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m_rx_state = ST_PARITY;
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m_rx_bit = 1;
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} else {
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@ -14,8 +14,9 @@
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#pragma once
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#include "h8_intc.h"
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class h8_device;
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class h8_intc_device;
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class h8_sci_device : public device_t {
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public:
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@ -117,7 +118,7 @@ protected:
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u32 m_clock_mode;
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bool m_ext_clock_value, m_rx_value;
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u8 m_rdr, m_tdr, m_smr, m_scr, m_ssr, m_brr, m_rsr, m_tsr;
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u8 m_rdr, m_tdr, m_smr, m_scr, m_ssr, m_ssr_read, m_brr, m_rsr, m_tsr;
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u64 m_clock_event, m_clock_step, m_divider;
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std::string m_last_clock_message;
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@ -144,7 +145,7 @@ protected:
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void rx_sync_tick();
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void rx_sync_step();
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bool is_sync_start() const;
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void sync_rx_start();
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bool has_recv_error() const;
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};
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