From 5c880f47f18f453a279350b9cd3f171d04b79ba6 Mon Sep 17 00:00:00 2001
From: yz70s <yz70s@users.noreply.github.com>
Date: Mon, 19 Oct 2015 21:55:49 +0200
Subject: [PATCH] idectrl/atahle.c: call routine fill_buffer using a timer to
 avoid reentering read_data and losing data with ultra dma (nw) Also small
 comment changes.

---
 src/devices/machine/atahle.c  | 8 +++++++-
 src/devices/machine/atahle.h  | 6 +++++-
 src/devices/machine/idectrl.c | 8 ++++----
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/devices/machine/atahle.c b/src/devices/machine/atahle.c
index c5351994ea2..850ab39d34f 100644
--- a/src/devices/machine/atahle.c
+++ b/src/devices/machine/atahle.c
@@ -110,6 +110,7 @@ void ata_hle_device::device_start()
 	save_item(NAME(m_identify_buffer));
 
 	m_busy_timer = timer_alloc(TID_BUSY);
+	m_buffer_empty_timer = timer_alloc(TID_BUFFER_EMPTY);
 }
 
 void ata_hle_device::device_reset()
@@ -158,6 +159,10 @@ void ata_hle_device::device_timer(emu_timer &timer, device_timer_id id, int para
 
 		finished_busy(param);
 		break;
+	case TID_BUFFER_EMPTY:
+		m_buffer_empty_timer->enable(false);
+		fill_buffer();
+		break;
 	}
 }
 
@@ -465,7 +470,8 @@ void ata_hle_device::read_buffer_empty()
 	if ((multi_word_dma_mode() >= 0) || (ultra_dma_mode() >= 0))
 		set_dmarq(CLEAR_LINE);
 
-	fill_buffer();
+	m_buffer_empty_timer->enable(true);
+	m_buffer_empty_timer->adjust(attotime::zero);
 }
 
 void ata_hle_device::write_buffer_full()
diff --git a/src/devices/machine/atahle.h b/src/devices/machine/atahle.h
index 30236e62d49..cd1d921fc37 100644
--- a/src/devices/machine/atahle.h
+++ b/src/devices/machine/atahle.h
@@ -34,6 +34,8 @@ public:
 	virtual DECLARE_WRITE_LINE_MEMBER(write_dmack);
 	virtual DECLARE_WRITE_LINE_MEMBER(write_pdiag);
 
+	TIMER_CALLBACK_MEMBER(buffer_empty_timer_work);
+
 protected:
 	virtual void device_start();
 	virtual void device_reset();
@@ -160,7 +162,8 @@ protected:
 
 	enum
 	{
-		TID_BUSY
+		TID_BUSY,
+		TID_BUFFER_EMPTY
 	};
 
 	enum
@@ -213,6 +216,7 @@ private:
 	bool m_resetting;
 
 	emu_timer *m_busy_timer;
+	emu_timer *m_buffer_empty_timer;
 };
 
 #endif
diff --git a/src/devices/machine/idectrl.c b/src/devices/machine/idectrl.c
index d1f81a12426..bebfcc09d0d 100644
--- a/src/devices/machine/idectrl.c
+++ b/src/devices/machine/idectrl.c
@@ -274,11 +274,11 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
 	case 0:
 		if( ACCESSING_BITS_0_7 )
 		{
-			/* command register */
+			/* Bus Master IDE Command register */
 			UINT8 old = m_bus_master_command;
 			UINT8 val = data & 0xff;
 
-			/* save the read/write bit and the start/stop bit */
+			/* save the "Read or Write Control" bit 3 and the "Start/Stop Bus Master" bit 0 */
 			m_bus_master_command = (old & 0xf6) | (val & 0x09);
 
 			if ((old ^ m_bus_master_command) & 1)
@@ -306,7 +306,7 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
 
 		if( ACCESSING_BITS_16_23 )
 		{
-			/* status register */
+			/* Bus Master IDE Status register */
 			UINT8 old = m_bus_master_status;
 			UINT8 val = data >> 16;
 
@@ -334,7 +334,7 @@ void bus_master_ide_controller_device::execute_dma()
 
 	while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
 	{
-		/* if we're out of space, grab the next descriptor */
+		/* if we're out of space, grab the next Physical Region Descriptor */
 		if (m_dma_bytes_left == 0)
 		{
 			/* fetch the address */