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https://github.com/holub/mame
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Hooked up Xain d'Sleena/Solar Warrior 68705 MCU [Phil Bennett, Dr. Decapitator]
This commit is contained in:
Phil Bennett
parent
f1c2bdd3f3
commit
5cc13fbf66
@ -135,10 +135,6 @@ Updates by Bryan McPhail, 12/12/2004:
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exactly synchronised in practice. This is currently hacked in MAME
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by raising the VBLANK bit a scanline early.
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TODO:
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- 68705 microcontroller not dumped, patched out.
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***************************************************************************/
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#include "emu.h"
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@ -149,7 +145,7 @@ TODO:
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#define MASTER_CLOCK XTAL_12MHz
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#define CPU_CLOCK MASTER_CLOCK / 8
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#define MCU_CLOCK MASTER_CLOCK / 4
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#define PIXEL_CLOCK MASTER_CLOCK / 2
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#define PIXEL_CLOCK MASTER_CLOCK / 2
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static int vblank;
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@ -166,6 +162,14 @@ WRITE8_HANDLER( xain_flipscreen_w );
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extern UINT8 *xain_charram, *xain_bgram0, *xain_bgram1, xain_pri;
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/* MCU */
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static int from_main;
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static int from_mcu;
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static UINT8 ddr_a, ddr_b, ddr_c;
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static UINT8 port_a_out, port_b_out, port_c_out;
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static UINT8 port_a_in, port_b_in, port_c_in;
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static int _mcu_ready;
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static int _mcu_accept;
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/*
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Based on the Solar Warrior schematics, vertical timing counts as follows:
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@ -275,13 +279,17 @@ static WRITE8_HANDLER( xain_irqB_clear_w )
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static READ8_HANDLER( xain_68705_r )
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{
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// logerror("read 68705\n");
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return 0x4d; /* fake P5 checksum test pass */
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_mcu_ready = 1;
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return from_mcu;
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}
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static WRITE8_HANDLER( xain_68705_w )
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{
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// logerror("write %02x to 68705\n",data);
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from_main = data;
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_mcu_accept = 0;
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if (devtag_get_device(space->machine, "mcu") != NULL)
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cputag_set_input_line(space->machine, "mcu", 0, ASSERT_LINE);
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}
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static CUSTOM_INPUT( xain_vblank_r )
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@ -290,6 +298,113 @@ static CUSTOM_INPUT( xain_vblank_r )
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}
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/***************************************************************************
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MC68705P5 I/O
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***************************************************************************/
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READ8_HANDLER( xain_68705_port_a_r )
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{
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return (port_a_out & ddr_a) | (port_a_in & ~ddr_a);
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}
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WRITE8_HANDLER( xain_68705_port_a_w )
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{
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port_a_out = data;
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}
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WRITE8_HANDLER( xain_68705_ddr_a_w )
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{
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ddr_a = data;
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}
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READ8_HANDLER( xain_68705_port_b_r )
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{
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return (port_b_out & ddr_b) | (port_b_in & ~ddr_b);
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}
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WRITE8_HANDLER( xain_68705_port_b_w )
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{
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if ((ddr_b & 0x02) && (~data & 0x02))
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{
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port_a_in = from_main;
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}
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/* Rising edge of PB1 */
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else if ((ddr_b & 0x02) && (~port_b_out & 0x02) && (data & 0x02))
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{
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_mcu_accept = 1;
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cputag_set_input_line(space->machine, "mcu", 0, CLEAR_LINE);
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}
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/* Rising edge of PB2 */
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if ((ddr_b & 0x04) && (~port_b_out & 0x04) && (data & 0x04))
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{
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_mcu_ready = 0;
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from_mcu = port_a_out;
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}
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port_b_out = data;
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}
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WRITE8_HANDLER( xain_68705_ddr_b_w )
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{
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ddr_b = data;
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}
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READ8_HANDLER( xain_68705_port_c_r )
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{
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port_c_in = 0;
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if (!_mcu_accept)
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port_c_in |= 0x01;
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if (_mcu_ready)
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port_c_in |= 0x02;
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return (port_c_out & ddr_c) | (port_c_in & ~ddr_c);
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}
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WRITE8_HANDLER( xain_68705_port_c_w )
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{
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port_c_out = data;
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}
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WRITE8_HANDLER( xain_68705_ddr_c_w )
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{
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ddr_c = data;
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}
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static CUSTOM_INPUT( mcu_status_r )
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{
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UINT8 res = 0;
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if (devtag_get_device(field->port->machine, "mcu") != NULL)
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{
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if (_mcu_ready == 1)
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res |= 0x01;
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if (_mcu_accept == 1)
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res |= 0x02;
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}
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else
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{
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return 3;
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}
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return res;
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}
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READ8_HANDLER( mcu_comm_reset_r )
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{
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_mcu_ready = 1;
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_mcu_accept = 1;
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if (devtag_get_device(space->machine, "mcu") != NULL)
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cputag_set_input_line(space->machine, "mcu", 0, CLEAR_LINE);
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return 0xff;
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}
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static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x0000, 0x1fff) AM_RAM AM_SHARE("share1")
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AM_RANGE(0x2000, 0x27ff) AM_RAM_WRITE(xain_charram_w) AM_BASE(&xain_charram)
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@ -302,15 +417,15 @@ static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x3a02, 0x3a02) AM_READ_PORT("DSW0")
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AM_RANGE(0x3a02, 0x3a03) AM_WRITE(xain_scrollyP1_w)
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AM_RANGE(0x3a03, 0x3a03) AM_READ_PORT("DSW1")
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AM_RANGE(0x3a04, 0x3a04) AM_READ(xain_68705_r) /* from the 68705 */
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AM_RANGE(0x3a04, 0x3a04) AM_READ(xain_68705_r)
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AM_RANGE(0x3a04, 0x3a05) AM_WRITE(xain_scrollxP0_w)
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AM_RANGE(0x3a05, 0x3a05) AM_READ_PORT("VBLANK")
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// AM_RANGE(0x3a06, 0x3a06) AM_READNOP /* ?? read (and discarded) on startup. Maybe reset the 68705 */
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AM_RANGE(0x3a06, 0x3a06) AM_READ(mcu_comm_reset_r)
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AM_RANGE(0x3a06, 0x3a07) AM_WRITE(xain_scrollyP0_w)
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AM_RANGE(0x3a08, 0x3a08) AM_WRITE(xain_sound_command_w)
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AM_RANGE(0x3a09, 0x3a0c) AM_WRITE(xain_main_irq_w)
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AM_RANGE(0x3a0d, 0x3a0d) AM_WRITE(xain_flipscreen_w)
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AM_RANGE(0x3a0e, 0x3a0e) AM_WRITE(xain_68705_w) /* to 68705 */
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AM_RANGE(0x3a0e, 0x3a0e) AM_WRITE(xain_68705_w)
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AM_RANGE(0x3a0f, 0x3a0f) AM_WRITE(xainCPUA_bankswitch_w)
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AM_RANGE(0x3c00, 0x3dff) AM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split1_w) AM_BASE_GENERIC(paletteram)
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AM_RANGE(0x3e00, 0x3fff) AM_WRITE(paletteram_xxxxBBBBGGGGRRRR_split2_w) AM_BASE_GENERIC(paletteram2)
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@ -327,12 +442,19 @@ static ADDRESS_MAP_START( cpu_map_B, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x8000, 0xffff) AM_ROM
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ADDRESS_MAP_END
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#if 0
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static ADDRESS_MAP_START( mcu_map, ADDRESS_SPACE_PROGRAM, 8 )
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ADDRESS_MAP_GLOBAL_MASK(0x7ff)
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AM_RANGE(0x0000, 0x0000) AM_READWRITE(xain_68705_port_a_r, xain_68705_port_a_w)
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AM_RANGE(0x0001, 0x0001) AM_READWRITE(xain_68705_port_b_r, xain_68705_port_b_w)
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AM_RANGE(0x0002, 0x0002) AM_READWRITE(xain_68705_port_c_r, xain_68705_port_c_w)
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AM_RANGE(0x0004, 0x0004) AM_WRITE(xain_68705_ddr_a_w)
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AM_RANGE(0x0005, 0x0005) AM_WRITE(xain_68705_ddr_b_w)
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AM_RANGE(0x0006, 0x0006) AM_WRITE(xain_68705_ddr_c_w)
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// AM_RANGE(0x0008, 0x0008) AM_READWRITE(m68705_tdr_r, m68705_tdr_w)
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// AM_RANGE(0x0009, 0x0009) AM_READWRITE(m68705_tcr_r, m68705_tcr_w)
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AM_RANGE(0x0010, 0x007f) AM_RAM
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AM_RANGE(0x0080, 0x07ff) AM_ROM
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ADDRESS_MAP_END
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#endif
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static ADDRESS_MAP_START( sound_map, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x0000, 0x07ff) AM_RAM
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@ -413,8 +535,7 @@ static INPUT_PORTS_START( xsleena )
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PORT_START("VBLANK")
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PORT_BIT( 0x03, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNKNOWN ) /* when 0, 68705 is ready to send data */
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* when 1, 68705 is ready to receive data */
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PORT_BIT( 0x18, IP_ACTIVE_HIGH, IPT_SPECIAL) PORT_CUSTOM(mcu_status_r, NULL)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SPECIAL ) PORT_CUSTOM(xain_vblank_r, NULL) /* VBLANK */
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PORT_BIT( 0xc0, IP_ACTIVE_LOW, IPT_UNUSED )
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INPUT_PORTS_END
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@ -477,18 +598,18 @@ static MACHINE_START( xsleena )
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static MACHINE_DRIVER_START( xsleena )
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/* basic machine hardware */
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MDRV_CPU_ADD("maincpu", M6809, CPU_CLOCK) /* Confirmed 1.5MHz */
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MDRV_CPU_ADD("maincpu", M6809, CPU_CLOCK)
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MDRV_CPU_PROGRAM_MAP(main_map)
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MDRV_TIMER_ADD_SCANLINE("scantimer", xain_scanline, "screen", 0, 1)
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MDRV_CPU_ADD("sub", M6809, CPU_CLOCK) /* Confirmed 1.5MHz */
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MDRV_CPU_ADD("sub", M6809, CPU_CLOCK)
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MDRV_CPU_PROGRAM_MAP(cpu_map_B)
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MDRV_CPU_ADD("audiocpu", M6809, CPU_CLOCK) /* Confirmed 1.5MHz */
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MDRV_CPU_ADD("audiocpu", M6809, CPU_CLOCK)
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MDRV_CPU_PROGRAM_MAP(sound_map)
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// MDRV_CPU_ADD("mcu", M68705, MCU_CLOCK) /* Confirmed 3MHz */
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// MDRV_CPU_PROGRAM_MAP(mcu_map)
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MDRV_CPU_ADD("mcu", M68705, MCU_CLOCK)
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MDRV_CPU_PROGRAM_MAP(mcu_map)
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MDRV_MACHINE_START(xsleena)
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@ -508,14 +629,14 @@ static MACHINE_DRIVER_START( xsleena )
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/* sound hardware */
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MDRV_SPEAKER_STANDARD_MONO("mono")
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MDRV_SOUND_ADD("ym1", YM2203, 3000000)
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MDRV_SOUND_ADD("ym1", YM2203, MCU_CLOCK)
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MDRV_SOUND_CONFIG(ym2203_config)
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MDRV_SOUND_ROUTE(0, "mono", 0.50)
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MDRV_SOUND_ROUTE(1, "mono", 0.50)
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MDRV_SOUND_ROUTE(2, "mono", 0.50)
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MDRV_SOUND_ROUTE(3, "mono", 0.40)
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MDRV_SOUND_ADD("ym2", YM2203, 3000000)
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MDRV_SOUND_ADD("ym2", YM2203, MCU_CLOCK)
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MDRV_SOUND_ROUTE(0, "mono", 0.50)
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MDRV_SOUND_ROUTE(1, "mono", 0.50)
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MDRV_SOUND_ROUTE(2, "mono", 0.50)
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@ -523,6 +644,12 @@ static MACHINE_DRIVER_START( xsleena )
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MACHINE_DRIVER_END
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static MACHINE_DRIVER_START( xsleenab )
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MDRV_IMPORT_FROM(xsleena)
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MDRV_DEVICE_REMOVE("mcu")
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MACHINE_DRIVER_END
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/***************************************************************************
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Game driver(s)
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@ -543,8 +670,8 @@ ROM_START( xsleena )
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ROM_REGION( 0x10000, "audiocpu", 0 )
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ROM_LOAD( "s-3.4s", 0x8000, 0x8000, CRC(a5318cb8) SHA1(35fb28c5598e39f22552bb036ae356b78422f080) )
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// ROM_REGION( 0x800, "cpu3", 0 )
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// ROM_LOAD( "pz-0.113", 0x000, 0x800, CRC(0) SHA1(0) )
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ROM_REGION( 0x800, "mcu", 0 )
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ROM_LOAD( "p1-0.113", 0x000, 0x800, CRC(a432a907) SHA1(4708a40e3a82dec2c5a64bc5da884a37d503cb6b) )
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ROM_REGION( 0x08000, "gfx1", 0 )
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ROM_LOAD( "s-12.8b", 0x00000, 0x8000, CRC(83c00dd8) SHA1(8e9b19281039b63072270c7a63d9fb30cda570fd) ) /* chars */
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@ -648,8 +775,8 @@ ROM_START( solarwar )
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ROM_REGION( 0x10000, "audiocpu", 0 )
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ROM_LOAD( "s-3.4s", 0x8000, 0x8000, CRC(a5318cb8) SHA1(35fb28c5598e39f22552bb036ae356b78422f080) )
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// ROM_REGION( 0x800, "cpu3", 0 )
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// ROM_LOAD( "pz-0.113", 0x000, 0x800, CRC(0) SHA1(0) )
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ROM_REGION( 0x800, "mcu", 0 )
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ROM_LOAD( "p1-0.113", 0x000, 0x800, CRC(a432a907) SHA1(4708a40e3a82dec2c5a64bc5da884a37d503cb6b) )
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ROM_REGION( 0x08000, "gfx1", 0 )
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ROM_LOAD( "s-12.8b", 0x00000, 0x8000, CRC(83c00dd8) SHA1(8e9b19281039b63072270c7a63d9fb30cda570fd) ) /* chars */
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@ -689,33 +816,6 @@ ROM_START( solarwar )
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ROM_END
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static DRIVER_INIT( xsleena )
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{
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UINT8 *RAM = memory_region(machine, "maincpu");
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/* do the same patch as the bootleg xsleena */
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RAM[0xd488] = 0x12;
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RAM[0xd489] = 0x12;
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RAM[0xd48a] = 0x12;
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RAM[0xd48b] = 0x12;
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RAM[0xd48c] = 0x12;
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RAM[0xd48d] = 0x12;
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}
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static DRIVER_INIT( solarwar )
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{
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UINT8 *RAM = memory_region(machine, "maincpu");
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/* do the same patch as the bootleg xsleena */
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RAM[0xd47e] = 0x12;
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RAM[0xd47f] = 0x12;
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RAM[0xd480] = 0x12;
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RAM[0xd481] = 0x12;
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RAM[0xd482] = 0x12;
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RAM[0xd483] = 0x12;
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}
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GAME( 1986, xsleena, 0, xsleena, xsleena, xsleena, ROT0, "Technos Japan", "Xain'd Sleena", 0 )
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GAME( 1986, xsleenab, xsleena, xsleena, xsleena, 0, ROT0, "bootleg", "Xain'd Sleena (bootleg)", 0 )
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GAME( 1986, solarwar, xsleena, xsleena, xsleena, solarwar, ROT0, "Technos Japan / Taito (Memetron license)", "Solar-Warrior", 0 )
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GAME( 1986, xsleena, 0, xsleena, xsleena, 0, ROT0, "Technos Japan", "Xain'd Sleena", 0 )
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GAME( 1986, xsleenab, xsleena, xsleenab, xsleena, 0, ROT0, "bootleg", "Xain'd Sleena (bootleg)", 0 )
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GAME( 1986, solarwar, xsleena, xsleena, xsleena, 0, ROT0, "Technos Japan / Taito (Memetron license)", "Solar-Warrior", 0 )
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