diff --git a/src/emu/cpu/m37710/m37710.c b/src/emu/cpu/m37710/m37710.c
index 19e4a116493..4979fc71ae1 100644
--- a/src/emu/cpu/m37710/m37710.c
+++ b/src/emu/cpu/m37710/m37710.c
@@ -57,7 +57,7 @@
 
 #define M37710_DEBUG	(0)	// enables verbose logging for peripherals, etc.
 
-static void m37710_set_irq_line(m37710i_cpu_struct *m37710i_cpu, int line, int state);
+static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state);
 
 /* interrupt control mapping */
 
@@ -260,20 +260,20 @@ static const char *const m37710_tnames[8] =
 
 static TIMER_CALLBACK( m37710_timer_cb )
 {
-	m37710i_cpu_struct *m37710i_cpu = ptr;
+	m37710i_cpu_struct *cpustate = ptr;
 	int which = param;
 	int curirq = M37710_LINE_TIMERA0 - which;
 
-	cpu_push_context(m37710i_cpu->device);
-	timer_adjust_oneshot(m37710i_cpu->timers[which], m37710i_cpu->reload[which], param);
+	cpu_push_context(cpustate->device);
+	timer_adjust_oneshot(cpustate->timers[which], cpustate->reload[which], param);
 
-	m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] |= 0x04;
-	m37710_set_irq_line(m37710i_cpu, curirq, PULSE_LINE);
-	cpu_triggerint(m37710i_cpu->device);
+	cpustate->m37710_regs[m37710_irq_levels[curirq]] |= 0x04;
+	m37710_set_irq_line(cpustate, curirq, PULSE_LINE);
+	cpu_triggerint(cpustate->device);
 	cpu_pop_context();
 }
 
-static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int state)
+static void m37710_external_tick(m37710i_cpu_struct *cpustate, int timer, int state)
 {
 	// we only care if the state is "on"
 	if (!state)
@@ -282,18 +282,18 @@ static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int
 	}
 
 	// check if enabled
-	if (m37710i_cpu->m37710_regs[0x40] & (1<<timer))
+	if (cpustate->m37710_regs[0x40] & (1<<timer))
 	{
-		if ((m37710i_cpu->m37710_regs[0x56+timer] & 0x3) == 1)
+		if ((cpustate->m37710_regs[0x56+timer] & 0x3) == 1)
 		{
-			if (m37710i_cpu->m37710_regs[0x46+(timer*2)] == 0xff)
+			if (cpustate->m37710_regs[0x46+(timer*2)] == 0xff)
 			{
-				m37710i_cpu->m37710_regs[0x46+(timer*2)] = 0;
-				m37710i_cpu->m37710_regs[0x46+(timer*2)+1]++;
+				cpustate->m37710_regs[0x46+(timer*2)] = 0;
+				cpustate->m37710_regs[0x46+(timer*2)+1]++;
 			}
 			else
 			{
-				m37710i_cpu->m37710_regs[0x46+(timer*2)]++;
+				cpustate->m37710_regs[0x46+(timer*2)]++;
 			}
 		}
 		else
@@ -303,40 +303,39 @@ static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int
 	}
 }
 
-static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine *machine, int timer)
+static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, running_machine *machine, int timer)
 {
-	int cpunum = cpunum_get_active();
 	int tval;
 	static const int tcr[8] = { 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d };
 	attotime time;
 	static const int tscales[4] = { 2, 16, 64, 512 };
 
 	// check if enabled
-	if (m37710i_cpu->m37710_regs[0x40] & (1<<timer))
+	if (cpustate->m37710_regs[0x40] & (1<<timer))
 	{
 		#if M37710_DEBUG
 		mame_printf_debug("Timer %d (%s) is enabled\n", timer, m37710_tnames[timer]);
 		#endif
 
 		// set the timer's value
-		tval = m37710i_cpu->m37710_regs[0x46+(timer*2)] | (m37710i_cpu->m37710_regs[0x47+(timer*2)]<<8);
+		tval = cpustate->m37710_regs[0x46+(timer*2)] | (cpustate->m37710_regs[0x47+(timer*2)]<<8);
 
 		// check timer's mode
 		// modes are slightly different between timer groups A and B
 		if (timer < 5)
 		{
-			switch (m37710i_cpu->m37710_regs[0x56+timer] & 0x3)
+			switch (cpustate->m37710_regs[0x56+timer] & 0x3)
 			{
 				case 0:	      	// timer mode
-					time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[m37710i_cpu->m37710_regs[tcr[timer]]>>6]);
+					time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]);
 					time = attotime_mul(time, tval + 1);
 
 					#if M37710_DEBUG
 					mame_printf_debug("Timer %d in timer mode, %f Hz\n", timer, 1.0 / attotime_to_double(time));
 					#endif
 
-					timer_adjust_oneshot(m37710i_cpu->timers[timer], time, cpunum);
-					m37710i_cpu->reload[timer] = time;
+					timer_adjust_oneshot(cpustate->timers[timer], time, timer);
+					cpustate->reload[timer] = time;
 					break;
 
 				case 1:	      	// event counter mode
@@ -360,18 +359,18 @@ static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine
 		}
 		else
 		{
-			switch (m37710i_cpu->m37710_regs[0x56+timer] & 0x3)
+			switch (cpustate->m37710_regs[0x56+timer] & 0x3)
 			{
 				case 0:	      	// timer mode
-					time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[m37710i_cpu->m37710_regs[tcr[timer]]>>6]);
+					time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]);
 					time = attotime_mul(time, tval + 1);
 
 					#if M37710_DEBUG
 					mame_printf_debug("Timer %d in timer mode, %f Hz\n", timer, 1.0 / attotime_to_double(time));
 					#endif
 
-					timer_adjust_oneshot(m37710i_cpu->timers[timer], time, cpunum);
-					m37710i_cpu->reload[timer] = time;
+					timer_adjust_oneshot(cpustate->timers[timer], time, timer);
+					cpustate->reload[timer] = time;
 					break;
 
 				case 1:	      	// event counter mode
@@ -396,7 +395,7 @@ static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine
 	}
 }
 
-static UINT8 m37710_internal_r(m37710i_cpu_struct *m37710i_cpu, int offset)
+static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset)
 {
 	#if M37710_DEBUG
 	if (offset > 1)
@@ -406,147 +405,147 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *m37710i_cpu, int offset)
 	switch (offset)
 	{
 		case 2: // p0
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT0);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT0);
 			break;
 		case 3: // p1
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT1);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT1);
 			break;
 		case 6: // p2
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT2);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT2);
 			break;
 		case 7: // p3
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT3);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT3);
 			break;
 		case 0xa: // p4
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT4);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT4);
 			break;
 		case 0xb: // p5
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT5);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT5);
 			break;
 		case 0xe: // p6
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT6);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT6);
 			break;
 		case 0xf: // p7
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT7);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT7);
 			break;
 		case 0x12: // p8
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT8);
+			return memory_read_byte_8le(cpustate->io, M37710_PORT8);
 			break;
 
 		case 0x20:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC0_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC0_L);
 			break;
 		case 0x21:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC0_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC0_H);
 			break;
 		case 0x22:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC1_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC1_L);
 			break;
 		case 0x23:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC1_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC1_H);
 			break;
 		case 0x24:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC2_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC2_L);
 			break;
 		case 0x25:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC2_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC2_H);
 			break;
 		case 0x26:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC3_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC3_L);
 			break;
 		case 0x27:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC3_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC3_H);
 			break;
 		case 0x28:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC4_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC4_L);
 			break;
 		case 0x29:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC4_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC4_H);
 			break;
 		case 0x2a:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC5_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC5_L);
 			break;
 		case 0x2b:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC5_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC5_H);
 			break;
 		case 0x2c:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC6_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC6_L);
 			break;
 		case 0x2d:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC6_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC6_H);
 			break;
 		case 0x2e:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC7_L);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC7_L);
 			break;
 		case 0x2f:
-			return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC7_H);
+			return memory_read_byte_8le(cpustate->io, M37710_ADC7_H);
 			break;
 		case 0x35:
 			return 0xff;	// UART control
 			break;
 
 		case 0x70:	// A/D IRQ control
-			return m37710i_cpu->m37710_regs[offset] | 8;
+			return cpustate->m37710_regs[offset] | 8;
 			break;
 	}
 
-	return m37710i_cpu->m37710_regs[offset];
+	return cpustate->m37710_regs[offset];
 }
 
-static void m37710_internal_w(m37710i_cpu_struct *m37710i_cpu, int offset, UINT8 data)
+static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 data)
 {
 	int i;
 
 	switch(offset)
 	{
 		case 2: // p0
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT0, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT0, data);
 			return;
 			break;
 		case 3: // p1
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT1, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT1, data);
 			return;
 			break;
 		case 6: // p2
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT2, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT2, data);
 			return;
 			break;
 		case 7: // p3
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT3, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT3, data);
 			return;
 			break;
 		case 0xa: // p4
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT4, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT4, data);
 			return;
 			break;
 		case 0xb: // p5
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT5, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT5, data);
 			return;
 			break;
 		case 0xe: // p6
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT6, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT6, data);
 			return;
 			break;
 		case 0xf: // p7
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT7, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT7, data);
 			return;
 			break;
 		case 0x12: // p8
-			memory_write_byte_8le(m37710i_cpu->io, M37710_PORT8, data);
+			memory_write_byte_8le(cpustate->io, M37710_PORT8, data);
 			return;
 			break;
 
 		case 0x40:	// count start
 			for (i = 0; i < 8; i++)
 			{
-				if ((data & (1<<i)) && !(m37710i_cpu->m37710_regs[offset] & (1<<i)))
+				if ((data & (1<<i)) && !(cpustate->m37710_regs[offset] & (1<<i)))
 				{
-					m37710i_cpu->m37710_regs[offset] |= (1<<i);
-					m37710_recalc_timer(m37710i_cpu, m37710i_cpu->device->machine, i);
+					cpustate->m37710_regs[offset] |= (1<<i);
+					m37710_recalc_timer(cpustate, cpustate->device->machine, i);
 				}
 			}
 
-			m37710i_cpu->m37710_regs[offset] = data;
+			cpustate->m37710_regs[offset] = data;
 
 			return;
 			break;
@@ -556,29 +555,29 @@ static void m37710_internal_w(m37710i_cpu_struct *m37710i_cpu, int offset, UINT8
 			break;
 	}
 
-	m37710i_cpu->m37710_regs[offset] = data;
+	cpustate->m37710_regs[offset] = data;
 
 	#if M37710_DEBUG
 	if (offset >= 0x1e && offset <= 0x40)
-	logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], m37710i_cpu->m37710_regs[offset]);
+	logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], cpustate->m37710_regs[offset]);
 	#endif
 }
 
 static READ16_HANDLER( m37710_internal_word_r )
 {
-	m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)space->cpu->token;
+	m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)space->cpu->token;
 
 	if (mem_mask == 0xffff)
 	{
-		return (m37710_internal_r(m37710i_cpu, offset*2) | m37710_internal_r(m37710i_cpu, (offset*2)+1)<<8);
+		return (m37710_internal_r(cpustate, offset*2) | m37710_internal_r(cpustate, (offset*2)+1)<<8);
 	}
 	else if (mem_mask == 0xff00)
 	{
-		return m37710_internal_r(m37710i_cpu, (offset*2)+1)<<8;
+		return m37710_internal_r(cpustate, (offset*2)+1)<<8;
 	}
 	else if (mem_mask == 0x00ff)
 	{
-		return m37710_internal_r(m37710i_cpu, (offset*2));
+		return m37710_internal_r(cpustate, (offset*2));
 	}
 
 	return 0;
@@ -586,56 +585,56 @@ static READ16_HANDLER( m37710_internal_word_r )
 
 static WRITE16_HANDLER( m37710_internal_word_w )
 {
-	m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)space->cpu->token;
+	m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)space->cpu->token;
 
 	if (mem_mask == 0xffff)
 	{
-		m37710_internal_w(m37710i_cpu, (offset*2), data & 0xff);
-		m37710_internal_w(m37710i_cpu, (offset*2)+1, data>>8);
+		m37710_internal_w(cpustate, (offset*2), data & 0xff);
+		m37710_internal_w(cpustate, (offset*2)+1, data>>8);
 	}
 	else if (mem_mask == 0xff00)
 	{
-		m37710_internal_w(m37710i_cpu, (offset*2)+1, data>>8);
+		m37710_internal_w(cpustate, (offset*2)+1, data>>8);
 	}
 	else if (mem_mask == 0x00ff)
 	{
-		m37710_internal_w(m37710i_cpu, (offset*2), data & 0xff);
+		m37710_internal_w(cpustate, (offset*2), data & 0xff);
 	}
 }
 
-extern void (*const m37710i_opcodes_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes42_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes89_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern uint m37710i_get_reg_M0X0(m37710i_cpu_struct *m37710i_cpu, int regnum);
-extern void m37710i_set_reg_M0X0(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
-extern void m37710i_set_line_M0X0(m37710i_cpu_struct *m37710i_cpu, int line, int state);
-extern int  m37710i_execute_M0X0(m37710i_cpu_struct *m37710i_cpu, int cycles);
+extern void (*const m37710i_opcodes_M0X0[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes42_M0X0[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes89_M0X0[])(m37710i_cpu_struct *cpustate);
+extern uint m37710i_get_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum);
+extern void m37710i_set_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum, uint val);
+extern void m37710i_set_line_M0X0(m37710i_cpu_struct *cpustate, int line, int state);
+extern int  m37710i_execute_M0X0(m37710i_cpu_struct *cpustate, int cycles);
 
-extern void (*const m37710i_opcodes_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes42_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes89_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern uint m37710i_get_reg_M0X1(m37710i_cpu_struct *m37710i_cpu, int regnum);
-extern void m37710i_set_reg_M0X1(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
-extern void m37710i_set_line_M0X1(m37710i_cpu_struct *m37710i_cpu, int line, int state);
-extern int  m37710i_execute_M0X1(m37710i_cpu_struct *m37710i_cpu, int cycles);
+extern void (*const m37710i_opcodes_M0X1[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes42_M0X1[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes89_M0X1[])(m37710i_cpu_struct *cpustate);
+extern uint m37710i_get_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum);
+extern void m37710i_set_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum, uint val);
+extern void m37710i_set_line_M0X1(m37710i_cpu_struct *cpustate, int line, int state);
+extern int  m37710i_execute_M0X1(m37710i_cpu_struct *cpustate, int cycles);
 
-extern void (*const m37710i_opcodes_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes42_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes89_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
-extern uint m37710i_get_reg_M1X0(m37710i_cpu_struct *m37710i_cpu, int regnum);
-extern void m37710i_set_reg_M1X0(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
-extern void m37710i_set_line_M1X0(m37710i_cpu_struct *m37710i_cpu, int line, int state);
-extern int  m37710i_execute_M1X0(m37710i_cpu_struct *m37710i_cpu, int cycles);
+extern void (*const m37710i_opcodes_M1X0[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes42_M1X0[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes89_M1X0[])(m37710i_cpu_struct *cpustate);
+extern uint m37710i_get_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum);
+extern void m37710i_set_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum, uint val);
+extern void m37710i_set_line_M1X0(m37710i_cpu_struct *cpustate, int line, int state);
+extern int  m37710i_execute_M1X0(m37710i_cpu_struct *cpustate, int cycles);
 
-extern void (*const m37710i_opcodes_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes42_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const m37710i_opcodes89_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
-extern uint m37710i_get_reg_M1X1(m37710i_cpu_struct *m37710i_cpu, int regnum);
-extern void m37710i_set_reg_M1X1(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
-extern void m37710i_set_line_M1X1(m37710i_cpu_struct *m37710i_cpu, int line, int state);
-extern int  m37710i_execute_M1X1(m37710i_cpu_struct *m37710i_cpu, int cycles);
+extern void (*const m37710i_opcodes_M1X1[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes42_M1X1[])(m37710i_cpu_struct *cpustate);
+extern void (*const m37710i_opcodes89_M1X1[])(m37710i_cpu_struct *cpustate);
+extern uint m37710i_get_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum);
+extern void m37710i_set_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum, uint val);
+extern void m37710i_set_line_M1X1(m37710i_cpu_struct *cpustate, int line, int state);
+extern int  m37710i_execute_M1X1(m37710i_cpu_struct *cpustate, int cycles);
 
-void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *m37710i_cpu) =
+void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *cpustate) =
 {
 	m37710i_opcodes_M0X0,
 	m37710i_opcodes_M0X1,
@@ -643,7 +642,7 @@ void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *m37710i_cpu) =
 	m37710i_opcodes_M1X1,
 };
 
-void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *m37710i_cpu) =
+void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *cpustate) =
 {
 	m37710i_opcodes42_M0X0,
 	m37710i_opcodes42_M0X1,
@@ -651,7 +650,7 @@ void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *m37710i_cpu) =
 	m37710i_opcodes42_M1X1,
 };
 
-void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *m37710i_cpu) =
+void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *cpustate) =
 {
 	m37710i_opcodes89_M0X0,
 	m37710i_opcodes89_M0X1,
@@ -659,7 +658,7 @@ void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *m37710i_cpu) =
 	m37710i_opcodes89_M1X1,
 };
 
-uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum) =
+uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *cpustate, int regnum) =
 {
 	m37710i_get_reg_M0X0,
 	m37710i_get_reg_M0X1,
@@ -667,7 +666,7 @@ uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum) =
 	m37710i_get_reg_M1X1,
 };
 
-void (*const m37710i_set_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val) =
+void (*const m37710i_set_reg[4])(m37710i_cpu_struct *cpustate, int regnum, uint val) =
 {
 	m37710i_set_reg_M0X0,
 	m37710i_set_reg_M0X1,
@@ -675,7 +674,7 @@ void (*const m37710i_set_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum, ui
 	m37710i_set_reg_M1X1,
 };
 
-void (*const m37710i_set_line[4])(m37710i_cpu_struct *m37710i_cpu, int line, int state) =
+void (*const m37710i_set_line[4])(m37710i_cpu_struct *cpustate, int line, int state) =
 {
 	m37710i_set_line_M0X0,
 	m37710i_set_line_M0X1,
@@ -683,7 +682,7 @@ void (*const m37710i_set_line[4])(m37710i_cpu_struct *m37710i_cpu, int line, int
 	m37710i_set_line_M1X1,
 };
 
-int (*const m37710i_execute[4])(m37710i_cpu_struct *m37710i_cpu, int cycles) =
+int (*const m37710i_execute[4])(m37710i_cpu_struct *cpustate, int cycles) =
 {
 	m37710i_execute_M0X0,
 	m37710i_execute_M0X1,
@@ -693,19 +692,19 @@ int (*const m37710i_execute[4])(m37710i_cpu_struct *m37710i_cpu, int cycles) =
 
 /* internal functions */
 
-INLINE void m37710i_push_8(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_push_8(m37710i_cpu_struct *cpustate, uint value)
 {
 	m37710_write_8(REG_S, value);
 	REG_S = MAKE_UINT_16(REG_S-1);
 }
 
-INLINE void m37710i_push_16(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_push_16(m37710i_cpu_struct *cpustate, uint value)
 {
-	m37710i_push_8(m37710i_cpu, value>>8);
-	m37710i_push_8(m37710i_cpu, value&0xff);
+	m37710i_push_8(cpustate, value>>8);
+	m37710i_push_8(cpustate, value&0xff);
 }
 
-INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
+INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate)
 {
 	return	(FLAG_N&0x80)		|
 			((FLAG_V>>1)&0x40)	|
@@ -717,7 +716,7 @@ INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
 			((FLAG_C>>8)&1);
 }
 
-void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
+void m37710i_update_irqs(m37710i_cpu_struct *cpustate)
 {
 	int curirq, pending = LINE_IRQ;
 	int wantedIRQ, curpri;
@@ -737,16 +736,16 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
 			// this IRQ is set
 			if (m37710_irq_levels[curirq])
 			{
-//              logerror("line %d set, level %x curpri %x IPL %x\n", curirq, m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7, curpri, m37710i_cpu->ipl);
+//              logerror("line %d set, level %x curpri %x IPL %x\n", curirq, cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7, curpri, cpustate->ipl);
 				// it's maskable, check if the level works
-				if ((m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7) > curpri)
+				if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > curpri)
 				{
 					// also make sure it's acceptable for the current CPU level
-					if ((m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7) > m37710i_cpu->ipl)
+					if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > cpustate->ipl)
 					{
 						// mark us as the best candidate
 						wantedIRQ = curirq;
-						curpri = m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7;
+						curpri = cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7;
 					}
 				}
 			}
@@ -762,7 +761,7 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
 
 	if (wantedIRQ != -1)
 	{
-		if (INT_ACK) INT_ACK(m37710i_cpu->device, wantedIRQ);
+		if (INT_ACK) INT_ACK(cpustate->device, wantedIRQ);
 
 		// make sure we're running to service the interrupt
 		CPU_STOPPED &= ~STOP_LEVEL_WAI;
@@ -770,27 +769,27 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
 		// indicate we're servicing it now
 		if (m37710_irq_levels[wantedIRQ])
 		{
-			m37710i_cpu->m37710_regs[m37710_irq_levels[wantedIRQ]] &= ~8;
+			cpustate->m37710_regs[m37710_irq_levels[wantedIRQ]] &= ~8;
 		}
 
 		// auto-clear if it's an internal line
 		if (wantedIRQ <= 12)
 		{
-			m37710_set_irq_line(m37710i_cpu, wantedIRQ, CLEAR_LINE);
+			m37710_set_irq_line(cpustate, wantedIRQ, CLEAR_LINE);
 		}
 
 		// let's do it...
 		// push PB, then PC, then status
 		CLK(8);
-//      mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, m37710i_cpu->ipl);
-		m37710i_push_8(m37710i_cpu, REG_PB>>16);
-		m37710i_push_16(m37710i_cpu, REG_PC);
-		m37710i_push_8(m37710i_cpu, m37710i_cpu->ipl);
-		m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+//      mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, cpustate->ipl);
+		m37710i_push_8(cpustate, REG_PB>>16);
+		m37710i_push_16(cpustate, REG_PC);
+		m37710i_push_8(cpustate, cpustate->ipl);
+		m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 
 		// set I to 1, set IPL to the interrupt we're taking
 		FLAG_I = IFLAG_SET;
-		m37710i_cpu->ipl = curpri;
+		cpustate->ipl = curpri;
 		// then PB=0, PC=(vector)
 		REG_PB = 0;
 		REG_PC = m37710_read_8(m37710_irq_vectors[wantedIRQ]) |
@@ -804,7 +803,7 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
 
 static CPU_RESET( m37710 )
 {
-	m37710i_cpu_struct *m37710i_cpu = device->token;
+	m37710i_cpu_struct *cpustate = device->token;
 
 	/* Start the CPU */
 	CPU_STOPPED = 0;
@@ -833,7 +832,7 @@ static CPU_RESET( m37710 )
 	IRQ_DELAY = 0;
 
 	/* Set the function tables to emulation mode */
-	m37710i_set_execution_mode(m37710i_cpu, EXECUTION_MODE_M0X0);
+	m37710i_set_execution_mode(cpustate, EXECUTION_MODE_M0X0);
 
 	FLAG_Z = ZFLAG_CLEAR;
 	REG_S = 0x1ff;
@@ -871,34 +870,34 @@ static CPU_SET_CONTEXT( m37710 )
 }
 
 /* Set the Program Counter */
-static void m37710_set_pc(m37710i_cpu_struct *m37710i_cpu, unsigned val)
+static void m37710_set_pc(m37710i_cpu_struct *cpustate, unsigned val)
 {
 	REG_PC = MAKE_UINT_16(val);
 	m37710_jumping(REG_PB | REG_PC);
 }
 
 /* Get the current Stack Pointer */
-static unsigned m37710_get_sp(m37710i_cpu_struct *m37710i_cpu)
+static unsigned m37710_get_sp(m37710i_cpu_struct *cpustate)
 {
 	return REG_S;
 }
 
 /* Set the Stack Pointer */
-static void m37710_set_sp(m37710i_cpu_struct *m37710i_cpu, unsigned val)
+static void m37710_set_sp(m37710i_cpu_struct *cpustate, unsigned val)
 {
 	REG_S = MAKE_UINT_16(val);
 }
 
 /* Get a register */
-static unsigned m37710_get_reg(m37710i_cpu_struct *m37710i_cpu, int regnum)
+static unsigned m37710_get_reg(m37710i_cpu_struct *cpustate, int regnum)
 {
-	return FTABLE_GET_REG(m37710i_cpu, regnum);
+	return FTABLE_GET_REG(cpustate, regnum);
 }
 
 /* Set a register */
-static void m37710_set_reg(m37710i_cpu_struct *m37710i_cpu, int regnum, unsigned value)
+static void m37710_set_reg(m37710i_cpu_struct *cpustate, int regnum, unsigned value)
 {
-	FTABLE_SET_REG(m37710i_cpu, regnum, value);
+	FTABLE_SET_REG(cpustate, regnum, value);
 }
 
 /* Load a CPU state */
@@ -912,9 +911,9 @@ void m37710_state_save(void *file)
 }
 
 /* Set an interrupt line */
-static void m37710_set_irq_line(m37710i_cpu_struct *m37710i_cpu, int line, int state)
+static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state)
 {
-	FTABLE_SET_LINE(m37710i_cpu, line, state);
+	FTABLE_SET_LINE(cpustate, line, state);
 }
 
 /* Set the callback that is called when servicing an interrupt */
@@ -930,17 +929,17 @@ void m37710_set_irq_callback(cpu_irq_callback callback)
 
 static CPU_DISASSEMBLE( m37710 )
 {
-	m37710i_cpu_struct *m37710i_cpu = device->token;
+	m37710i_cpu_struct *cpustate = device->token;
 
 	return m7700_disassemble(buffer, (pc&0xffff), pc>>16, oprom, FLAG_M, FLAG_X);
 }
 
 static STATE_POSTLOAD( m37710_restore_state )
 {
-	m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)param;
+	m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)param;
 
 	// restore proper function pointers
-	m37710i_set_execution_mode(m37710i_cpu, (FLAG_M>>4) | (FLAG_X>>4));
+	m37710i_set_execution_mode(cpustate, (FLAG_M>>4) | (FLAG_X>>4));
 
 	// make sure the memory system can keep up
 	m37710i_jumping(REG_PB | REG_PC);
@@ -948,74 +947,74 @@ static STATE_POSTLOAD( m37710_restore_state )
 
 static CPU_INIT( m37710 )
 {
-	m37710i_cpu_struct *m37710i_cpu = device->token;
+	m37710i_cpu_struct *cpustate = device->token;
 	int i;
 
-	memset(m37710i_cpu, 0, sizeof(m37710i_cpu));
+	memset(cpustate, 0, sizeof(cpustate));
 
 	INT_ACK = irqcallback;
-	m37710i_cpu->device = device;
-	m37710i_cpu->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
-	m37710i_cpu->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
+	cpustate->device = device;
+	cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
+	cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
 
-	m37710i_cpu->ICount = 0;
+	cpustate->ICount = 0;
 
-	m37710i_cpu->source = 0;
-	m37710i_cpu->destination = 0;
+	cpustate->source = 0;
+	cpustate->destination = 0;
 	
 	for (i = 0; i < 8; i++)
-		m37710i_cpu->timers[0] = timer_alloc(device->machine, m37710_timer_cb, m37710i_cpu);
+		cpustate->timers[i] = timer_alloc(device->machine, m37710_timer_cb, cpustate);
 
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->a);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->b);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ba);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->bb);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->x);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->y);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->s);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->pc);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ppc);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->pb);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->db);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->d);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_e);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_m);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_x);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_n);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_v);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_d);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_i);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_z);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_c);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->line_irq);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ipl);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ir);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im2);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im3);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im4);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->irq_delay);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->irq_level);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->stopped);
-	state_save_register_item_array("M377xx", device->tag, 0, m37710i_cpu->m37710_regs);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[0].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[0].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[1].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[1].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[2].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[2].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[3].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[3].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[4].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[4].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[5].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[5].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[6].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[6].attoseconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[7].seconds);
-	state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[7].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->a);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->b);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->ba);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->bb);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->x);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->y);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->s);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->pc);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->ppc);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->pb);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->db);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->d);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_e);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_m);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_x);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_n);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_v);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_d);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_i);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_z);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->flag_c);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->line_irq);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->ipl);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->ir);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->im);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->im2);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->im3);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->im4);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->irq_delay);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->irq_level);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->stopped);
+	state_save_register_item_array("M377xx", device->tag, 0, cpustate->m37710_regs);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[0].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[0].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[1].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[1].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[2].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[2].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[3].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[3].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[4].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[4].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[5].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[5].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[6].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[6].attoseconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[7].seconds);
+	state_save_register_item("M377xx", device->tag, 0, cpustate->reload[7].attoseconds);
 
-	state_save_register_postload(device->machine, m37710_restore_state, m37710i_cpu);
+	state_save_register_postload(device->machine, m37710_restore_state, cpustate);
 }
 
 /**************************************************************************
@@ -1024,40 +1023,40 @@ static CPU_INIT( m37710 )
 
 static CPU_SET_INFO( m37710 )
 {
-	m37710i_cpu_struct *m37710i_cpu = device->token;
+	m37710i_cpu_struct *cpustate = device->token;
 
 	switch (state)
 	{
 		/* --- the following bits of info are set as 64-bit signed integers --- */
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_ADC: 	m37710_set_irq_line(m37710i_cpu, M37710_LINE_ADC, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: 	m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ0, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: 	m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ1, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: 	m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ2, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_ADC: 	m37710_set_irq_line(cpustate, M37710_LINE_ADC, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: 	m37710_set_irq_line(cpustate, M37710_LINE_IRQ0, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: 	m37710_set_irq_line(cpustate, M37710_LINE_IRQ1, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: 	m37710_set_irq_line(cpustate, M37710_LINE_IRQ2, info->i); break;
 
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA0TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA1TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA2TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA3TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA4TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB0TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB1TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
-		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB2TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA3TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA4TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
+		case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
 
-		case CPUINFO_INT_PC:							REG_PB = info->i & 0xff0000; m37710_set_pc(m37710i_cpu, info->i & 0xffff); break;
-		case CPUINFO_INT_SP:							m37710_set_sp(m37710i_cpu, info->i);	     			break;
+		case CPUINFO_INT_PC:							REG_PB = info->i & 0xff0000; m37710_set_pc(cpustate, info->i & 0xffff); break;
+		case CPUINFO_INT_SP:							m37710_set_sp(cpustate, info->i);	     			break;
 
-		case CPUINFO_INT_REGISTER + M37710_PC:			m37710_set_reg(m37710i_cpu, M37710_PC, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_S:			m37710_set_reg(m37710i_cpu, M37710_S, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_P:			m37710_set_reg(m37710i_cpu, M37710_P, info->i&0xff);	m37710i_cpu->ipl = (info->i>>8)&0xff;	break;
-		case CPUINFO_INT_REGISTER + M37710_A:			m37710_set_reg(m37710i_cpu, M37710_A, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_X:			m37710_set_reg(m37710i_cpu, M37710_X, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_Y:			m37710_set_reg(m37710i_cpu, M37710_Y, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_PB:			m37710_set_reg(m37710i_cpu, M37710_PB, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_DB:			m37710_set_reg(m37710i_cpu, M37710_DB, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_D:			m37710_set_reg(m37710i_cpu, M37710_D, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_E:			m37710_set_reg(m37710i_cpu, M37710_E, info->i);		break;
-		case CPUINFO_INT_REGISTER + M37710_NMI_STATE:	m37710_set_reg(m37710i_cpu, M37710_NMI_STATE, info->i); break;
-		case CPUINFO_INT_REGISTER + M37710_IRQ_STATE:	m37710_set_reg(m37710i_cpu, M37710_IRQ_STATE, info->i); break;
+		case CPUINFO_INT_REGISTER + M37710_PC:			m37710_set_reg(cpustate, M37710_PC, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_S:			m37710_set_reg(cpustate, M37710_S, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_P:			m37710_set_reg(cpustate, M37710_P, info->i&0xff);	cpustate->ipl = (info->i>>8)&0xff;	break;
+		case CPUINFO_INT_REGISTER + M37710_A:			m37710_set_reg(cpustate, M37710_A, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_X:			m37710_set_reg(cpustate, M37710_X, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_Y:			m37710_set_reg(cpustate, M37710_Y, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_PB:			m37710_set_reg(cpustate, M37710_PB, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_DB:			m37710_set_reg(cpustate, M37710_DB, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_D:			m37710_set_reg(cpustate, M37710_D, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_E:			m37710_set_reg(cpustate, M37710_E, info->i);		break;
+		case CPUINFO_INT_REGISTER + M37710_NMI_STATE:	m37710_set_reg(cpustate, M37710_NMI_STATE, info->i); break;
+		case CPUINFO_INT_REGISTER + M37710_IRQ_STATE:	m37710_set_reg(cpustate, M37710_IRQ_STATE, info->i); break;
 	}
 }
 
@@ -1073,7 +1072,7 @@ ADDRESS_MAP_END
 
 CPU_GET_INFO( m37710 )
 {
-	m37710i_cpu_struct *m37710i_cpu = (device != NULL) ? device->token : NULL;
+	m37710i_cpu_struct *cpustate = (device != NULL) ? device->token : NULL;
 
 	switch (state)
 	{
@@ -1106,21 +1105,21 @@ CPU_GET_INFO( m37710 )
 
 		case CPUINFO_INT_PREVIOUSPC:					info->i = REG_PPC;						break;
 		case CPUINFO_INT_PC:	 						info->i = (REG_PB | REG_PC);			break;
-		case CPUINFO_INT_SP:							info->i = m37710_get_sp(m37710i_cpu);				break;
+		case CPUINFO_INT_SP:							info->i = m37710_get_sp(cpustate);				break;
 
-		case CPUINFO_INT_REGISTER + M37710_PC:			info->i = m37710_get_reg(m37710i_cpu, M37710_PC);	break;
-		case CPUINFO_INT_REGISTER + M37710_S:			info->i = m37710_get_reg(m37710i_cpu, M37710_S);		break;
-		case CPUINFO_INT_REGISTER + M37710_P:			info->i = m37710_get_reg(m37710i_cpu, M37710_P) | (m37710i_cpu->ipl<<8); break;
-		case CPUINFO_INT_REGISTER + M37710_A:			info->i = m37710_get_reg(m37710i_cpu, M37710_A);		break;
-		case CPUINFO_INT_REGISTER + M37710_B:			info->i = m37710_get_reg(m37710i_cpu, M37710_B);		break;
-		case CPUINFO_INT_REGISTER + M37710_X:			info->i = m37710_get_reg(m37710i_cpu, M37710_X);		break;
-		case CPUINFO_INT_REGISTER + M37710_Y:			info->i = m37710_get_reg(m37710i_cpu, M37710_Y);		break;
-		case CPUINFO_INT_REGISTER + M37710_PB:			info->i = m37710_get_reg(m37710i_cpu, M37710_PB);	break;
-		case CPUINFO_INT_REGISTER + M37710_DB:			info->i = m37710_get_reg(m37710i_cpu, M37710_DB);	break;
-		case CPUINFO_INT_REGISTER + M37710_D:			info->i = m37710_get_reg(m37710i_cpu, M37710_D);		break;
-		case CPUINFO_INT_REGISTER + M37710_E:			info->i = m37710_get_reg(m37710i_cpu, M37710_E);		break;
-		case CPUINFO_INT_REGISTER + M37710_NMI_STATE:	info->i = m37710_get_reg(m37710i_cpu, M37710_NMI_STATE); break;
-		case CPUINFO_INT_REGISTER + M37710_IRQ_STATE:	info->i = m37710_get_reg(m37710i_cpu, M37710_IRQ_STATE); break;
+		case CPUINFO_INT_REGISTER + M37710_PC:			info->i = m37710_get_reg(cpustate, M37710_PC);	break;
+		case CPUINFO_INT_REGISTER + M37710_S:			info->i = m37710_get_reg(cpustate, M37710_S);		break;
+		case CPUINFO_INT_REGISTER + M37710_P:			info->i = m37710_get_reg(cpustate, M37710_P) | (cpustate->ipl<<8); break;
+		case CPUINFO_INT_REGISTER + M37710_A:			info->i = m37710_get_reg(cpustate, M37710_A);		break;
+		case CPUINFO_INT_REGISTER + M37710_B:			info->i = m37710_get_reg(cpustate, M37710_B);		break;
+		case CPUINFO_INT_REGISTER + M37710_X:			info->i = m37710_get_reg(cpustate, M37710_X);		break;
+		case CPUINFO_INT_REGISTER + M37710_Y:			info->i = m37710_get_reg(cpustate, M37710_Y);		break;
+		case CPUINFO_INT_REGISTER + M37710_PB:			info->i = m37710_get_reg(cpustate, M37710_PB);	break;
+		case CPUINFO_INT_REGISTER + M37710_DB:			info->i = m37710_get_reg(cpustate, M37710_DB);	break;
+		case CPUINFO_INT_REGISTER + M37710_D:			info->i = m37710_get_reg(cpustate, M37710_D);		break;
+		case CPUINFO_INT_REGISTER + M37710_E:			info->i = m37710_get_reg(cpustate, M37710_E);		break;
+		case CPUINFO_INT_REGISTER + M37710_NMI_STATE:	info->i = m37710_get_reg(cpustate, M37710_NMI_STATE); break;
+		case CPUINFO_INT_REGISTER + M37710_IRQ_STATE:	info->i = m37710_get_reg(cpustate, M37710_IRQ_STATE); break;
 
 		/* --- the following bits of info are returned as pointers to data or functions --- */
 		case CPUINFO_PTR_SET_INFO:						info->setinfo = CPU_SET_INFO_NAME(m37710);		break;
@@ -1132,7 +1131,7 @@ CPU_GET_INFO( m37710 )
 		case CPUINFO_PTR_EXECUTE:						info->execute = CPU_EXECUTE_NAME(m37710);			break;
 		case CPUINFO_PTR_BURN:							info->burn = NULL;						break;
 		case CPUINFO_PTR_DISASSEMBLE:					info->disassemble = CPU_DISASSEMBLE_NAME(m37710);		break;
-		case CPUINFO_PTR_INSTRUCTION_COUNTER:			info->icount = &m37710i_cpu->ICount;			break;
+		case CPUINFO_PTR_INSTRUCTION_COUNTER:			info->icount = &cpustate->ICount;			break;
 
 		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(m37710_internal_map); break;
 		case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA:    info->internal_map16 = NULL;	break;
@@ -1147,36 +1146,36 @@ CPU_GET_INFO( m37710 )
 
 		case CPUINFO_STR_FLAGS:
 			sprintf(info->s, "%c%c%c%c%c%c%c%c",
-				m37710i_cpu->flag_n & NFLAG_SET ? 'N':'.',
-				m37710i_cpu->flag_v & VFLAG_SET ? 'V':'.',
-				m37710i_cpu->flag_m & MFLAG_SET ? 'M':'.',
-				m37710i_cpu->flag_x & XFLAG_SET ? 'X':'.',
-				m37710i_cpu->flag_d & DFLAG_SET ? 'D':'.',
-				m37710i_cpu->flag_i & IFLAG_SET ? 'I':'.',
-				m37710i_cpu->flag_z == 0        ? 'Z':'.',
-				m37710i_cpu->flag_c & CFLAG_SET ? 'C':'.');
+				cpustate->flag_n & NFLAG_SET ? 'N':'.',
+				cpustate->flag_v & VFLAG_SET ? 'V':'.',
+				cpustate->flag_m & MFLAG_SET ? 'M':'.',
+				cpustate->flag_x & XFLAG_SET ? 'X':'.',
+				cpustate->flag_d & DFLAG_SET ? 'D':'.',
+				cpustate->flag_i & IFLAG_SET ? 'I':'.',
+				cpustate->flag_z == 0        ? 'Z':'.',
+				cpustate->flag_c & CFLAG_SET ? 'C':'.');
 			break;
 
-		case CPUINFO_STR_REGISTER + M37710_PC:			sprintf(info->s, "PC:%04X", m37710i_cpu->pc); break;
-		case CPUINFO_STR_REGISTER + M37710_PB:			sprintf(info->s, "PB:%02X", m37710i_cpu->pb>>16); break;
-		case CPUINFO_STR_REGISTER + M37710_DB:			sprintf(info->s, "DB:%02X", m37710i_cpu->db>>16); break;
-		case CPUINFO_STR_REGISTER + M37710_D:			sprintf(info->s, "D:%04X", m37710i_cpu->d); break;
-		case CPUINFO_STR_REGISTER + M37710_S:			sprintf(info->s, "S:%04X", m37710i_cpu->s); break;
+		case CPUINFO_STR_REGISTER + M37710_PC:			sprintf(info->s, "PC:%04X", cpustate->pc); break;
+		case CPUINFO_STR_REGISTER + M37710_PB:			sprintf(info->s, "PB:%02X", cpustate->pb>>16); break;
+		case CPUINFO_STR_REGISTER + M37710_DB:			sprintf(info->s, "DB:%02X", cpustate->db>>16); break;
+		case CPUINFO_STR_REGISTER + M37710_D:			sprintf(info->s, "D:%04X", cpustate->d); break;
+		case CPUINFO_STR_REGISTER + M37710_S:			sprintf(info->s, "S:%04X", cpustate->s); break;
 		case CPUINFO_STR_REGISTER + M37710_P:			sprintf(info->s, "P:%04X",
-																 (m37710i_cpu->flag_n&0x80)		|
-																((m37710i_cpu->flag_v>>1)&0x40)	|
-																m37710i_cpu->flag_m				|
-																m37710i_cpu->flag_x				|
-																m37710i_cpu->flag_d				|
-																m37710i_cpu->flag_i				|
-																((!m37710i_cpu->flag_z)<<1)		|
-																((m37710i_cpu->flag_c>>8)&1) | (m37710i_cpu->ipl<<8)); break;
-		case CPUINFO_STR_REGISTER + M37710_E:			sprintf(info->s, "E:%d", m37710i_cpu->flag_e); break;
-		case CPUINFO_STR_REGISTER + M37710_A:			sprintf(info->s, "A:%04X", m37710i_cpu->a | m37710i_cpu->b); break;
-		case CPUINFO_STR_REGISTER + M37710_B:			sprintf(info->s, "B:%04X", m37710i_cpu->ba | m37710i_cpu->bb); break;
-		case CPUINFO_STR_REGISTER + M37710_X:			sprintf(info->s, "X:%04X", m37710i_cpu->x); break;
-		case CPUINFO_STR_REGISTER + M37710_Y:			sprintf(info->s, "Y:%04X", m37710i_cpu->y); break;
-		case CPUINFO_STR_REGISTER + M37710_IRQ_STATE:	sprintf(info->s, "IRQ:%X", m37710i_cpu->line_irq); break;
+																 (cpustate->flag_n&0x80)		|
+																((cpustate->flag_v>>1)&0x40)	|
+																cpustate->flag_m				|
+																cpustate->flag_x				|
+																cpustate->flag_d				|
+																cpustate->flag_i				|
+																((!cpustate->flag_z)<<1)		|
+																((cpustate->flag_c>>8)&1) | (cpustate->ipl<<8)); break;
+		case CPUINFO_STR_REGISTER + M37710_E:			sprintf(info->s, "E:%d", cpustate->flag_e); break;
+		case CPUINFO_STR_REGISTER + M37710_A:			sprintf(info->s, "A:%04X", cpustate->a | cpustate->b); break;
+		case CPUINFO_STR_REGISTER + M37710_B:			sprintf(info->s, "B:%04X", cpustate->ba | cpustate->bb); break;
+		case CPUINFO_STR_REGISTER + M37710_X:			sprintf(info->s, "X:%04X", cpustate->x); break;
+		case CPUINFO_STR_REGISTER + M37710_Y:			sprintf(info->s, "Y:%04X", cpustate->y); break;
+		case CPUINFO_STR_REGISTER + M37710_IRQ_STATE:	sprintf(info->s, "IRQ:%X", cpustate->line_irq); break;
 	}
 }
 
diff --git a/src/emu/cpu/m37710/m37710.h b/src/emu/cpu/m37710/m37710.h
index d38ec7551a6..759d7a8bd40 100644
--- a/src/emu/cpu/m37710/m37710.h
+++ b/src/emu/cpu/m37710/m37710.h
@@ -100,12 +100,12 @@ void m37710_state_load(void *file);
 
 #undef M37710_CALL_DEBUGGER
 
-#define M37710_CALL_DEBUGGER(x) 		debugger_instruction_hook(m37710i_cpu->device, x)
-#define m37710_read_8(addr) 			memory_read_byte_16le(m37710i_cpu->program, addr)
-#define m37710_write_8(addr,data)		memory_write_byte_16le(m37710i_cpu->program, addr,data)
-#define m37710_read_8_immediate(A)		memory_read_byte_16le(m37710i_cpu->program, A)
-#define m37710_read_16(addr) 			memory_read_word_16le(m37710i_cpu->program, addr)
-#define m37710_write_16(addr,data)		memory_write_word_16le(m37710i_cpu->program, addr,data)
+#define M37710_CALL_DEBUGGER(x) 		debugger_instruction_hook(cpustate->device, x)
+#define m37710_read_8(addr) 			memory_read_byte_16le(cpustate->program, addr)
+#define m37710_write_8(addr,data)		memory_write_byte_16le(cpustate->program, addr,data)
+#define m37710_read_8_immediate(A)		memory_read_byte_16le(cpustate->program, A)
+#define m37710_read_16(addr) 			memory_read_word_16le(cpustate->program, addr)
+#define m37710_write_16(addr,data)		memory_write_word_16le(cpustate->program, addr,data)
 #define m37710_jumping(A)
 #define m37710_branching(A)
 
diff --git a/src/emu/cpu/m37710/m37710cm.h b/src/emu/cpu/m37710/m37710cm.h
index ea0033367e6..68e088e83f5 100644
--- a/src/emu/cpu/m37710/m37710cm.h
+++ b/src/emu/cpu/m37710/m37710cm.h
@@ -104,13 +104,13 @@ struct _m37710i_cpu_struct
 	const address_space *program;
 	const address_space *io;
 	uint stopped;		/* Sets how the CPU is stopped */
-	void (*const *opcodes)(m37710i_cpu_struct *m37710i_cpu);		/* opcodes with no prefix */
-	void (*const *opcodes42)(m37710i_cpu_struct *m37710i_cpu);	/* opcodes with 0x42 prefix */
-	void (*const *opcodes89)(m37710i_cpu_struct *m37710i_cpu);	/* opcodes with 0x89 prefix */
-	uint (*get_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum);
-	void (*set_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
-	void (*set_line)(m37710i_cpu_struct *m37710i_cpu, int line, int state);
-	int  (*execute)(m37710i_cpu_struct *m37710i_cpu, int cycles);
+	void (*const *opcodes)(m37710i_cpu_struct *cpustate);		/* opcodes with no prefix */
+	void (*const *opcodes42)(m37710i_cpu_struct *cpustate);	/* opcodes with 0x42 prefix */
+	void (*const *opcodes89)(m37710i_cpu_struct *cpustate);	/* opcodes with 0x89 prefix */
+	uint (*get_reg)(m37710i_cpu_struct *cpustate, int regnum);
+	void (*set_reg)(m37710i_cpu_struct *cpustate, int regnum, uint val);
+	void (*set_line)(m37710i_cpu_struct *cpustate, int line, int state);
+	int  (*execute)(m37710i_cpu_struct *cpustate, int cycles);
 
 	// on-board peripheral stuff
 	UINT8 m37710_regs[128];
@@ -122,51 +122,51 @@ struct _m37710i_cpu_struct
 extern uint m37710i_adc_tbl[];
 extern uint m37710i_sbc_tbl[];
 
-extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *m37710i_cpu);
-extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *m37710i_cpu);
-extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum);
-extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum, uint val);
-extern void (*const m37710i_set_line[])(m37710i_cpu_struct *m37710i_cpu,int line, int state);
-extern int (*const m37710i_execute[])(m37710i_cpu_struct *m37710i_cpu, int cycles);
+extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *cpustate);
+extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *cpustate);
+extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *cpustate);
+extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *cpustate,int regnum);
+extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *cpustate,int regnum, uint val);
+extern void (*const m37710i_set_line[])(m37710i_cpu_struct *cpustate,int line, int state);
+extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles);
 
-#define REG_A			m37710i_cpu->a		/* Accumulator */
-#define REG_B			m37710i_cpu->b		/* Accumulator hi byte */
-#define REG_BA			m37710i_cpu->ba		/* Secondary Accumulator */
-#define REG_BB			m37710i_cpu->bb		/* Secondary Accumulator hi byte */
-#define REG_X			m37710i_cpu->x		/* Index X Register */
-#define REG_Y			m37710i_cpu->y		/* Index Y Register */
-#define REG_S			m37710i_cpu->s		/* Stack Pointer */
-#define REG_PC			m37710i_cpu->pc		/* Program Counter */
-#define REG_PPC			m37710i_cpu->ppc		/* Previous Program Counter */
-#define REG_PB			m37710i_cpu->pb		/* Program Bank */
-#define REG_DB			m37710i_cpu->db		/* Data Bank */
-#define REG_D			m37710i_cpu->d		/* Direct Register */
-#define FLAG_M			m37710i_cpu->flag_m	/* Memory/Accumulator Select Flag */
-#define FLAG_X			m37710i_cpu->flag_x	/* Index Select Flag */
-#define FLAG_N			m37710i_cpu->flag_n	/* Negative Flag */
-#define FLAG_V			m37710i_cpu->flag_v	/* Overflow Flag */
-#define FLAG_D			m37710i_cpu->flag_d	/* Decimal Mode Flag */
-#define FLAG_I			m37710i_cpu->flag_i	/* Interrupt Mask Flag */
-#define FLAG_Z			m37710i_cpu->flag_z	/* Zero Flag (inverted) */
-#define FLAG_C			m37710i_cpu->flag_c	/* Carry Flag */
-#define LINE_IRQ		m37710i_cpu->line_irq	/* Status of the IRQ line */
-#define REG_IR			m37710i_cpu->ir		/* Instruction Register */
-#define REG_IM			m37710i_cpu->im		/* Immediate load value */
-#define REG_IM2			m37710i_cpu->im2		/* Immediate load target */
-#define REG_IM3			m37710i_cpu->im3		/* Immediate load target */
-#define REG_IM4			m37710i_cpu->im4		/* Immediate load target */
-#define INT_ACK			m37710i_cpu->int_ack	/* Interrupt Acknowledge function pointer */
-#define CLOCKS			m37710i_cpu->ICount		/* Clock cycles remaining */
-#define IRQ_DELAY		m37710i_cpu->irq_delay /* Delay 1 instruction before checking IRQ */
-#define CPU_STOPPED 	m37710i_cpu->stopped	/* Stopped status of the CPU */
+#define REG_A			cpustate->a		/* Accumulator */
+#define REG_B			cpustate->b		/* Accumulator hi byte */
+#define REG_BA			cpustate->ba		/* Secondary Accumulator */
+#define REG_BB			cpustate->bb		/* Secondary Accumulator hi byte */
+#define REG_X			cpustate->x		/* Index X Register */
+#define REG_Y			cpustate->y		/* Index Y Register */
+#define REG_S			cpustate->s		/* Stack Pointer */
+#define REG_PC			cpustate->pc		/* Program Counter */
+#define REG_PPC			cpustate->ppc		/* Previous Program Counter */
+#define REG_PB			cpustate->pb		/* Program Bank */
+#define REG_DB			cpustate->db		/* Data Bank */
+#define REG_D			cpustate->d		/* Direct Register */
+#define FLAG_M			cpustate->flag_m	/* Memory/Accumulator Select Flag */
+#define FLAG_X			cpustate->flag_x	/* Index Select Flag */
+#define FLAG_N			cpustate->flag_n	/* Negative Flag */
+#define FLAG_V			cpustate->flag_v	/* Overflow Flag */
+#define FLAG_D			cpustate->flag_d	/* Decimal Mode Flag */
+#define FLAG_I			cpustate->flag_i	/* Interrupt Mask Flag */
+#define FLAG_Z			cpustate->flag_z	/* Zero Flag (inverted) */
+#define FLAG_C			cpustate->flag_c	/* Carry Flag */
+#define LINE_IRQ		cpustate->line_irq	/* Status of the IRQ line */
+#define REG_IR			cpustate->ir		/* Instruction Register */
+#define REG_IM			cpustate->im		/* Immediate load value */
+#define REG_IM2			cpustate->im2		/* Immediate load target */
+#define REG_IM3			cpustate->im3		/* Immediate load target */
+#define REG_IM4			cpustate->im4		/* Immediate load target */
+#define INT_ACK			cpustate->int_ack	/* Interrupt Acknowledge function pointer */
+#define CLOCKS			cpustate->ICount		/* Clock cycles remaining */
+#define IRQ_DELAY		cpustate->irq_delay /* Delay 1 instruction before checking IRQ */
+#define CPU_STOPPED 	cpustate->stopped	/* Stopped status of the CPU */
 
-#define FTABLE_GET_REG	m37710i_cpu->get_reg
-#define FTABLE_SET_REG	m37710i_cpu->set_reg
-#define FTABLE_SET_LINE	m37710i_cpu->set_line
+#define FTABLE_GET_REG	cpustate->get_reg
+#define FTABLE_SET_REG	cpustate->set_reg
+#define FTABLE_SET_LINE	cpustate->set_line
 
-#define SRC  		m37710i_cpu->source		/* Source Operand */
-#define DST  		m37710i_cpu->destination	/* Destination Operand */
+#define SRC  		cpustate->source		/* Source Operand */
+#define DST  		cpustate->destination	/* Destination Operand */
 
 #define STOP_LEVEL_WAI	1
 #define STOP_LEVEL_STOP	2
@@ -176,15 +176,15 @@ extern int (*const m37710i_execute[])(m37710i_cpu_struct *m37710i_cpu, int cycle
 #define EXECUTION_MODE_M1X0	2
 #define EXECUTION_MODE_M1X1	3
 
-INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *m37710i_cpu, uint mode)
+INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode)
 {
-	m37710i_cpu->opcodes = m37710i_opcodes[mode];
-	m37710i_cpu->opcodes42 = m37710i_opcodes2[mode];
-	m37710i_cpu->opcodes89 = m37710i_opcodes3[mode];
+	cpustate->opcodes = m37710i_opcodes[mode];
+	cpustate->opcodes42 = m37710i_opcodes2[mode];
+	cpustate->opcodes89 = m37710i_opcodes3[mode];
 	FTABLE_GET_REG = m37710i_get_reg[mode];
 	FTABLE_SET_REG = m37710i_set_reg[mode];
 	FTABLE_SET_LINE = m37710i_set_line[mode];
-	m37710i_cpu->execute = m37710i_execute[mode];
+	cpustate->execute = m37710i_execute[mode];
 }
 
 /* ======================================================================== */
@@ -312,7 +312,7 @@ INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *m37710i_cpu, uint mod
 #define CFLAG_AS_1()	((FLAG_C>>8)&1)
 
 /* update IRQ state (internal use only) */
-void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu);
+void m37710i_update_irqs(m37710i_cpu_struct *cpustate);
 
 /* ======================================================================== */
 /* ================================== CPU ================================= */
diff --git a/src/emu/cpu/m37710/m37710op.h b/src/emu/cpu/m37710/m37710op.h
index a9585b71717..8dd36694f86 100644
--- a/src/emu/cpu/m37710/m37710op.h
+++ b/src/emu/cpu/m37710/m37710op.h
@@ -25,46 +25,46 @@
 
 #define ADDRESS_37710(A) ((A)&0xffffff)
 
-INLINE uint m37710i_read_8_normal(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_8_normal(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	return m37710_read_8(address);
 }
 
-INLINE uint m37710i_read_8_immediate(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_8_immediate(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	return m37710_read_8_immediate(address);
 }
 
-INLINE uint m37710i_read_8_direct(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_8_direct(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	return m37710_read_8(address);
 }
 
-INLINE void m37710i_write_8_normal(m37710i_cpu_struct *m37710i_cpu, uint address, uint value)
+INLINE void m37710i_write_8_normal(m37710i_cpu_struct *cpustate, uint address, uint value)
 {
 	address = ADDRESS_37710(address);
 	m37710_write_8(address, MAKE_UINT_8(value));
 }
 
-INLINE void m37710i_write_8_direct(m37710i_cpu_struct *m37710i_cpu, uint address, uint value)
+INLINE void m37710i_write_8_direct(m37710i_cpu_struct *cpustate, uint address, uint value)
 {
 	address = ADDRESS_37710(address);
 	m37710_write_8(address, MAKE_UINT_8(value));
 }
 
-INLINE uint m37710i_read_16_normal(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_16_normal(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	if (address & 1)
-		return m37710i_read_8_normal(m37710i_cpu, address) | m37710i_read_8_normal(m37710i_cpu, address+1)<<8;
+		return m37710i_read_8_normal(cpustate, address) | m37710i_read_8_normal(cpustate, address+1)<<8;
 	else
 		return m37710_read_16(address);
 }
 
-INLINE uint m37710i_read_16_immediate(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_16_immediate(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	if (address & 1)
@@ -73,7 +73,7 @@ INLINE uint m37710i_read_16_immediate(m37710i_cpu_struct *m37710i_cpu, uint addr
 		return m37710_read_16(address);
 }
 
-INLINE uint m37710i_read_16_direct(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_16_direct(m37710i_cpu_struct *cpustate, uint address)
 {
 	address = ADDRESS_37710(address);
 	if (address & 1)
@@ -82,7 +82,7 @@ INLINE uint m37710i_read_16_direct(m37710i_cpu_struct *m37710i_cpu, uint address
 		return m37710_read_16(address);
 }
 
-INLINE void m37710i_write_16_normal(m37710i_cpu_struct *m37710i_cpu, uint address, uint value)
+INLINE void m37710i_write_16_normal(m37710i_cpu_struct *cpustate, uint address, uint value)
 {
 	address = ADDRESS_37710(address);
 	if (address & 1)
@@ -94,7 +94,7 @@ INLINE void m37710i_write_16_normal(m37710i_cpu_struct *m37710i_cpu, uint addres
 		m37710_write_16(address, value);
 }
 
-INLINE void m37710i_write_16_direct(m37710i_cpu_struct *m37710i_cpu, uint address, uint value)
+INLINE void m37710i_write_16_direct(m37710i_cpu_struct *cpustate, uint address, uint value)
 {
 	address = ADDRESS_37710(address);
 	if (address & 1)
@@ -106,22 +106,22 @@ INLINE void m37710i_write_16_direct(m37710i_cpu_struct *m37710i_cpu, uint addres
 		m37710_write_16(address, value);
 }
 
-INLINE uint m37710i_read_24_normal(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_24_normal(m37710i_cpu_struct *cpustate, uint address)
 {
-	return	 m37710i_read_16_normal(m37710i_cpu, address)       |
-			(m37710i_read_8_normal(m37710i_cpu, address+2)<<16);
+	return	 m37710i_read_16_normal(cpustate, address)       |
+			(m37710i_read_8_normal(cpustate, address+2)<<16);
 }
 
-INLINE uint m37710i_read_24_immediate(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_24_immediate(m37710i_cpu_struct *cpustate, uint address)
 {
-	return	 m37710i_read_16_immediate(m37710i_cpu, address)       |
-			(m37710i_read_8_immediate(m37710i_cpu, address+2)<<16);
+	return	 m37710i_read_16_immediate(cpustate, address)       |
+			(m37710i_read_8_immediate(cpustate, address+2)<<16);
 }
 
-INLINE uint m37710i_read_24_direct(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE uint m37710i_read_24_direct(m37710i_cpu_struct *cpustate, uint address)
 {
-	return	 m37710i_read_16_direct(m37710i_cpu, address)         |
-			(m37710i_read_8_direct(m37710i_cpu, address+2)<<16);
+	return	 m37710i_read_16_direct(cpustate, address)         |
+			(m37710i_read_8_direct(cpustate, address+2)<<16);
 }
 
 
@@ -130,42 +130,42 @@ INLINE uint m37710i_read_24_direct(m37710i_cpu_struct *m37710i_cpu, uint address
 /* ================================= STACK ================================ */
 /* ======================================================================== */
 
-INLINE void m37710i_push_8(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_push_8(m37710i_cpu_struct *cpustate, uint value)
 {
-	m37710i_write_8_normal(m37710i_cpu, REG_S, value);
+	m37710i_write_8_normal(cpustate, REG_S, value);
 	REG_S = MAKE_UINT_16(REG_S-1);
 }
 
-INLINE uint m37710i_pull_8(m37710i_cpu_struct *m37710i_cpu)
+INLINE uint m37710i_pull_8(m37710i_cpu_struct *cpustate)
 {
 	REG_S = MAKE_UINT_16(REG_S+1);
-	return m37710i_read_8_normal(m37710i_cpu, REG_S);
+	return m37710i_read_8_normal(cpustate, REG_S);
 }
 
-INLINE void m37710i_push_16(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_push_16(m37710i_cpu_struct *cpustate, uint value)
 {
-	m37710i_push_8(m37710i_cpu, value>>8);
-	m37710i_push_8(m37710i_cpu, value&0xff);
+	m37710i_push_8(cpustate, value>>8);
+	m37710i_push_8(cpustate, value&0xff);
 }
 
-INLINE uint m37710i_pull_16(m37710i_cpu_struct *m37710i_cpu)
+INLINE uint m37710i_pull_16(m37710i_cpu_struct *cpustate)
 {
-	uint res = m37710i_pull_8(m37710i_cpu);
-	return res | (m37710i_pull_8(m37710i_cpu) << 8);
+	uint res = m37710i_pull_8(cpustate);
+	return res | (m37710i_pull_8(cpustate) << 8);
 }
 
-INLINE void m37710i_push_24(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_push_24(m37710i_cpu_struct *cpustate, uint value)
 {
-	m37710i_push_8(m37710i_cpu, value>>16);
-	m37710i_push_8(m37710i_cpu, (value>>8)&0xff);
-	m37710i_push_8(m37710i_cpu, value&0xff);
+	m37710i_push_8(cpustate, value>>16);
+	m37710i_push_8(cpustate, (value>>8)&0xff);
+	m37710i_push_8(cpustate, value&0xff);
 }
 
-INLINE uint m37710i_pull_24(m37710i_cpu_struct *m37710i_cpu)
+INLINE uint m37710i_pull_24(m37710i_cpu_struct *cpustate)
 {
-	uint res = m37710i_pull_8(m37710i_cpu);
-	res |= m37710i_pull_8(m37710i_cpu) << 8;
-	return res | (m37710i_pull_8(m37710i_cpu) << 16);
+	uint res = m37710i_pull_8(cpustate);
+	res |= m37710i_pull_8(cpustate) << 8;
+	return res | (m37710i_pull_8(cpustate) << 16);
 }
 
 
@@ -173,26 +173,26 @@ INLINE uint m37710i_pull_24(m37710i_cpu_struct *m37710i_cpu)
 /* ============================ PROGRAM COUNTER =========================== */
 /* ======================================================================== */
 
-INLINE void m37710i_jump_16(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE void m37710i_jump_16(m37710i_cpu_struct *cpustate, uint address)
 {
 	REG_PC = MAKE_UINT_16(address);
 	m37710i_jumping(REG_PC);
 }
 
-INLINE void m37710i_jump_24(m37710i_cpu_struct *m37710i_cpu, uint address)
+INLINE void m37710i_jump_24(m37710i_cpu_struct *cpustate, uint address)
 {
 	REG_PB = address&0xff0000;
 	REG_PC = MAKE_UINT_16(address);
 	m37710i_jumping(REG_PC);
 }
 
-INLINE void m37710i_branch_8(m37710i_cpu_struct *m37710i_cpu, uint offset)
+INLINE void m37710i_branch_8(m37710i_cpu_struct *cpustate, uint offset)
 {
 	REG_PC = MAKE_UINT_16(REG_PC + MAKE_INT_8(offset));
 	m37710i_branching(REG_PC);
 }
 
-INLINE void m37710i_branch_16(m37710i_cpu_struct *m37710i_cpu, uint offset)
+INLINE void m37710i_branch_16(m37710i_cpu_struct *cpustate, uint offset)
 {
 	REG_PC = MAKE_UINT_16(REG_PC + offset);
 	m37710i_branching(REG_PC);
@@ -206,7 +206,7 @@ INLINE void m37710i_branch_16(m37710i_cpu_struct *m37710i_cpu, uint offset)
 /* note: difference from 65816.  when switching to 8-bit X/Y, X and Y are *not* truncated
    to 8 bits! */
 
-INLINE void m37710i_set_flag_mx(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_set_flag_mx(m37710i_cpu_struct *cpustate, uint value)
 {
 #if FLAG_SET_M
 	if(!(value & FLAGPOS_M))
@@ -238,11 +238,11 @@ INLINE void m37710i_set_flag_mx(m37710i_cpu_struct *m37710i_cpu, uint value)
 		FLAG_X = XFLAG_SET;
 	}
 #endif
-	m37710i_set_execution_mode(m37710i_cpu, (FLAG_M>>4) | (FLAG_X>>4));
+	m37710i_set_execution_mode(cpustate, (FLAG_M>>4) | (FLAG_X>>4));
 }
 
 
-INLINE void m37710i_set_flag_i(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_set_flag_i(m37710i_cpu_struct *cpustate, uint value)
 {
 	value &= FLAGPOS_I;
 	if(!FLAG_I || value)
@@ -257,7 +257,7 @@ INLINE void m37710i_set_flag_i(m37710i_cpu_struct *m37710i_cpu, uint value)
 
 
 /* Get the Processor Status Register */
-INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
+INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate)
 {
 	return	(FLAG_N&0x80)		|
 			((FLAG_V>>1)&0x40)	|
@@ -269,49 +269,49 @@ INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
 			((FLAG_C>>8)&1);
 }
 
-INLINE void m37710i_set_reg_p(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_set_reg_p(m37710i_cpu_struct *cpustate, uint value)
 {
 	FLAG_N = value;
 	FLAG_V = value << 1;
 	FLAG_D = value & FLAGPOS_D;
 	FLAG_Z = !(value & FLAGPOS_Z);
 	FLAG_C = value << 8;
-	m37710i_set_flag_mx(m37710i_cpu, value);
-	m37710i_set_flag_i(m37710i_cpu, value);
+	m37710i_set_flag_mx(cpustate, value);
+	m37710i_set_flag_i(cpustate, value);
 }
 
-INLINE void m37710i_set_reg_ipl(m37710i_cpu_struct *m37710i_cpu, uint value)
+INLINE void m37710i_set_reg_ipl(m37710i_cpu_struct *cpustate, uint value)
 {
-	m37710i_cpu->ipl = value & 7;
+	cpustate->ipl = value & 7;
 }
 
 /* ======================================================================== */
 /* =============================== INTERRUPTS ============================= */
 /* ======================================================================== */
 
-INLINE void m37710i_interrupt_hardware(m37710i_cpu_struct *m37710i_cpu, uint vector)
+INLINE void m37710i_interrupt_hardware(m37710i_cpu_struct *cpustate, uint vector)
 {
 	CLK(8);
-	m37710i_push_8(m37710i_cpu, REG_PB>>16);
-	m37710i_push_16(m37710i_cpu, REG_PC);
-	m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+	m37710i_push_8(cpustate, REG_PB>>16);
+	m37710i_push_16(cpustate, REG_PC);
+	m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 	FLAG_D = DFLAG_CLEAR;
-	m37710i_set_flag_i(m37710i_cpu, IFLAG_SET);
+	m37710i_set_flag_i(cpustate, IFLAG_SET);
 	REG_PB = 0;
-	m37710i_jump_16(m37710i_cpu, m37710i_read_16_normal(m37710i_cpu, vector));
-	if(INT_ACK) INT_ACK(m37710i_cpu->device, 0);
+	m37710i_jump_16(cpustate, m37710i_read_16_normal(cpustate, vector));
+	if(INT_ACK) INT_ACK(cpustate->device, 0);
 }
 
-INLINE void m37710i_interrupt_software(m37710i_cpu_struct *m37710i_cpu, uint vector)
+INLINE void m37710i_interrupt_software(m37710i_cpu_struct *cpustate, uint vector)
 {
 	CLK(8);
-	m37710i_push_8(m37710i_cpu, REG_PB>>16);
-	m37710i_push_16(m37710i_cpu, REG_PC);
-	m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+	m37710i_push_8(cpustate, REG_PB>>16);
+	m37710i_push_16(cpustate, REG_PC);
+	m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 	FLAG_D = DFLAG_CLEAR;
-	m37710i_set_flag_i(m37710i_cpu, IFLAG_SET);
+	m37710i_set_flag_i(cpustate, IFLAG_SET);
 	REG_PB = 0;
-	m37710i_jump_16(m37710i_cpu, m37710i_read_16_normal(m37710i_cpu, vector));
+	m37710i_jump_16(cpustate, m37710i_read_16_normal(cpustate, vector));
 }
 
 /* ======================================================================== */
@@ -319,191 +319,191 @@ INLINE void m37710i_interrupt_software(m37710i_cpu_struct *m37710i_cpu, uint vec
 /* ======================================================================== */
 
 /* Effective-address based memory access macros */
-#define read_8_NORM(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_IMM(A)		m37710i_read_8_immediate(m37710i_cpu, A)
-#define read_8_D(A)	   	m37710i_read_8_direct(m37710i_cpu, A)
-#define read_8_A(A)	   	m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_AL(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DX(A)		m37710i_read_8_direct(m37710i_cpu, A)
-#define read_8_DY(A)		m37710i_read_8_direct(m37710i_cpu, A)
-#define read_8_AX(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_ALX(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_AY(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DLI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_AI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_ALI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DXI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DIY(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_DLIY(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_AXI(A)		m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_S(A)	   	m37710i_read_8_normal(m37710i_cpu, A)
-#define read_8_SIY(A)		m37710i_read_8_normal(m37710i_cpu, A)
+#define read_8_NORM(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_IMM(A)		m37710i_read_8_immediate(cpustate, A)
+#define read_8_D(A)	   	m37710i_read_8_direct(cpustate, A)
+#define read_8_A(A)	   	m37710i_read_8_normal(cpustate, A)
+#define read_8_AL(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DX(A)		m37710i_read_8_direct(cpustate, A)
+#define read_8_DY(A)		m37710i_read_8_direct(cpustate, A)
+#define read_8_AX(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_ALX(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_AY(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DLI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_AI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_ALI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DXI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DIY(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_DLIY(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_AXI(A)		m37710i_read_8_normal(cpustate, A)
+#define read_8_S(A)	   	m37710i_read_8_normal(cpustate, A)
+#define read_8_SIY(A)		m37710i_read_8_normal(cpustate, A)
 
-#define read_16_NORM(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_IMM(A)		m37710i_read_16_immediate(m37710i_cpu, A)
-#define read_16_D(A)		m37710i_read_16_direct(m37710i_cpu, A)
-#define read_16_A(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_AL(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DX(A)		m37710i_read_16_direct(m37710i_cpu, A)
-#define read_16_DY(A)		m37710i_read_16_direct(m37710i_cpu, A)
-#define read_16_AX(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_ALX(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_AY(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DLI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_AI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_ALI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DXI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DIY(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_DLIY(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_AXI(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_S(A)		m37710i_read_16_normal(m37710i_cpu, A)
-#define read_16_SIY(A)		m37710i_read_16_normal(m37710i_cpu, A)
+#define read_16_NORM(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_IMM(A)		m37710i_read_16_immediate(cpustate, A)
+#define read_16_D(A)		m37710i_read_16_direct(cpustate, A)
+#define read_16_A(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_AL(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DX(A)		m37710i_read_16_direct(cpustate, A)
+#define read_16_DY(A)		m37710i_read_16_direct(cpustate, A)
+#define read_16_AX(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_ALX(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_AY(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DLI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_AI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_ALI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DXI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DIY(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_DLIY(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_AXI(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_S(A)		m37710i_read_16_normal(cpustate, A)
+#define read_16_SIY(A)		m37710i_read_16_normal(cpustate, A)
 
-#define read_24_NORM(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_IMM(A)		m37710i_read_24_immediate(m37710i_cpu, A)
-#define read_24_D(A)		m37710i_read_24_direct(m37710i_cpu, A)
-#define read_24_A(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_AL(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DX(A)		m37710i_read_24_direct(m37710i_cpu, A)
-#define read_24_DY(A)		m37710i_read_24_direct(m37710i_cpu, A)
-#define read_24_AX(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_ALX(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_AY(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DLI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_AI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_ALI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DXI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DIY(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_DLIY(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_AXI(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_S(A)		m37710i_read_24_normal(m37710i_cpu, A)
-#define read_24_SIY(A)		m37710i_read_24_normal(m37710i_cpu, A)
+#define read_24_NORM(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_IMM(A)		m37710i_read_24_immediate(cpustate, A)
+#define read_24_D(A)		m37710i_read_24_direct(cpustate, A)
+#define read_24_A(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_AL(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DX(A)		m37710i_read_24_direct(cpustate, A)
+#define read_24_DY(A)		m37710i_read_24_direct(cpustate, A)
+#define read_24_AX(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_ALX(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_AY(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DLI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_AI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_ALI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DXI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DIY(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_DLIY(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_AXI(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_S(A)		m37710i_read_24_normal(cpustate, A)
+#define read_24_SIY(A)		m37710i_read_24_normal(cpustate, A)
 
-#define write_8_NORM(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_D(A, V)		m37710i_write_8_direct(m37710i_cpu, A, V)
-#define write_8_A(A, V)		m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_AL(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DX(A, V)	m37710i_write_8_direct(m37710i_cpu, A, V)
-#define write_8_DY(A, V)	m37710i_write_8_direct(m37710i_cpu, A, V)
-#define write_8_AX(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_ALX(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_AY(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DLI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_AI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_ALI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DXI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DIY(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_DLIY(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_AXI(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_S(A, V)		m37710i_write_8_normal(m37710i_cpu, A, V)
-#define write_8_SIY(A, V)	m37710i_write_8_normal(m37710i_cpu, A, V)
+#define write_8_NORM(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_D(A, V)		m37710i_write_8_direct(cpustate, A, V)
+#define write_8_A(A, V)		m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AL(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DX(A, V)	m37710i_write_8_direct(cpustate, A, V)
+#define write_8_DY(A, V)	m37710i_write_8_direct(cpustate, A, V)
+#define write_8_AX(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_ALX(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AY(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DLI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_ALI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DXI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DIY(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_DLIY(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_AXI(A, V)	m37710i_write_8_normal(cpustate, A, V)
+#define write_8_S(A, V)		m37710i_write_8_normal(cpustate, A, V)
+#define write_8_SIY(A, V)	m37710i_write_8_normal(cpustate, A, V)
 
-#define write_16_NORM(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_D(A, V)	m37710i_write_16_direct(m37710i_cpu, A, V)
-#define write_16_A(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_AL(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DX(A, V)	m37710i_write_16_direct(m37710i_cpu, A, V)
-#define write_16_DY(A, V)	m37710i_write_16_direct(m37710i_cpu, A, V)
-#define write_16_AX(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_ALX(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_AY(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DLI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_AI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_ALI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DXI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DIY(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_DLIY(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_AXI(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_S(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
-#define write_16_SIY(A, V)	m37710i_write_16_normal(m37710i_cpu, A, V)
+#define write_16_NORM(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_D(A, V)	m37710i_write_16_direct(cpustate, A, V)
+#define write_16_A(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AL(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DX(A, V)	m37710i_write_16_direct(cpustate, A, V)
+#define write_16_DY(A, V)	m37710i_write_16_direct(cpustate, A, V)
+#define write_16_AX(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_ALX(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AY(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DLI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_ALI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DXI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DIY(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_DLIY(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_AXI(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_S(A, V)	m37710i_write_16_normal(cpustate, A, V)
+#define write_16_SIY(A, V)	m37710i_write_16_normal(cpustate, A, V)
 
 
-#define OPER_8_IMM(m37710i_cpu)		read_8_IMM(EA_IMM8(m37710i_cpu))
-#define OPER_8_D(m37710i_cpu)		read_8_D(EA_D(m37710i_cpu))
-#define OPER_8_A(m37710i_cpu)		read_8_A(EA_A(m37710i_cpu))
-#define OPER_8_AL(m37710i_cpu)		read_8_AL(EA_AL(m37710i_cpu))
-#define OPER_8_DX(m37710i_cpu)		read_8_DX(EA_DX(m37710i_cpu))
-#define OPER_8_DY(m37710i_cpu)		read_8_DY(EA_DY(m37710i_cpu))
-#define OPER_8_AX(m37710i_cpu)		read_8_AX(EA_AX(m37710i_cpu))
-#define OPER_8_ALX(m37710i_cpu)		read_8_ALX(EA_ALX(m37710i_cpu))
-#define OPER_8_AY(m37710i_cpu)		read_8_AY(EA_AY(m37710i_cpu))
-#define OPER_8_DI(m37710i_cpu)		read_8_DI(EA_DI(m37710i_cpu))
-#define OPER_8_DLI(m37710i_cpu)		read_8_DLI(EA_DLI(m37710i_cpu))
-#define OPER_8_AI(m37710i_cpu)		read_8_AI(EA_AI(m37710i_cpu))
-#define OPER_8_ALI(m37710i_cpu)		read_8_ALI(EA_ALI(m37710i_cpu))
-#define OPER_8_DXI(m37710i_cpu)		read_8_DXI(EA_DXI(m37710i_cpu))
-#define OPER_8_DIY(m37710i_cpu)		read_8_DIY(EA_DIY(m37710i_cpu))
-#define OPER_8_DLIY(m37710i_cpu)	read_8_DLIY(EA_DLIY(m37710i_cpu))
-#define OPER_8_AXI(m37710i_cpu)		read_8_AXI(EA_AXI(m37710i_cpu))
-#define OPER_8_S(m37710i_cpu)		read_8_S(EA_S(m37710i_cpu))
-#define OPER_8_SIY(m37710i_cpu)		read_8_SIY(EA_SIY(m37710i_cpu))
+#define OPER_8_IMM(cpustate)		read_8_IMM(EA_IMM8(cpustate))
+#define OPER_8_D(cpustate)		read_8_D(EA_D(cpustate))
+#define OPER_8_A(cpustate)		read_8_A(EA_A(cpustate))
+#define OPER_8_AL(cpustate)		read_8_AL(EA_AL(cpustate))
+#define OPER_8_DX(cpustate)		read_8_DX(EA_DX(cpustate))
+#define OPER_8_DY(cpustate)		read_8_DY(EA_DY(cpustate))
+#define OPER_8_AX(cpustate)		read_8_AX(EA_AX(cpustate))
+#define OPER_8_ALX(cpustate)		read_8_ALX(EA_ALX(cpustate))
+#define OPER_8_AY(cpustate)		read_8_AY(EA_AY(cpustate))
+#define OPER_8_DI(cpustate)		read_8_DI(EA_DI(cpustate))
+#define OPER_8_DLI(cpustate)		read_8_DLI(EA_DLI(cpustate))
+#define OPER_8_AI(cpustate)		read_8_AI(EA_AI(cpustate))
+#define OPER_8_ALI(cpustate)		read_8_ALI(EA_ALI(cpustate))
+#define OPER_8_DXI(cpustate)		read_8_DXI(EA_DXI(cpustate))
+#define OPER_8_DIY(cpustate)		read_8_DIY(EA_DIY(cpustate))
+#define OPER_8_DLIY(cpustate)	read_8_DLIY(EA_DLIY(cpustate))
+#define OPER_8_AXI(cpustate)		read_8_AXI(EA_AXI(cpustate))
+#define OPER_8_S(cpustate)		read_8_S(EA_S(cpustate))
+#define OPER_8_SIY(cpustate)		read_8_SIY(EA_SIY(cpustate))
 
-#define OPER_16_IMM(m37710i_cpu)	read_16_IMM(EA_IMM16(m37710i_cpu))
-#define OPER_16_D(m37710i_cpu)		read_16_D(EA_D(m37710i_cpu))
-#define OPER_16_A(m37710i_cpu)		read_16_A(EA_A(m37710i_cpu))
-#define OPER_16_AL(m37710i_cpu)		read_16_AL(EA_AL(m37710i_cpu))
-#define OPER_16_DX(m37710i_cpu)		read_16_DX(EA_DX(m37710i_cpu))
-#define OPER_16_DY(m37710i_cpu)		read_16_DY(EA_DY(m37710i_cpu))
-#define OPER_16_AX(m37710i_cpu)		read_16_AX(EA_AX(m37710i_cpu))
-#define OPER_16_ALX(m37710i_cpu)	read_16_ALX(EA_ALX(m37710i_cpu))
-#define OPER_16_AY(m37710i_cpu)		read_16_AY(EA_AY(m37710i_cpu))
-#define OPER_16_DI(m37710i_cpu)		read_16_DI(EA_DI(m37710i_cpu))
-#define OPER_16_DLI(m37710i_cpu)	read_16_DLI(EA_DLI(m37710i_cpu))
-#define OPER_16_AI(m37710i_cpu)		read_16_AI(EA_AI(m37710i_cpu))
-#define OPER_16_ALI(m37710i_cpu)	read_16_ALI(EA_ALI(m37710i_cpu))
-#define OPER_16_DXI(m37710i_cpu)	read_16_DXI(EA_DXI(m37710i_cpu))
-#define OPER_16_DIY(m37710i_cpu)	read_16_DIY(EA_DIY(m37710i_cpu))
-#define OPER_16_DLIY(m37710i_cpu)	read_16_DLIY(EA_DLIY(m37710i_cpu))
-#define OPER_16_AXI(m37710i_cpu)	read_16_AXI(EA_AXI(m37710i_cpu))
-#define OPER_16_S(m37710i_cpu)		read_16_S(EA_S(m37710i_cpu))
-#define OPER_16_SIY(m37710i_cpu)	read_16_SIY(EA_SIY(m37710i_cpu))
+#define OPER_16_IMM(cpustate)	read_16_IMM(EA_IMM16(cpustate))
+#define OPER_16_D(cpustate)		read_16_D(EA_D(cpustate))
+#define OPER_16_A(cpustate)		read_16_A(EA_A(cpustate))
+#define OPER_16_AL(cpustate)		read_16_AL(EA_AL(cpustate))
+#define OPER_16_DX(cpustate)		read_16_DX(EA_DX(cpustate))
+#define OPER_16_DY(cpustate)		read_16_DY(EA_DY(cpustate))
+#define OPER_16_AX(cpustate)		read_16_AX(EA_AX(cpustate))
+#define OPER_16_ALX(cpustate)	read_16_ALX(EA_ALX(cpustate))
+#define OPER_16_AY(cpustate)		read_16_AY(EA_AY(cpustate))
+#define OPER_16_DI(cpustate)		read_16_DI(EA_DI(cpustate))
+#define OPER_16_DLI(cpustate)	read_16_DLI(EA_DLI(cpustate))
+#define OPER_16_AI(cpustate)		read_16_AI(EA_AI(cpustate))
+#define OPER_16_ALI(cpustate)	read_16_ALI(EA_ALI(cpustate))
+#define OPER_16_DXI(cpustate)	read_16_DXI(EA_DXI(cpustate))
+#define OPER_16_DIY(cpustate)	read_16_DIY(EA_DIY(cpustate))
+#define OPER_16_DLIY(cpustate)	read_16_DLIY(EA_DLIY(cpustate))
+#define OPER_16_AXI(cpustate)	read_16_AXI(EA_AXI(cpustate))
+#define OPER_16_S(cpustate)		read_16_S(EA_S(cpustate))
+#define OPER_16_SIY(cpustate)	read_16_SIY(EA_SIY(cpustate))
 
-#define OPER_24_IMM(m37710i_cpu)	read_24_IMM(EA_IMM24(m37710i_cpu))
-#define OPER_24_D(m37710i_cpu)		read_24_D(EA_D(m37710i_cpu))
-#define OPER_24_A(m37710i_cpu)		read_24_A(EA_A(m37710i_cpu))
-#define OPER_24_AL(m37710i_cpu)		read_24_AL(EA_AL(m37710i_cpu))
-#define OPER_24_DX(m37710i_cpu)		read_24_DX(EA_DX(m37710i_cpu))
-#define OPER_24_DY(m37710i_cpu)		read_24_DY(EA_DY(m37710i_cpu))
-#define OPER_24_AX(m37710i_cpu)		read_24_AX(EA_AX(m37710i_cpu))
-#define OPER_24_ALX(m37710i_cpu)	read_24_ALX(EA_ALX(m37710i_cpu))
-#define OPER_24_AY(m37710i_cpu)		read_24_AY(EA_AY(m37710i_cpu))
-#define OPER_24_DI(m37710i_cpu)		read_24_DI(EA_DI(m37710i_cpu))
-#define OPER_24_DLI(m37710i_cpu)	read_24_DLI(EA_DLI(m37710i_cpu))
-#define OPER_24_AI(m37710i_cpu)		read_24_AI(EA_AI(m37710i_cpu))
-#define OPER_24_ALI(m37710i_cpu)	read_24_ALI(EA_ALI())
-#define OPER_24_DXI(m37710i_cpu)	read_24_DXI(EA_DXI(m37710i_cpu))
-#define OPER_24_DIY(m37710i_cpu)	read_24_DIY(EA_DIY(m37710i_cpu))
-#define OPER_24_DLIY(m37710i_cpu)	read_24_DLIY(EA_DLIY(m37710i_cpu))
-#define OPER_24_AXI(m37710i_cpu)	read_24_AXI(EA_AXI(m37710i_cpu))
-#define OPER_24_S(m37710i_cpu)	  	read_24_S(EA_S(m37710i_cpu))
-#define OPER_24_SIY(m37710i_cpu)	read_24_SIY(EA_SIY(m37710i_cpu))
+#define OPER_24_IMM(cpustate)	read_24_IMM(EA_IMM24(cpustate))
+#define OPER_24_D(cpustate)		read_24_D(EA_D(cpustate))
+#define OPER_24_A(cpustate)		read_24_A(EA_A(cpustate))
+#define OPER_24_AL(cpustate)		read_24_AL(EA_AL(cpustate))
+#define OPER_24_DX(cpustate)		read_24_DX(EA_DX(cpustate))
+#define OPER_24_DY(cpustate)		read_24_DY(EA_DY(cpustate))
+#define OPER_24_AX(cpustate)		read_24_AX(EA_AX(cpustate))
+#define OPER_24_ALX(cpustate)	read_24_ALX(EA_ALX(cpustate))
+#define OPER_24_AY(cpustate)		read_24_AY(EA_AY(cpustate))
+#define OPER_24_DI(cpustate)		read_24_DI(EA_DI(cpustate))
+#define OPER_24_DLI(cpustate)	read_24_DLI(EA_DLI(cpustate))
+#define OPER_24_AI(cpustate)		read_24_AI(EA_AI(cpustate))
+#define OPER_24_ALI(cpustate)	read_24_ALI(EA_ALI())
+#define OPER_24_DXI(cpustate)	read_24_DXI(EA_DXI(cpustate))
+#define OPER_24_DIY(cpustate)	read_24_DIY(EA_DIY(cpustate))
+#define OPER_24_DLIY(cpustate)	read_24_DLIY(EA_DLIY(cpustate))
+#define OPER_24_AXI(cpustate)	read_24_AXI(EA_AXI(cpustate))
+#define OPER_24_S(cpustate)	  	read_24_S(EA_S(cpustate))
+#define OPER_24_SIY(cpustate)	read_24_SIY(EA_SIY(cpustate))
 
-INLINE uint EA_IMM8(m37710i_cpu_struct *m37710i_cpu)  {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);}
-INLINE uint EA_IMM16(m37710i_cpu_struct *m37710i_cpu) {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);}
-INLINE uint EA_IMM24(m37710i_cpu_struct *m37710i_cpu) {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);}
-INLINE uint EA_D(m37710i_cpu_struct *m37710i_cpu)     {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM(m37710i_cpu));}
-INLINE uint EA_A(m37710i_cpu_struct *m37710i_cpu)     {return REG_DB | OPER_16_IMM(m37710i_cpu);}
-INLINE uint EA_AL(m37710i_cpu_struct *m37710i_cpu)    {return OPER_24_IMM(m37710i_cpu);}
-INLINE uint EA_DX(m37710i_cpu_struct *m37710i_cpu)    {return MAKE_UINT_16(REG_D + OPER_8_IMM(m37710i_cpu) + REG_X);}
-INLINE uint EA_DY(m37710i_cpu_struct *m37710i_cpu)    {return MAKE_UINT_16(REG_D + OPER_8_IMM(m37710i_cpu) + REG_Y);}
-INLINE uint EA_AX(m37710i_cpu_struct *m37710i_cpu)    {uint tmp = EA_A(m37710i_cpu); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;}
-INLINE uint EA_ALX(m37710i_cpu_struct *m37710i_cpu)   {return EA_AL(m37710i_cpu) + REG_X;}
-INLINE uint EA_AY(m37710i_cpu_struct *m37710i_cpu)    {uint tmp = EA_A(m37710i_cpu); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
-INLINE uint EA_DI(m37710i_cpu_struct *m37710i_cpu)    {return REG_DB | OPER_16_D(m37710i_cpu);}
-INLINE uint EA_DLI(m37710i_cpu_struct *m37710i_cpu)   {return OPER_24_D(m37710i_cpu);}
-INLINE uint EA_AI(m37710i_cpu_struct *m37710i_cpu)    {return read_16_A(OPER_16_IMM(m37710i_cpu));}
-INLINE uint EA_ALI(m37710i_cpu_struct *m37710i_cpu)   {return OPER_24_A(m37710i_cpu);}
-INLINE uint EA_DXI(m37710i_cpu_struct *m37710i_cpu)   {return REG_DB | OPER_16_DX(m37710i_cpu);}
-INLINE uint EA_DIY(m37710i_cpu_struct *m37710i_cpu)   {uint tmp = REG_DB | OPER_16_D(m37710i_cpu); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
-INLINE uint EA_DLIY(m37710i_cpu_struct *m37710i_cpu)  {return OPER_24_D(m37710i_cpu) + REG_Y;}
-INLINE uint EA_AXI(m37710i_cpu_struct *m37710i_cpu)   {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM(m37710i_cpu) + REG_X));}
-INLINE uint EA_S(m37710i_cpu_struct *m37710i_cpu)     {return MAKE_UINT_16(REG_S + OPER_8_IMM(m37710i_cpu));}
-INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM(m37710i_cpu)) + REG_Y) | REG_DB;}
+INLINE uint EA_IMM8(m37710i_cpu_struct *cpustate)  {REG_PC += 1; return REG_PB | MAKE_UINT_16(REG_PC-1);}
+INLINE uint EA_IMM16(m37710i_cpu_struct *cpustate) {REG_PC += 2; return REG_PB | MAKE_UINT_16(REG_PC-2);}
+INLINE uint EA_IMM24(m37710i_cpu_struct *cpustate) {REG_PC += 3; return REG_PB | MAKE_UINT_16(REG_PC-3);}
+INLINE uint EA_D(m37710i_cpu_struct *cpustate)     {if(MAKE_UINT_8(REG_D)) CLK(1); return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate));}
+INLINE uint EA_A(m37710i_cpu_struct *cpustate)     {return REG_DB | OPER_16_IMM(cpustate);}
+INLINE uint EA_AL(m37710i_cpu_struct *cpustate)    {return OPER_24_IMM(cpustate);}
+INLINE uint EA_DX(m37710i_cpu_struct *cpustate)    {return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate) + REG_X);}
+INLINE uint EA_DY(m37710i_cpu_struct *cpustate)    {return MAKE_UINT_16(REG_D + OPER_8_IMM(cpustate) + REG_Y);}
+INLINE uint EA_AX(m37710i_cpu_struct *cpustate)    {uint tmp = EA_A(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_X;}
+INLINE uint EA_ALX(m37710i_cpu_struct *cpustate)   {return EA_AL(cpustate) + REG_X;}
+INLINE uint EA_AY(m37710i_cpu_struct *cpustate)    {uint tmp = EA_A(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
+INLINE uint EA_DI(m37710i_cpu_struct *cpustate)    {return REG_DB | OPER_16_D(cpustate);}
+INLINE uint EA_DLI(m37710i_cpu_struct *cpustate)   {return OPER_24_D(cpustate);}
+INLINE uint EA_AI(m37710i_cpu_struct *cpustate)    {return read_16_A(OPER_16_IMM(cpustate));}
+INLINE uint EA_ALI(m37710i_cpu_struct *cpustate)   {return OPER_24_A(cpustate);}
+INLINE uint EA_DXI(m37710i_cpu_struct *cpustate)   {return REG_DB | OPER_16_DX(cpustate);}
+INLINE uint EA_DIY(m37710i_cpu_struct *cpustate)   {uint tmp = REG_DB | OPER_16_D(cpustate); if((tmp^(tmp+REG_X))&0xff00) CLK(1); return tmp + REG_Y;}
+INLINE uint EA_DLIY(m37710i_cpu_struct *cpustate)  {return OPER_24_D(cpustate) + REG_Y;}
+INLINE uint EA_AXI(m37710i_cpu_struct *cpustate)   {return read_16_AXI(MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X));}
+INLINE uint EA_S(m37710i_cpu_struct *cpustate)     {return MAKE_UINT_16(REG_S + OPER_8_IMM(cpustate));}
+INLINE uint EA_SIY(m37710i_cpu_struct *cpustate)   {return MAKE_UINT_16(read_16_SIY(REG_S + OPER_8_IMM(cpustate)) + REG_Y) | REG_DB;}
 
 
 /* ======================================================================== */
@@ -516,82 +516,82 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #if FLAG_SET_X
 #define OP_PSH(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x1)	\
-		m37710i_push_8(m37710i_cpu, REG_A);	\
+		m37710i_push_8(cpustate, REG_A);	\
 	if (SRC&0x2)	\
-		m37710i_push_8(m37710i_cpu, REG_BA);	\
+		m37710i_push_8(cpustate, REG_BA);	\
 	if (SRC&0x4)	\
-		m37710i_push_8(m37710i_cpu, REG_X);	\
+		m37710i_push_8(cpustate, REG_X);	\
 	if (SRC&0x8)	\
-		m37710i_push_8(m37710i_cpu, REG_Y);	\
+		m37710i_push_8(cpustate, REG_Y);	\
 	if (SRC&0x10)	\
-		m37710i_push_16(m37710i_cpu, REG_D);	\
+		m37710i_push_16(cpustate, REG_D);	\
 	if (SRC&0x20)	\
-		m37710i_push_8(m37710i_cpu, REG_DB>>16);	\
+		m37710i_push_8(cpustate, REG_DB>>16);	\
 	if (SRC&0x40)	\
-		m37710i_push_8(m37710i_cpu, REG_PB>>16);	\
+		m37710i_push_8(cpustate, REG_PB>>16);	\
 	if (SRC&0x80)	\
-		m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+		m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 #else	// FLAG_SET_X
 #define OP_PSH(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x1)	\
-		m37710i_push_8(m37710i_cpu, REG_A);	\
+		m37710i_push_8(cpustate, REG_A);	\
 	if (SRC&0x2)	\
-		m37710i_push_8(m37710i_cpu, REG_BA);	\
+		m37710i_push_8(cpustate, REG_BA);	\
 	if (SRC&0x4)	\
-		m37710i_push_16(m37710i_cpu, REG_X);	\
+		m37710i_push_16(cpustate, REG_X);	\
 	if (SRC&0x8)	\
-		m37710i_push_16(m37710i_cpu, REG_Y);	\
+		m37710i_push_16(cpustate, REG_Y);	\
 	if (SRC&0x10)	\
-		m37710i_push_16(m37710i_cpu, REG_D);	\
+		m37710i_push_16(cpustate, REG_D);	\
 	if (SRC&0x20)	\
-		m37710i_push_8(m37710i_cpu, REG_DB>>16);	\
+		m37710i_push_8(cpustate, REG_DB>>16);	\
 	if (SRC&0x40)	\
-		m37710i_push_8(m37710i_cpu, REG_PB>>16);	\
+		m37710i_push_8(cpustate, REG_PB>>16);	\
 	if (SRC&0x80)	\
-		m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+		m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 #endif	// FLAG_SET_X
 #else	// FLAG_SET_M
 #if FLAG_SET_X
 #define OP_PSH(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x1)	\
-		m37710i_push_16(m37710i_cpu, REG_A);	\
+		m37710i_push_16(cpustate, REG_A);	\
 	if (SRC&0x2)	\
-		m37710i_push_16(m37710i_cpu, REG_BA);	\
+		m37710i_push_16(cpustate, REG_BA);	\
 	if (SRC&0x4)	\
-		m37710i_push_8(m37710i_cpu, REG_X);	\
+		m37710i_push_8(cpustate, REG_X);	\
 	if (SRC&0x8)	\
-		m37710i_push_8(m37710i_cpu, REG_Y);	\
+		m37710i_push_8(cpustate, REG_Y);	\
 	if (SRC&0x10)	\
-		m37710i_push_16(m37710i_cpu, REG_D);	\
+		m37710i_push_16(cpustate, REG_D);	\
 	if (SRC&0x20)	\
-		m37710i_push_8(m37710i_cpu, REG_DB>>16);	\
+		m37710i_push_8(cpustate, REG_DB>>16);	\
 	if (SRC&0x40)	\
-		m37710i_push_8(m37710i_cpu, REG_PB>>16);	\
+		m37710i_push_8(cpustate, REG_PB>>16);	\
 	if (SRC&0x80)	\
-		m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+		m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 #else	// FLAG_SET_X
 #define OP_PSH(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x1)	\
-		m37710i_push_16(m37710i_cpu, REG_A);	\
+		m37710i_push_16(cpustate, REG_A);	\
 	if (SRC&0x2)	\
-		m37710i_push_16(m37710i_cpu, REG_BA);	\
+		m37710i_push_16(cpustate, REG_BA);	\
 	if (SRC&0x4)	\
-		m37710i_push_16(m37710i_cpu, REG_X);	\
+		m37710i_push_16(cpustate, REG_X);	\
 	if (SRC&0x8)	\
-		m37710i_push_16(m37710i_cpu, REG_Y);	\
+		m37710i_push_16(cpustate, REG_Y);	\
 	if (SRC&0x10)	\
-		m37710i_push_16(m37710i_cpu, REG_D);	\
+		m37710i_push_16(cpustate, REG_D);	\
 	if (SRC&0x20)	\
-		m37710i_push_8(m37710i_cpu, REG_DB>>16);	\
+		m37710i_push_8(cpustate, REG_DB>>16);	\
 	if (SRC&0x40)	\
-		m37710i_push_8(m37710i_cpu, REG_PB>>16);	\
+		m37710i_push_8(cpustate, REG_PB>>16);	\
 	if (SRC&0x80)	\
-		m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
+		m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
 #endif	// FLAG_SET_X
 #endif	// FLAG_SET_M
 
@@ -600,82 +600,82 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #if FLAG_SET_X
 #define OP_PUL(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x80)	\
-		m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));	\
+		m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));	\
 	if (SRC&0x40)	\
-		REG_PB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_PB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x20)	\
-		REG_DB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_DB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x10)	\
-		REG_D  = m37710i_pull_16(m37710i_cpu);	\
+		REG_D  = m37710i_pull_16(cpustate);	\
 	if (SRC&0x8)	\
-		REG_Y = m37710i_pull_8(m37710i_cpu);	\
+		REG_Y = m37710i_pull_8(cpustate);	\
 	if (SRC&0x4)	\
-		REG_X = m37710i_pull_8(m37710i_cpu);	\
+		REG_X = m37710i_pull_8(cpustate);	\
 	if (SRC&0x2)	\
-		REG_BA = m37710i_pull_8(m37710i_cpu);	\
+		REG_BA = m37710i_pull_8(cpustate);	\
 	if (SRC&0x1)	\
-		REG_A = m37710i_pull_8(m37710i_cpu);
+		REG_A = m37710i_pull_8(cpustate);
 #else
 #define OP_PUL(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x80)	\
-		m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));	\
+		m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));	\
 	if (SRC&0x40)	\
-		REG_PB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_PB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x20)	\
-		REG_DB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_DB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x10)	\
-		REG_D  = m37710i_pull_16(m37710i_cpu);	\
+		REG_D  = m37710i_pull_16(cpustate);	\
 	if (SRC&0x8)	\
-		REG_Y = m37710i_pull_16(m37710i_cpu);	\
+		REG_Y = m37710i_pull_16(cpustate);	\
 	if (SRC&0x4)	\
-		REG_X = m37710i_pull_16(m37710i_cpu);	\
+		REG_X = m37710i_pull_16(cpustate);	\
 	if (SRC&0x2)	\
-		REG_BA = m37710i_pull_8(m37710i_cpu);	\
+		REG_BA = m37710i_pull_8(cpustate);	\
 	if (SRC&0x1)	\
-		REG_A = m37710i_pull_8(m37710i_cpu);
+		REG_A = m37710i_pull_8(cpustate);
 #endif
 #else
 #if FLAG_SET_X
 #define OP_PUL(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x80)	\
-		m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));	\
+		m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));	\
 	if (SRC&0x40)	\
-		REG_PB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_PB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x20)	\
-		REG_DB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_DB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x10)	\
-		REG_D  = m37710i_pull_16(m37710i_cpu);	\
+		REG_D  = m37710i_pull_16(cpustate);	\
 	if (SRC&0x8)	\
-		REG_Y = m37710i_pull_8(m37710i_cpu);	\
+		REG_Y = m37710i_pull_8(cpustate);	\
 	if (SRC&0x4)	\
-		REG_X = m37710i_pull_8(m37710i_cpu);	\
+		REG_X = m37710i_pull_8(cpustate);	\
 	if (SRC&0x2)	\
-		REG_BA = m37710i_pull_16(m37710i_cpu);	\
+		REG_BA = m37710i_pull_16(cpustate);	\
 	if (SRC&0x1)	\
-		REG_A = m37710i_pull_16(m37710i_cpu);
+		REG_A = m37710i_pull_16(cpustate);
 #else
 #define OP_PUL(MODE)	\
-	SRC	= OPER_8_##MODE(m37710i_cpu);	\
+	SRC	= OPER_8_##MODE(cpustate);	\
 	if (SRC&0x80)	\
-		m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));	\
+		m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));	\
 	if (SRC&0x40)	\
-		REG_PB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_PB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x20)	\
-		REG_DB = m37710i_pull_8(m37710i_cpu) << 16;	\
+		REG_DB = m37710i_pull_8(cpustate) << 16;	\
 	if (SRC&0x10)	\
-		REG_D  = m37710i_pull_16(m37710i_cpu);	\
+		REG_D  = m37710i_pull_16(cpustate);	\
 	if (SRC&0x8)	\
-		REG_Y = m37710i_pull_16(m37710i_cpu);	\
+		REG_Y = m37710i_pull_16(cpustate);	\
 	if (SRC&0x4)	\
-		REG_X = m37710i_pull_16(m37710i_cpu);	\
+		REG_X = m37710i_pull_16(cpustate);	\
 	if (SRC&0x2)	\
-		REG_BA = m37710i_pull_16(m37710i_cpu);	\
+		REG_BA = m37710i_pull_16(cpustate);	\
 	if (SRC&0x1)	\
-		REG_A = m37710i_pull_16(m37710i_cpu);
+		REG_A = m37710i_pull_16(cpustate);
 #endif
 #endif
 
@@ -684,12 +684,12 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_MPY(MODE)														\
 	CLK(CLK_OP + CLK_R8 + CLK_##MODE);	\
-	SRC = OPER_8_##MODE(m37710i_cpu);			\
+	SRC = OPER_8_##MODE(cpustate);			\
 	{ int temp = SRC * REG_A;  REG_A = temp & 0xff; REG_BA = (temp>>8)&0xff; FLAG_Z = temp; FLAG_N = (temp & 0x8000) ? 1 : 0; FLAG_C = 0; }
 #else
 #define OP_MPY(MODE)														\
 	CLK(CLK_OP + CLK_R16 + CLK_##MODE);	\
-	SRC = OPER_16_##MODE(m37710i_cpu);			\
+	SRC = OPER_16_##MODE(cpustate);			\
 	{ int temp = SRC * REG_A;  REG_A = temp & 0xffff;  REG_BA = (temp>>16)&0xffff; FLAG_Z = temp; FLAG_N = (temp & 0x80000000) ? 1 : 0; FLAG_C = 0; }
 #endif
 
@@ -699,7 +699,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #define OP_DIV(MODE)	\
 	CLK(CLK_OP + CLK_R8 + CLK_##MODE + 25);	\
 	SRC = (REG_BA&0xff)<<8 | (REG_A & 0xff);	\
-	DST = OPER_8_##MODE(m37710i_cpu);			\
+	DST = OPER_8_##MODE(cpustate);			\
 	if (DST != 0) {	REG_A = SRC / DST; REG_BA = SRC % DST; SRC /= DST; }		\
 	FLAG_N = (SRC & 0x80) ? 1 : 0;	\
 	FLAG_Z = MAKE_UINT_8(SRC);	\
@@ -708,7 +708,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #define OP_DIV(MODE)	\
 	CLK(CLK_OP + CLK_R16 + CLK_##MODE + 25);	\
 	SRC = (REG_BA<<16) | REG_A;	\
-	DST = OPER_16_##MODE(m37710i_cpu);		\
+	DST = OPER_16_##MODE(cpustate);		\
 	if (DST != 0) { REG_A = SRC / DST; REG_BA = SRC % DST; SRC /= DST; }	\
 	FLAG_N = (SRC & 0x8000) ? 1 : 0;	\
 	FLAG_Z = SRC;	\
@@ -720,7 +720,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ADC(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			SRC    = OPER_8_##MODE(m37710i_cpu);										\
+			SRC    = OPER_8_##MODE(cpustate);										\
 			FLAG_C = REG_A + SRC + CFLAG_AS_1();						\
 			if(FLAG_D)														\
 			{																\
@@ -734,7 +734,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_ADC(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			SRC    = OPER_16_##MODE(m37710i_cpu);										\
+			SRC    = OPER_16_##MODE(cpustate);										\
 			if(!FLAG_D)														\
 			{																\
 				FLAG_C = REG_A + SRC + CFLAG_AS_1();						\
@@ -767,7 +767,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ADCB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			SRC    = OPER_8_##MODE(m37710i_cpu);										\
+			SRC    = OPER_8_##MODE(cpustate);										\
 			FLAG_C = REG_BA + SRC + CFLAG_AS_1();						\
 			if(FLAG_D)														\
 			{																\
@@ -781,7 +781,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_ADCB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			SRC    = OPER_16_##MODE(m37710i_cpu);										\
+			SRC    = OPER_16_##MODE(cpustate);										\
 			if(!FLAG_D)														\
 			{																\
 				FLAG_C = REG_BA + SRC + CFLAG_AS_1();						\
@@ -814,11 +814,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_AND(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_A &= OPER_8_##MODE(cpustate)
 #else
 #define OP_AND(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_A &= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_A &= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_A)
 #endif
 
@@ -827,11 +827,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ANDB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_BA &= OPER_8_##MODE(cpustate)
 #else
 #define OP_ANDB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_BA &= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_BA &= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_BA)
 #endif
 
@@ -872,14 +872,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ASLM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_C = read_8_##MODE(DST) << 1;								\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C);							\
 			write_8_##MODE(DST, FLAG_Z)
 #else
 #define OP_ASLM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_C = read_16_##MODE(DST) << 1;								\
 			FLAG_Z = MAKE_UINT_16(FLAG_C);									\
 			FLAG_N = NFLAG_16(FLAG_C);										\
@@ -890,11 +890,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 /* M37710   Branch on Condition Code */
 #undef OP_BCC
 #define OP_BCC(COND)														\
-			DST = OPER_8_IMM(m37710i_cpu);												\
+			DST = OPER_8_IMM(cpustate);												\
 			if(COND)														\
 			{																\
 				CLK(CLK_OP + CLK_RELATIVE_8 + 1);							\
-				m37710i_branch_8(m37710i_cpu, DST);										\
+				m37710i_branch_8(cpustate, DST);										\
 				BREAKOUT;													\
 			}																\
 			CLK(CLK_OP + CLK_RELATIVE_8);									\
@@ -904,13 +904,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_BIT(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = OPER_8_##MODE(m37710i_cpu);										\
+			FLAG_N = OPER_8_##MODE(cpustate);										\
 			FLAG_Z = FLAG_N & REG_A;										\
 			FLAG_V = FLAG_N << 1
 #else
 #define OP_BIT(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_N = OPER_16_##MODE(m37710i_cpu);										\
+			FLAG_N = OPER_16_##MODE(cpustate);										\
 			FLAG_Z = FLAG_N & REG_A;										\
 			FLAG_N = NFLAG_16(FLAG_N);										\
 			FLAG_V = FLAG_N << 1
@@ -921,11 +921,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_BITI()															\
 			CLK(CLK_OP + CLK_R8 + CLK_IMM);									\
-			FLAG_Z = REG_A & OPER_8_IMM(m37710i_cpu)
+			FLAG_Z = REG_A & OPER_8_IMM(cpustate)
 #else
 #define OP_BITI()															\
 			CLK(CLK_OP + CLK_R16 + CLK_IMM);								\
-			FLAG_Z = REG_A & OPER_16_IMM(m37710i_cpu)
+			FLAG_Z = REG_A & OPER_16_IMM(cpustate)
 #endif
 
 /* M37710   Cause a Break interrupt */
@@ -933,19 +933,19 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #define OP_BRK()															\
 			REG_PC++;													\
 			fatalerror("BRK at PC=%06x", REG_PB|REG_PC);									\
-			m37710i_interrupt_software(m37710i_cpu, 0xfffa)
+			m37710i_interrupt_software(cpustate, 0xfffa)
 
 /* M37710  Branch Always */
 #undef OP_BRA
 #define OP_BRA()															\
 			CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8);						\
-			m37710i_branch_8(m37710i_cpu, OPER_8_IMM(m37710i_cpu))
+			m37710i_branch_8(cpustate, OPER_8_IMM(cpustate))
 
 /* M37710  Branch Always Long */
 #undef OP_BRL
 #define OP_BRL()															\
 			CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16);					\
-			m37710i_branch_16(m37710i_cpu, OPER_16_IMM(m37710i_cpu))
+			m37710i_branch_16(cpustate, OPER_16_IMM(cpustate))
 
 /* M37710   Clear Carry flag */
 #undef OP_CLC
@@ -963,7 +963,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_CLI
 #define OP_CLI()															\
 			CLK(CLK_OP + CLK_IMPLIED);										\
-			m37710i_set_flag_i(m37710i_cpu, IFLAG_CLEAR)
+			m37710i_set_flag_i(cpustate, IFLAG_CLEAR)
 
 /* M37710   Clear oVerflow flag */
 #undef OP_CLV
@@ -977,13 +977,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_CMP(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_C = REG_A - OPER_8_##MODE(m37710i_cpu);								\
+			FLAG_C = REG_A - OPER_8_##MODE(cpustate);								\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C);							\
 			FLAG_C ^= CFLAG_SET
 #else
 #define OP_CMP(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_C = REG_A - OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_C = REG_A - OPER_16_##MODE(cpustate);								\
 			FLAG_Z = MAKE_UINT_16(FLAG_C);									\
 			FLAG_N = NFLAG_16(FLAG_C);										\
 			FLAG_C = ~CFLAG_16(FLAG_C)
@@ -995,13 +995,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_CMPB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_C = REG_BA - OPER_8_##MODE(m37710i_cpu);								\
+			FLAG_C = REG_BA - OPER_8_##MODE(cpustate);								\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C);							\
 			FLAG_C ^= CFLAG_SET
 #else
 #define OP_CMPB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_C = REG_BA - OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_C = REG_BA - OPER_16_##MODE(cpustate);								\
 			FLAG_Z = MAKE_UINT_16(FLAG_C);									\
 			FLAG_N = NFLAG_16(FLAG_C);										\
 			FLAG_C = ~CFLAG_16(FLAG_C)
@@ -1013,13 +1013,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_X
 #define OP_CMPX(REG, MODE)													\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_C = REG - OPER_8_##MODE(m37710i_cpu);									\
+			FLAG_C = REG - OPER_8_##MODE(cpustate);									\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C);							\
 			FLAG_C ^= CFLAG_SET
 #else
 #define OP_CMPX(REG, MODE)													\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_C = REG - OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_C = REG - OPER_16_##MODE(cpustate);								\
 			FLAG_Z = MAKE_UINT_16(FLAG_C);									\
 			FLAG_N = NFLAG_16(FLAG_C);										\
 			FLAG_C = ~CFLAG_16(FLAG_C)
@@ -1029,7 +1029,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_COP
 #define OP_COP()															\
 			REG_PC++;														\
-			m37710i_interrupt_software(m37710i_cpu, VECTOR_COP)
+			m37710i_interrupt_software(cpustate, VECTOR_COP)
 
 /* M37710   Decrement accumulator */
 #undef OP_DEC
@@ -1062,13 +1062,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_DECM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1);			\
 			write_8_##MODE(DST, FLAG_Z)
 #else
 #define OP_DECM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1);					\
 			FLAG_N = NFLAG_16(FLAG_Z);										\
 			write_16_##MODE(DST, FLAG_Z)
@@ -1092,11 +1092,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_EOR(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_A ^= OPER_8_##MODE(cpustate)
 #else
 #define OP_EOR(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_A ^= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_A ^= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_A)
 #endif
 
@@ -1105,11 +1105,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_EORB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_BA ^= OPER_8_##MODE(cpustate)
 #else
 #define OP_EORB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_BA ^= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_BA ^= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_BA)
 #endif
 
@@ -1144,13 +1144,13 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_INCM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1);			\
 			write_8_##MODE(DST, FLAG_Z)
 #else
 #define OP_INCM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1);					\
 			FLAG_N = NFLAG_16(FLAG_Z);										\
 			write_16_##MODE(DST, FLAG_Z)
@@ -1173,61 +1173,61 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_JMLAI
 #define OP_JMLAI()															\
 			CLK(CLK_OP + CLK_AI + 1);										\
-			m37710i_jump_24(m37710i_cpu, read_24_A(OPER_16_IMM(m37710i_cpu)))
+			m37710i_jump_24(cpustate, read_24_A(OPER_16_IMM(cpustate)))
 
 /* M37710   Jump */
 #undef OP_JMP
 #define OP_JMP(MODE)														\
 			CLK(CLK_OP + CLK_##MODE);										\
-			m37710i_jump_16(m37710i_cpu, EA_##MODE(m37710i_cpu))
+			m37710i_jump_16(cpustate, EA_##MODE(cpustate))
 
 /* M37710   Jump absolute indexed indirect */
 #undef OP_JMPAXI
 #define OP_JMPAXI()															\
 			CLK(CLK_OP + CLK_AXI);											\
-			m37710i_jump_16(m37710i_cpu, read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(m37710i_cpu) + REG_X))))
+			m37710i_jump_16(cpustate, read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X))))
 
 /* M37710  Jump absolute long */
 #undef OP_JMPAL
 #define OP_JMPAL()															\
 			CLK(CLK_OP + CLK_AL);											\
-			m37710i_jump_24(m37710i_cpu, EA_AL(m37710i_cpu))
+			m37710i_jump_24(cpustate, EA_AL(cpustate))
 
 /* M37710  Jump to Subroutine Long */
 #undef OP_JSL
 #define OP_JSL(MODE)														\
 			CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1);							\
-			DST = EA_##MODE(m37710i_cpu);												\
-			m37710i_push_8(m37710i_cpu, REG_PB>>16);										\
-			m37710i_push_16(m37710i_cpu, REG_PC);										\
-			m37710i_jump_24(m37710i_cpu, DST)
+			DST = EA_##MODE(cpustate);												\
+			m37710i_push_8(cpustate, REG_PB>>16);										\
+			m37710i_push_16(cpustate, REG_PC);										\
+			m37710i_jump_24(cpustate, DST)
 
 /* M37710   Jump to Subroutine */
 #undef OP_JSR
 #define OP_JSR(MODE)														\
 			CLK(CLK_OP + CLK_W16 + CLK_##MODE);								\
-			DST = EA_##MODE(m37710i_cpu);												\
-			m37710i_push_16(m37710i_cpu, REG_PC);										\
-			m37710i_jump_16(m37710i_cpu, DST)
+			DST = EA_##MODE(cpustate);												\
+			m37710i_push_16(cpustate, REG_PC);										\
+			m37710i_jump_16(cpustate, DST)
 
 /* M37710   Jump to Subroutine */
 #undef OP_JSRAXI
 #define OP_JSRAXI()															\
 			CLK(CLK_OP + CLK_W16 + CLK_AXI);								\
-			DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(m37710i_cpu) + REG_X))); \
-			m37710i_push_16(m37710i_cpu, REG_PC);										\
-			m37710i_jump_16(m37710i_cpu, DST)
+			DST = read_16_AXI(REG_PB | (MAKE_UINT_16(OPER_16_IMM(cpustate) + REG_X))); \
+			m37710i_push_16(cpustate, REG_PC);										\
+			m37710i_jump_16(cpustate, DST)
 
 /* M37710   Load accumulator with operand */
 #undef OP_LDA
 #if FLAG_SET_M
 #define OP_LDA(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_A = OPER_8_##MODE(cpustate)
 #else
 #define OP_LDA(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_A = OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_A = OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_A)
 #endif
 
@@ -1236,11 +1236,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_LDB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_BA = OPER_8_##MODE(cpustate)
 #else
 #define OP_LDB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_BA = OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_BA = OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_BA)
 #endif
 
@@ -1249,14 +1249,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_LDM(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);	\
-			REG_IM2 = EA_##MODE(m37710i_cpu);		\
+			REG_IM2 = EA_##MODE(cpustate);		\
 			REG_IM = read_8_NORM(REG_PB|REG_PC);		\
 			REG_PC++;				\
 			write_8_##MODE(REG_IM2, REG_IM)
 #else
 #define OP_LDM(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);	\
-			REG_IM2 = EA_##MODE(m37710i_cpu);		\
+			REG_IM2 = EA_##MODE(cpustate);		\
 			REG_IM = read_16_NORM(REG_PB|REG_PC);		\
 			REG_PC+=2;				\
 			write_16_##MODE(REG_IM2, REG_IM)
@@ -1267,28 +1267,28 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_BBS(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);	\
-			REG_IM2 = read_8_NORM(EA_##MODE(m37710i_cpu)); 	\
+			REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); 	\
 			REG_IM = read_8_NORM(REG_PC);		\
 			REG_PC++;				\
-			DST = OPER_8_IMM(m37710i_cpu);	  		\
+			DST = OPER_8_IMM(cpustate);	  		\
 			if ((REG_IM2 & REG_IM) == REG_IM)	\
 			{				   	\
 				CLK(CLK_OP + CLK_RELATIVE_8 + 1); 	\
-				m37710i_branch_8(m37710i_cpu, DST);		\
+				m37710i_branch_8(cpustate, DST);		\
 				BREAKOUT;			\
 			}
 #else
 #define OP_BBS(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);	\
-			REG_IM2 = read_16_NORM(EA_##MODE(m37710i_cpu)); 	\
+			REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); 	\
 			REG_IM = read_16_NORM(REG_PC);		\
 			REG_PC++;				\
 			REG_PC++;				\
-			DST = OPER_8_IMM(m37710i_cpu);	  		\
+			DST = OPER_8_IMM(cpustate);	  		\
 			if ((REG_IM2 & REG_IM) == REG_IM)	\
 			{				   	\
 				CLK(CLK_OP + CLK_RELATIVE_8 + 1); 	\
-				m37710i_branch_8(m37710i_cpu, DST);		\
+				m37710i_branch_8(cpustate, DST);		\
 				BREAKOUT;			\
 			}
 #endif
@@ -1298,28 +1298,28 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_BBC(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);	\
-			REG_IM2 = read_8_NORM(EA_##MODE(m37710i_cpu)); 	\
+			REG_IM2 = read_8_NORM(EA_##MODE(cpustate)); 	\
 			REG_IM = read_8_NORM(REG_PC);		\
 			REG_PC++;				\
-			DST = OPER_8_IMM(m37710i_cpu);	  		\
+			DST = OPER_8_IMM(cpustate);	  		\
 			if ((REG_IM2 & REG_IM) == 0)   		\
 			{				   	\
 				CLK(CLK_OP + CLK_RELATIVE_8 + 1); 	\
-				m37710i_branch_8(m37710i_cpu, DST);		\
+				m37710i_branch_8(cpustate, DST);		\
 				BREAKOUT;			\
 			}
 #else
 #define OP_BBC(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);	\
-			REG_IM2 = read_16_NORM(EA_##MODE(m37710i_cpu)); 	\
+			REG_IM2 = read_16_NORM(EA_##MODE(cpustate)); 	\
 			REG_IM = read_16_NORM(REG_PC);		\
 			REG_PC++;				\
 			REG_PC++;				\
-			DST = OPER_8_IMM(m37710i_cpu);	  		\
+			DST = OPER_8_IMM(cpustate);	  		\
 			if ((REG_IM2 & REG_IM) == 0)		\
 			{				   	\
 				CLK(CLK_OP + CLK_RELATIVE_8 + 1); 	\
-				m37710i_branch_8(m37710i_cpu, DST);		\
+				m37710i_branch_8(cpustate, DST);		\
 				BREAKOUT;			\
 			}
 #endif
@@ -1346,11 +1346,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_X
 #define OP_LDX(REG, MODE)													\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG = OPER_8_##MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG = OPER_8_##MODE(cpustate)
 #else
 #define OP_LDX(REG, MODE)													\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG = OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG = OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG)
 #endif
 
@@ -1391,7 +1391,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_LSRM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_N = 0;														\
 			FLAG_Z = read_8_##MODE(DST);									\
 			FLAG_C = FLAG_Z << 8;											\
@@ -1400,7 +1400,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_LSRM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			FLAG_N = 0;														\
 			FLAG_Z = read_16_##MODE(DST);									\
 			FLAG_C = FLAG_Z << 8;											\
@@ -1412,8 +1412,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_MVN
 #if FLAG_SET_X
 #define OP_MVN()															\
-			DST = OPER_8_IMM(m37710i_cpu)<<16;											\
-			SRC = OPER_8_IMM(m37710i_cpu)<<16;											\
+			DST = OPER_8_IMM(cpustate)<<16;											\
+			SRC = OPER_8_IMM(cpustate)<<16;											\
 			REG_DB = DST;	\
 			REG_A |= REG_B;													\
 			CLK(7);												\
@@ -1442,8 +1442,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 			}
 #else
 #define OP_MVN()															\
-			DST = OPER_8_IMM(m37710i_cpu)<<16;											\
-			SRC = OPER_8_IMM(m37710i_cpu)<<16;											\
+			DST = OPER_8_IMM(cpustate)<<16;											\
+			SRC = OPER_8_IMM(cpustate)<<16;											\
 			REG_DB = DST;	\
 			REG_A |= REG_B;													\
 			CLK(7);												\
@@ -1476,8 +1476,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_MVP
 #if FLAG_SET_X
 #define OP_MVP()															\
-			DST = OPER_8_IMM(m37710i_cpu)<<16;											\
-			SRC = OPER_8_IMM(m37710i_cpu)<<16;											\
+			DST = OPER_8_IMM(cpustate)<<16;											\
+			SRC = OPER_8_IMM(cpustate)<<16;											\
 			REG_DB = DST;	\
 			REG_A |= REG_B;													\
 			CLK(7);												\
@@ -1506,8 +1506,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 			}
 #else
 #define OP_MVP()															\
-			DST = OPER_8_IMM(m37710i_cpu)<<16;											\
-			SRC = OPER_8_IMM(m37710i_cpu)<<16;											\
+			DST = OPER_8_IMM(cpustate)<<16;											\
+			SRC = OPER_8_IMM(cpustate)<<16;											\
 			REG_DB = DST;	\
 			REG_A |= REG_B;													\
 			CLK(7);												\
@@ -1546,11 +1546,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ORA(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_A |= OPER_8_ ## MODE(cpustate)
 #else
 #define OP_ORA(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_A |= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_A |= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_A)
 #endif
 
@@ -1559,11 +1559,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ORB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_BA |= OPER_8_ ## MODE(cpustate)
 #else
 #define OP_ORB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			FLAG_Z = REG_BA |= OPER_16_##MODE(m37710i_cpu);								\
+			FLAG_Z = REG_BA |= OPER_16_##MODE(cpustate);								\
 			FLAG_N = NFLAG_16(REG_BA)
 #endif
 
@@ -1571,31 +1571,31 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_PEA
 #define OP_PEA()															\
 			CLK(CLK_OP + CLK_R16 + CLK_W16);								\
-			m37710i_push_16(m37710i_cpu, OPER_16_IMM(m37710i_cpu))
+			m37710i_push_16(cpustate, OPER_16_IMM(cpustate))
 
 /* M37710  Push Effective Indirect Address */
 #undef OP_PEI
 #define OP_PEI()															\
 			CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D);						\
-			m37710i_push_16(m37710i_cpu, EA_DI(m37710i_cpu))
+			m37710i_push_16(cpustate, EA_DI(cpustate))
 
 /* M37710  Push Effective PC-Relative Address */
 #undef OP_PER
 #define OP_PER()															\
 			CLK(CLK_OP + CLK_R16 + CLK_W16 + 1);							\
-			SRC = OPER_16_IMM(m37710i_cpu);											\
-			m37710i_push_16(m37710i_cpu, REG_PC + SRC)
+			SRC = OPER_16_IMM(cpustate);											\
+			m37710i_push_16(cpustate, REG_PC + SRC)
 
 /* M37710   Push accumulator to the stack */
 #undef OP_PHA
 #if FLAG_SET_M
 #define OP_PHA()															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, REG_A)
+			m37710i_push_8(cpustate, REG_A)
 #else
 #define OP_PHA()															\
 			CLK(CLK_OP + CLK_W16 + 1);										\
-			m37710i_push_16(m37710i_cpu, REG_A)
+			m37710i_push_16(cpustate, REG_A)
 #endif
 
 /* M37710   Push B accumulator to the stack */
@@ -1603,11 +1603,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_PHAB()															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, REG_BA)
+			m37710i_push_8(cpustate, REG_BA)
 #else
 #define OP_PHAB()															\
 			CLK(CLK_OP + CLK_W16 + 1);										\
-			m37710i_push_16(m37710i_cpu, REG_BA)
+			m37710i_push_16(cpustate, REG_BA)
 #endif
 
 /* M37710   Push index register to the stack */
@@ -1615,48 +1615,48 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_X
 #define OP_PHX(REG)															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, REG)
+			m37710i_push_8(cpustate, REG)
 #else
 #define OP_PHX(REG)															\
 			CLK(CLK_OP + CLK_W16 + 1);										\
-			m37710i_push_16(m37710i_cpu, REG)
+			m37710i_push_16(cpustate, REG)
 #endif
 
 /* M37710  Push data bank register */
 #undef OP_PHT
 #define OP_PHT()															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, REG_DB>>16)
+			m37710i_push_8(cpustate, REG_DB>>16)
 
 /* M37710  Push direct register */
 #undef OP_PHD
 #define OP_PHD()															\
 			CLK(CLK_OP + CLK_W16 + 1);										\
-			m37710i_push_16(m37710i_cpu, REG_D)
+			m37710i_push_16(cpustate, REG_D)
 
 /* M37710  Push program bank register */
 #undef OP_PHK
 #define OP_PHK()															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, REG_PB>>16)
+			m37710i_push_8(cpustate, REG_PB>>16)
 
 /* M37710   Push the Processor Status Register to the stack */
 #undef OP_PHP
 #define OP_PHP()															\
 			CLK(CLK_OP + CLK_W8 + 1);										\
-			m37710i_push_8(m37710i_cpu, m37710i_cpu->ipl);									\
-			m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu))
+			m37710i_push_8(cpustate, cpustate->ipl);									\
+			m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate))
 
 /* M37710   Pull accumulator from the stack */
 #undef OP_PLA
 #if FLAG_SET_M
 #define OP_PLA()															\
 			CLK(CLK_OP + CLK_R8 + 2);										\
-			FLAG_N = FLAG_Z = REG_A = m37710i_pull_8(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_A = m37710i_pull_8(cpustate)
 #else
 #define OP_PLA()															\
 			CLK(CLK_OP + CLK_R16 + 2);										\
-			FLAG_Z = REG_A = m37710i_pull_16(m37710i_cpu);								\
+			FLAG_Z = REG_A = m37710i_pull_16(cpustate);								\
 			FLAG_N = NFLAG_16(FLAG_Z)
 #endif
 
@@ -1665,11 +1665,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_PLAB()															\
 			CLK(CLK_OP + CLK_R8 + 2);										\
-			FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG_BA = m37710i_pull_8(cpustate)
 #else
 #define OP_PLAB()															\
 			CLK(CLK_OP + CLK_R16 + 2);										\
-			FLAG_Z = REG_BA = m37710i_pull_16(m37710i_cpu);								\
+			FLAG_Z = REG_BA = m37710i_pull_16(cpustate);								\
 			FLAG_N = NFLAG_16(FLAG_Z)
 #endif
 
@@ -1678,11 +1678,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_X
 #define OP_PLX(REG)															\
 			CLK(CLK_OP + CLK_R8 + 2);										\
-			FLAG_N = FLAG_Z = REG = m37710i_pull_8(m37710i_cpu)
+			FLAG_N = FLAG_Z = REG = m37710i_pull_8(cpustate)
 #else
 #define OP_PLX(REG)															\
 			CLK(CLK_OP + CLK_R16 + 2);										\
-			FLAG_Z = REG = m37710i_pull_16(m37710i_cpu);								\
+			FLAG_Z = REG = m37710i_pull_16(cpustate);								\
 			FLAG_N = NFLAG_16(FLAG_Z)
 #endif
 
@@ -1690,34 +1690,34 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_PLT
 #define OP_PLT()															\
 			CLK(CLK_OP + CLK_R8 + 2);										\
-			FLAG_N = FLAG_Z = m37710i_pull_8(m37710i_cpu);								\
+			FLAG_N = FLAG_Z = m37710i_pull_8(cpustate);								\
 			REG_DB = FLAG_Z << 16
 
 /* M37710  Pull direct register */
 #undef OP_PLD
 #define OP_PLD()															\
 			CLK(CLK_OP + CLK_R16 + 2);										\
-			FLAG_Z = REG_D = m37710i_pull_16(m37710i_cpu);								\
+			FLAG_Z = REG_D = m37710i_pull_16(cpustate);								\
 			FLAG_N = NFLAG_16(FLAG_Z)
 
 /* M37710   Pull the Processor Status Register from the stack */
 #undef OP_PLP
 #define OP_PLP()															\
 			CLK(CLK_OP + CLK_R8 + 2);										\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));									\
-			m37710i_set_reg_ipl(m37710i_cpu, m37710i_pull_8(m37710i_cpu))
+			m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));									\
+			m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate))
 
 /* M37710  Reset Program status word */
 #undef OP_REP
 #define OP_REP()															\
 			CLK(CLK_OP + CLK_R8 + 1);										\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu) & ~OPER_8_IMM(m37710i_cpu))
+			m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~OPER_8_IMM(cpustate))
 
 /* M37710  Clear "M" status bit */
 #undef OP_CLM
 #define OP_CLM()															\
 			CLK(CLK_OP + CLK_R8 + 1);										\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu) & ~FLAGPOS_M)
+			m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) & ~FLAGPOS_M)
 
 /* M37710   Rotate Left the accumulator */
 #undef OP_ROL
@@ -1755,10 +1755,10 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_RLA
 #if FLAG_SET_M
 #define OP_RLA(MODE)														\
-	{ int cnt = OPER_8_##MODE(m37710i_cpu); int tmp; while (cnt > 0) { CLK(6); tmp = REG_A; REG_A=(REG_A<<1)&0xff; REG_A |= (tmp>>7); cnt--; } }
+	{ int cnt = OPER_8_##MODE(cpustate); int tmp; while (cnt > 0) { CLK(6); tmp = REG_A; REG_A=(REG_A<<1)&0xff; REG_A |= (tmp>>7); cnt--; } }
 #else
 #define OP_RLA(MODE)														\
-	{ int cnt = OPER_16_##MODE(m37710i_cpu); int tmp; while (cnt > 0) { CLK(6); tmp = REG_A; REG_A=(REG_A<<1)&0xffff; REG_A |= (tmp>>15); cnt--; } }
+	{ int cnt = OPER_16_##MODE(cpustate); int tmp; while (cnt > 0) { CLK(6); tmp = REG_A; REG_A=(REG_A<<1)&0xffff; REG_A |= (tmp>>15); cnt--; } }
 #endif
 
 /* M37710   Rotate Left an operand */
@@ -1766,14 +1766,14 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_ROLM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST = EA_##MODE(m37710i_cpu);												\
+			DST = EA_##MODE(cpustate);												\
 			FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1();				\
 			FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C);							\
 			write_8_##MODE(DST, FLAG_Z)
 #else
 #define OP_ROLM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST = EA_##MODE(m37710i_cpu);												\
+			DST = EA_##MODE(cpustate);												\
 			FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1();				\
 			FLAG_Z = MAKE_UINT_16(FLAG_C);									\
 			FLAG_N = NFLAG_16(FLAG_C);										\
@@ -1820,7 +1820,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_RORM(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST = EA_##MODE(m37710i_cpu);												\
+			DST = EA_##MODE(cpustate);												\
 			FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100);					\
 			FLAG_C = FLAG_Z << 8;											\
 			FLAG_N = FLAG_Z >>= 1;											\
@@ -1828,7 +1828,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_RORM(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST = EA_##MODE(m37710i_cpu);												\
+			DST = EA_##MODE(cpustate);												\
 			FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000);			\
 			FLAG_C = FLAG_Z << 8;											\
 			FLAG_Z >>= 1;													\
@@ -1840,24 +1840,24 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_RTI
 #define OP_RTI()															\
 			CLK(8);															\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_pull_8(m37710i_cpu));					\
-			m37710i_set_reg_ipl(m37710i_cpu, m37710i_pull_8(m37710i_cpu));					\
-			m37710i_jump_16(m37710i_cpu, m37710i_pull_16(m37710i_cpu));					\
-			REG_PB = m37710i_pull_8(m37710i_cpu) << 16;					\
+			m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate));					\
+			m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate));					\
+			m37710i_jump_16(cpustate, m37710i_pull_16(cpustate));					\
+			REG_PB = m37710i_pull_8(cpustate) << 16;					\
 			m37710i_jumping(REG_PB | REG_PC)
 
 /* M37710  Return from Subroutine Long */
 #undef OP_RTL
 #define OP_RTL()															\
 			CLK(6);															\
-			m37710i_jump_24(m37710i_cpu, m37710i_pull_24(m37710i_cpu))
+			m37710i_jump_24(cpustate, m37710i_pull_24(cpustate))
 
 /* M37710   Return from Subroutine */
 #undef OP_RTS
 #define OP_RTS()															\
 			CLK(6);		\
-			DST = m37710i_pull_16(m37710i_cpu);													\
-			m37710i_jump_16(m37710i_cpu, DST)
+			DST = m37710i_pull_16(cpustate);													\
+			m37710i_jump_16(cpustate, DST)
 
 /* M37710   Subtract with Carry */
 /* Unusual behavior: C flag is inverted */
@@ -1865,7 +1865,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_SBC(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			SRC = OPER_8_##MODE(m37710i_cpu);											\
+			SRC = OPER_8_##MODE(cpustate);											\
 			FLAG_C = ~FLAG_C;												\
 			if(!FLAG_D)														\
 			{																\
@@ -1887,7 +1887,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_SBC(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			SRC = OPER_16_##MODE(m37710i_cpu);											\
+			SRC = OPER_16_##MODE(cpustate);											\
 			FLAG_C = ~FLAG_C;												\
 			if(!FLAG_D)														\
 			{																\
@@ -1924,7 +1924,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_SBCB(MODE)														\
 			CLK(CLK_OP + CLK_R8 + CLK_##MODE);								\
-			SRC = OPER_8_##MODE(m37710i_cpu);											\
+			SRC = OPER_8_##MODE(cpustate);											\
 			FLAG_C = ~FLAG_C;												\
 			if(!FLAG_D)														\
 			{																\
@@ -1946,7 +1946,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_SBCB(MODE)														\
 			CLK(CLK_OP + CLK_R16 + CLK_##MODE);								\
-			SRC = OPER_16_##MODE(m37710i_cpu);											\
+			SRC = OPER_16_##MODE(cpustate);											\
 			FLAG_C = ~FLAG_C;												\
 			if(!FLAG_D)														\
 			{																\
@@ -1993,30 +1993,30 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_SEI
 #define OP_SEI()															\
 			CLK(CLK_OP + CLK_IMPLIED);										\
-			m37710i_set_flag_i(m37710i_cpu, IFLAG_SET)
+			m37710i_set_flag_i(cpustate, IFLAG_SET)
 
 /* M37710  Set Program status word */
 #undef OP_SEP
 #define OP_SEP()															\
 			CLK(CLK_OP + CLK_R8 + 1);										\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu) | OPER_8_IMM(m37710i_cpu))
+			m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | OPER_8_IMM(cpustate))
 
 /* M37710  Set "M" status bit */
 #undef OP_SEM
 #define OP_SEM()															\
 			CLK(CLK_OP + CLK_R8 + 1);										\
-			m37710i_set_reg_p(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu) | FLAGPOS_M)
+			m37710i_set_reg_p(cpustate, m37710i_get_reg_p(cpustate) | FLAGPOS_M)
 
 /* M37710   Store accumulator to memory */
 #undef OP_STA
 #if FLAG_SET_M
 #define OP_STA(MODE)														\
 			CLK(CLK_OP + CLK_W8 + CLK_W_##MODE);								\
-			write_8_##MODE(EA_##MODE(m37710i_cpu), REG_A)
+			write_8_##MODE(EA_##MODE(cpustate), REG_A)
 #else
 #define OP_STA(MODE)														\
 			CLK(CLK_OP + CLK_W16 + CLK_W_##MODE);								\
-			write_16_##MODE(EA_##MODE(m37710i_cpu), REG_A)
+			write_16_##MODE(EA_##MODE(cpustate), REG_A)
 #endif
 
 /* M37710   Store B accumulator to memory */
@@ -2024,11 +2024,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_STB(MODE)														\
 			CLK(CLK_OP + CLK_W8 + CLK_W_##MODE);								\
-			write_8_##MODE(EA_##MODE(m37710i_cpu), REG_BA)
+			write_8_##MODE(EA_##MODE(cpustate), REG_BA)
 #else
 #define OP_STB(MODE)														\
 			CLK(CLK_OP + CLK_W16 + CLK_W_##MODE);								\
-			write_16_##MODE(EA_##MODE(m37710i_cpu), REG_BA)
+			write_16_##MODE(EA_##MODE(cpustate), REG_BA)
 #endif
 
 /* M37710   Store index register to memory */
@@ -2036,11 +2036,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_X
 #define OP_STX(REG, MODE)													\
 			CLK(CLK_OP + CLK_W8 + CLK_W_##MODE);								\
-			write_8_##MODE(EA_##MODE(m37710i_cpu), REG)
+			write_8_##MODE(EA_##MODE(cpustate), REG)
 #else
 #define OP_STX(REG, MODE)													\
 			CLK(CLK_OP + CLK_W16 + CLK_W_##MODE);								\
-			write_16_##MODE(EA_##MODE(m37710i_cpu), REG)
+			write_16_##MODE(EA_##MODE(cpustate), REG)
 #endif
 
 /* M37710   Store zero to memory */
@@ -2048,11 +2048,11 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_STZ(MODE)														\
 			CLK(CLK_OP + CLK_W8 + CLK_W_##MODE);								\
-			write_8_##MODE(EA_##MODE(m37710i_cpu), 0)
+			write_8_##MODE(EA_##MODE(cpustate), 0)
 #else
 #define OP_STZ(MODE)														\
 			CLK(CLK_OP + CLK_W16 + CLK_W_##MODE);								\
-			write_16_##MODE(EA_##MODE(m37710i_cpu), 0)
+			write_16_##MODE(EA_##MODE(cpustate), 0)
 #endif
 
 /* M37710  Stop the clock */
@@ -2251,7 +2251,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_CLB(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			REG_IM = read_8_##MODE(DST);									\
 			REG_IM2 = read_8_NORM(REG_PC);	\
 			REG_PC++;			\
@@ -2259,7 +2259,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_CLB(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			REG_IM = read_16_##MODE(DST);									\
 			REG_IM2 = read_16_NORM(REG_PC);	\
 			REG_PC+=2;			\
@@ -2271,7 +2271,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #if FLAG_SET_M
 #define OP_SEB(MODE)														\
 			CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			REG_IM = read_8_##MODE(DST);									\
 			REG_IM2 = read_8_NORM(REG_PC);	\
 			REG_PC++;			\
@@ -2279,7 +2279,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #else
 #define OP_SEB(MODE)														\
 			CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE);							\
-			DST    = EA_##MODE(m37710i_cpu);											\
+			DST    = EA_##MODE(cpustate);											\
 			REG_IM = read_16_##MODE(DST);									\
 			REG_IM2 = read_16_NORM(REG_PC);	\
 			REG_PC+=2;			\
@@ -2299,7 +2299,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 			CLK(2);		\
 			REG_IR = read_8_IMM(REG_PB | REG_PC);	\
 			REG_PC++;	\
-			m37710i_cpu->opcodes42[REG_IR](m37710i_cpu);
+			cpustate->opcodes42[REG_IR](cpustate);
 
 
 /* M37710  prefix for multiply / divide instructions (0x89) */
@@ -2307,7 +2307,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #define OP_PFXM()															\
 			REG_IR = read_8_IMM(REG_PB | REG_PC);	\
 			REG_PC++;	\
-			m37710i_cpu->opcodes89[REG_IR](m37710i_cpu);
+			cpustate->opcodes89[REG_IR](cpustate);
 
 
 /* M37710 unimplemented opcode */
@@ -2319,7 +2319,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef OP_LDTAAA
 #define OP_LDT(MODE)	\
 	CLK(CLK_OP + CLK_R8 + CLK_##MODE);	\
-	REG_DB = OPER_8_##MODE(m37710i_cpu)<<16;
+	REG_DB = OPER_8_##MODE(cpustate)<<16;
 
 /* ======================================================================== */
 /* ======================== OPCODE & FUNCTION TABLES ====================== */
@@ -2331,38 +2331,38 @@ INLINE uint EA_SIY(m37710i_cpu_struct *m37710i_cpu)   {return MAKE_UINT_16(read_
 #undef TABLE_FUNCTION
 
 #if !FLAG_SET_M && !FLAG_SET_X
-#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X0(m37710i_cpu_struct *m37710i_cpu) {OPERATION;}
+#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X0(m37710i_cpu_struct *cpustate) {OPERATION;}
 #define O(CODE) m37710i_ ## CODE ## _M0X0
-#define TABLE_OPCODES void (*const m37710i_opcodes_M0X0[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X0[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X0[256])(m37710i_cpu_struct *m37710i_cpu)
+#define TABLE_OPCODES void (*const m37710i_opcodes_M0X0[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X0[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X0[256])(m37710i_cpu_struct *cpustate)
 #define TABLE_FUNCTION(RTYPE, NAME, ARGS)	RTYPE m37710i_ ## NAME ## _M0X0 ARGS
 
 #elif !FLAG_SET_M && FLAG_SET_X
 
-#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X1(m37710i_cpu_struct *m37710i_cpu) {OPERATION;}
+#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M0X1(m37710i_cpu_struct *cpustate) {OPERATION;}
 #define O(CODE) m37710i_ ## CODE ## _M0X1
-#define TABLE_OPCODES void (*const m37710i_opcodes_M0X1[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X1[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X1[256])(m37710i_cpu_struct *m37710i_cpu)
+#define TABLE_OPCODES void (*const m37710i_opcodes_M0X1[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M0X1[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M0X1[256])(m37710i_cpu_struct *cpustate)
 #define TABLE_FUNCTION(RTYPE, NAME, ARGS)	RTYPE m37710i_ ## NAME ## _M0X1 ARGS
 
 #elif FLAG_SET_M && !FLAG_SET_X
 
-#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X0(m37710i_cpu_struct *m37710i_cpu) {OPERATION;}
+#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X0(m37710i_cpu_struct *cpustate) {OPERATION;}
 #define O(CODE) m37710i_ ## CODE ## _M1X0
-#define TABLE_OPCODES void (*const m37710i_opcodes_M1X0[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X0[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X0[256])(m37710i_cpu_struct *m37710i_cpu)
+#define TABLE_OPCODES void (*const m37710i_opcodes_M1X0[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X0[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X0[256])(m37710i_cpu_struct *cpustate)
 #define TABLE_FUNCTION(RTYPE, NAME, ARGS)	RTYPE m37710i_ ## NAME ## _M1X0 ARGS
 
 #elif FLAG_SET_M && FLAG_SET_X
 
-#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X1(m37710i_cpu_struct *m37710i_cpu) {OPERATION;}
+#define OP(CODE, OPERATION) static void m37710i_ ## CODE ## _M1X1(m37710i_cpu_struct *cpustate) {OPERATION;}
 #define O(CODE) m37710i_ ## CODE ## _M1X1
-#define TABLE_OPCODES void (*const m37710i_opcodes_M1X1[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X1[256])(m37710i_cpu_struct *m37710i_cpu)
-#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X1[256])(m37710i_cpu_struct *m37710i_cpu)
+#define TABLE_OPCODES void (*const m37710i_opcodes_M1X1[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES2 void (*const m37710i_opcodes42_M1X1[256])(m37710i_cpu_struct *cpustate)
+#define TABLE_OPCODES3 void (*const m37710i_opcodes89_M1X1[256])(m37710i_cpu_struct *cpustate)
 #define TABLE_FUNCTION(RTYPE, NAME, ARGS)	RTYPE m37710i_ ## NAME ## _M1X1 ARGS
 
 #endif
@@ -2832,7 +2832,7 @@ TABLE_OPCODES3 =
 extern int m37710_irq_levels[M37710_LINE_MAX];
 
 /* Assert or clear a line on the CPU */
-TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *m37710i_cpu, int line, int state))
+TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int state))
 {
 	switch(line)
 	{
@@ -2859,7 +2859,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *m37710i_cpu, int line, int s
 					LINE_IRQ &= ~(1 << line);
 					if (m37710_irq_levels[line])
 					{
-						m37710i_cpu->m37710_regs[m37710_irq_levels[line]] |= 8;
+						cpustate->m37710_regs[m37710_irq_levels[line]] |= 8;
 					}
 					return;
 					break;
@@ -2869,7 +2869,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *m37710i_cpu, int line, int s
 					LINE_IRQ |= (1 << line);
 					if (m37710_irq_levels[line])
 					{
-						m37710i_cpu->m37710_regs[m37710_irq_levels[line]] &= ~8;
+						cpustate->m37710_regs[m37710_irq_levels[line]] &= ~8;
 					}
 					break;
 			}
@@ -2888,7 +2888,7 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *m37710i_cpu, int line, int s
 
 
 /* Get a register from the CPU core */
-TABLE_FUNCTION(uint, get_reg, (m37710i_cpu_struct *m37710i_cpu, int regnum))
+TABLE_FUNCTION(uint, get_reg, (m37710i_cpu_struct *cpustate, int regnum))
 {
 	switch(regnum)
 	{
@@ -2901,20 +2901,20 @@ TABLE_FUNCTION(uint, get_reg, (m37710i_cpu_struct *m37710i_cpu, int regnum))
 		case M37710_PB: return REG_PB >> 16;
 		case M37710_DB: return REG_DB >> 16;
 		case M37710_D: return REG_D;
-		case M37710_P: return m37710i_get_reg_p(m37710i_cpu);
+		case M37710_P: return m37710i_get_reg_p(cpustate);
 		case M37710_IRQ_STATE: return LINE_IRQ;
 		case REG_PREVIOUSPC: return REG_PPC;
 	}
 	return 0;
 }
 
-TABLE_FUNCTION(void, set_reg, (m37710i_cpu_struct *m37710i_cpu, int regnum, uint val))
+TABLE_FUNCTION(void, set_reg, (m37710i_cpu_struct *cpustate, int regnum, uint val))
 {
 	switch(regnum)
 	{
 		case M37710_PC: REG_PC = MAKE_UINT_16(val); break;
 		case M37710_S: REG_S = MAKE_UINT_16(val); break;
-		case M37710_P: m37710i_set_reg_p(m37710i_cpu, val); break;
+		case M37710_P: m37710i_set_reg_p(cpustate, val); break;
 #if FLAG_SET_M
 		case M37710_A: REG_A = MAKE_UINT_8(val); REG_B = val&0xff00; break;
 		case M37710_B: REG_BA = MAKE_UINT_8(val); REG_BB = val&0xff00; break;
@@ -2929,11 +2929,11 @@ TABLE_FUNCTION(void, set_reg, (m37710i_cpu_struct *m37710i_cpu, int regnum, uint
 		case M37710_X: REG_X = MAKE_UINT_16(val); break;
 		case M37710_Y: REG_Y = MAKE_UINT_16(val); break;
 #endif
-		case M37710_IRQ_STATE: FTABLE_SET_LINE(m37710i_cpu, M37710_LINE_IRQ0, val == 0 ? CLEAR_LINE : ASSERT_LINE); break;
+		case M37710_IRQ_STATE: FTABLE_SET_LINE(cpustate, M37710_LINE_IRQ0, val == 0 ? CLEAR_LINE : ASSERT_LINE); break;
 		 }
 }
 
-TABLE_FUNCTION(int, execute, (m37710i_cpu_struct *m37710i_cpu, int clocks))
+TABLE_FUNCTION(int, execute, (m37710i_cpu_struct *cpustate, int clocks))
 {
 	if(!CPU_STOPPED)
 	{
@@ -2944,7 +2944,7 @@ TABLE_FUNCTION(int, execute, (m37710i_cpu_struct *m37710i_cpu, int clocks))
 			M37710_CALL_DEBUGGER(REG_PC);
 			REG_PC++;
 			REG_IR = read_8_IMM(REG_PB | REG_PPC);
-			m37710i_cpu->opcodes[REG_IR](m37710i_cpu);
+			cpustate->opcodes[REG_IR](cpustate);
 		} while(CLOCKS > 0);
 		return clocks - CLOCKS;
 	}