Cleanups and version bump.
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a86f8758fc
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5df39c5473
@ -619,19 +619,19 @@ static void superfx_add_clocks_internal(superfx_state *cpustate, INT32 clocks)
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{
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//printf( "superfx_add_clocks: %d\n", clocks);
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/*
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if(cpustate->romcl)
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{
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printf( "ROM is accessing\n" );
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printf( "romcl = %d, -= MIN(%d, %d) (= %d)\n", cpustate->romcl, clocks, cpustate->romcl, MIN(clocks, cpustate->romcl));
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cpustate->romcl -= MIN(clocks, cpustate->romcl);
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if(cpustate->romcl == 0)
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{
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cpustate->sfr &= ~SUPERFX_SFR_R;
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printf( "superfx_op_read: reading from rom, calling superfx_bus_read: %08x\n", (cpustate->rombr << 16) + cpustate->r[14] );
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cpustate->romdr = superfx_bus_read(cpustate, (cpustate->rombr << 16) + cpustate->r[14]);
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}
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}
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*/
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if(cpustate->romcl)
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{
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printf( "ROM is accessing\n" );
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printf( "romcl = %d, -= MIN(%d, %d) (= %d)\n", cpustate->romcl, clocks, cpustate->romcl, MIN(clocks, cpustate->romcl));
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cpustate->romcl -= MIN(clocks, cpustate->romcl);
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if(cpustate->romcl == 0)
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{
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cpustate->sfr &= ~SUPERFX_SFR_R;
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printf( "superfx_op_read: reading from rom, calling superfx_bus_read: %08x\n", (cpustate->rombr << 16) + cpustate->r[14] );
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cpustate->romdr = superfx_bus_read(cpustate, (cpustate->rombr << 16) + cpustate->r[14]);
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}
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}
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*/
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if(cpustate->ramcl)
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{
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@ -4417,7 +4417,7 @@ enum
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#define DISCRETE_TASK_END3(BNODE1,BNODE2,BNODE3) { NODE_SPECIAL, DSO_TASK_END , 3, { BNODE1,BNODE2,BNODE3 }, { BNODE1,BNODE2,BNODE3 }, NULL, "DISCRETE_TASK_END3" },
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#define DISCRETE_TASK_END4(BNODE1,BNODE2,BNODE3,BNODE4) { NODE_SPECIAL, DSO_TASK_END , 4, { BNODE1,BNODE2,BNODE3,BNODE4 }, { BNODE1,BNODE2,BNODE3,BNODE4 }, NULL, "DISCRETE_TASK_END4" },
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#define DISCRETE_TASK_END5(BNODE1,BNODE2,BNODE3,BNODE4,BNODE5) { NODE_SPECIAL, DSO_TASK_END , 5, { BNODE1,BNODE2,BNODE3,BNODE4,BNODE5 }, { BNODE1,BNODE2,BNODE3,BNODE4,BNODE5 }, NULL, "DISCRETE_TASK_END5" },
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//#define DISCRETE_TASK_SYNC() { NODE_SPECIAL, DSO_TASK_SYNC, 0, { 0 }, { 0 }, NULL, "DISCRETE_TASK_SYNC" },
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//#define DISCRETE_TASK_SYNC() { NODE_SPECIAL, DSO_TASK_SYNC, 0, { 0 }, { 0 }, NULL, "DISCRETE_TASK_SYNC" },
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/* output */
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#define DISCRETE_OUTPUT(OPNODE,GAIN) { NODE_SPECIAL, DSO_OUTPUT , 2, { OPNODE,NODE_NC }, { 0,GAIN }, NULL, "DISCRETE_OUTPUT" },
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@ -327,7 +327,7 @@ DEVICE_GET_INFO( bzone_sound )
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#define BZ_R8 RES_K(100)
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#define BZ_R9 RES_K(22)
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//#define RT (1.0/BZ_R5 + 1.0/BZ_R6 * 1.0/BZ_R7)
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//#define RT (1.0/BZ_R5 + 1.0/BZ_R6 * 1.0/BZ_R7)
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#define BZ_R10 RES_K(100)
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#define BZ_R11 RES_K(250)
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@ -467,7 +467,7 @@ static DISCRETE_SOUND_START(bzone)
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DISCRETE_INPUT_DATA(BZ_INPUT)
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/* decode the bits */
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DISCRETE_BITS_DECODE(NODE_10, BZ_INPUT, 0, 7, 5.7)// TTL_OUT) /* QA-QD 74393 */
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DISCRETE_BITS_DECODE(NODE_10, BZ_INPUT, 0, 7, 5.7)// TTL_OUT) /* QA-QD 74393 */
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DISCRETE_ADJUSTMENT_TAG(NODE_11, 0, RES_K(250), DISC_LINADJ, "R11")
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@ -2102,14 +2102,14 @@ static INTERRUPT_GEN( shogwarr_interrupt )
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/*
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unsigned char shogwarr_default_eeprom[128] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F, 0x2F, 0x41, 0x54, 0x4F, 0x50, 0x20, 0x31, 0x39, 0x39, 0x32,
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0x46, 0x55, 0x4A, 0x49, 0xFF, 0xFF, 0x4D, 0x41, 0x20, 0x42, 0x55, 0x53, 0x54, 0x45, 0x52, 0x20,
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0x20, 0x53, 0x48, 0x4F, 0xFF, 0xFF, 0x4E, 0x20, 0x57, 0x41, 0x52, 0x52, 0x49, 0x4F, 0x52, 0x53,
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0xFF, 0xFF, 0x70, 0x79, 0x72, 0x69, 0xFF, 0xFF, 0x74, 0x20, 0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F, 0x2F, 0x41, 0x54, 0x4F, 0x50, 0x20, 0x31, 0x39, 0x39, 0x32,
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0x46, 0x55, 0x4A, 0x49, 0xFF, 0xFF, 0x4D, 0x41, 0x20, 0x42, 0x55, 0x53, 0x54, 0x45, 0x52, 0x20,
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0x20, 0x53, 0x48, 0x4F, 0xFF, 0xFF, 0x4E, 0x20, 0x57, 0x41, 0x52, 0x52, 0x49, 0x4F, 0x52, 0x53,
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0xFF, 0xFF, 0x70, 0x79, 0x72, 0x69, 0xFF, 0xFF, 0x74, 0x20, 0x4B, 0x41, 0x4E, 0x45, 0x4B, 0x4F,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF
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};
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*/
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// the above eeprom looks corrupt, some of the text is wrong, the game never writes this text tho.. maybe it should be as below
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@ -3803,20 +3803,20 @@ DRIVER_INIT( calc3 )
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static DRIVER_INIT( brapboys )
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{
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/*
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Expand the OKI sample data
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Expand the OKI sample data
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OKI 1:
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Address space 0x00000-0x2ffff is fixed
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Address space 0x30000-0x3ffff is banked (13 banks)
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OKI 1:
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Address space 0x00000-0x2ffff is fixed
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Address space 0x30000-0x3ffff is banked (13 banks)
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OKI 2:
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Address space 0x00000-0x1ffff is fixed
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Address space 0x20000-0x3ffff is banked (15 banks)
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OKI 2:
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Address space 0x00000-0x1ffff is fixed
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Address space 0x20000-0x3ffff is banked (15 banks)
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The current sound device implementation can't handle
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the banking dynamically so we have to expand all the bank
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combinations here and use use okim6295_set_bank_base().
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*/
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The current sound device implementation can't handle
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the banking dynamically so we have to expand all the bank
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combinations here and use use okim6295_set_bank_base().
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*/
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int bank;
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UINT8 *src = memory_region(machine, "samples");
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UINT8 *dst1 = memory_region(machine, "oki1");
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@ -1461,9 +1461,9 @@ Galaxy Games StarPak 2
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NAMCO 307 Cartridge, has surface mount Flash chips in it:
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.u1 am29f800BB
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.u2 am29f800BB
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.u4 pic 12c508
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.u1 am29f800BB
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.u2 am29f800BB
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.u4 pic 12c508
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Board silkscreened 237-0209-00
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REV.-C
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@ -244,8 +244,8 @@ READ16_HANDLER(bloodwar_calc_r)
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}
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/*
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B Rap Boys
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Shogun Warriors
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B Rap Boys
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Shogun Warriors
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*/
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@ -1373,16 +1373,16 @@ void calc3_mcu_run(running_machine *machine)
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printf("Calc 3 Init Command - %04x ROM Checksum Address\n", cakc3_checkumaddress);
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printf("Calc 3 Init Command - %08x Data Write Address\n", calc3_writeaddress);
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#endif
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// memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
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// memory_write_byte(space, calc3_dsw_addr+0x200000, ( ~input_port_read(machine, "DSW1"))&0xff); // // DSW // dsw actually updates in realtime - mcu reads+writes it every frame
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kaneko16_mcu_ram[cakc3_checkumaddress / 2] = calc3_mcu_crc; // MCU Rom Checksum!
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/*
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for (i=0;i<0x40;i++)
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{
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kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) | ((eepromData[i]&0x00ff)<<8);
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}
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*/
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for (i=0;i<0x40;i++)
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{
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kaneko16_mcu_ram[(calc3_eeprom_addr / 2)+i] = kaneko16_eeprom_data[i];//((eepromData[i]&0xff00)>>8) | ((eepromData[i]&0x00ff)<<8);
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}
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*/
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{
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UINT32 length, size;
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@ -181,7 +181,7 @@ static WRITE16_HANDLER( mk_prot_w )
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static READ16_HANDLER( mkturbo_prot_r )
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{
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/* the security GAL overlays a counter of some sort at 0xfffff400 in ROM space.
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* A startup protection check expects to read back two different values in succession */
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* A startup protection check expects to read back two different values in succession */
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return mame_rand(space->machine);
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}
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@ -1210,8 +1210,8 @@ VIDEO_UPDATE( taitof2_driftout )
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UINT16 pen;
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/* send palette, workaround for bug http://www.mametesters.org/view.php?id=3356 (just for this game)
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driftout writes twice per frame to the palette, this causes glitches on some setups due to
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VIDEO_UPDATE not being synced to renderer update when multithreading is on. */
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driftout writes twice per frame to the palette, this causes glitches on some setups due to
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VIDEO_UPDATE not being synced to renderer update when multithreading is on. */
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for (pen=0;pen<4096;pen++)
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palette_set_color_rgb(screen->machine, pen, pal5bit(paletteram_buffer[pen] >> 10), pal5bit(paletteram_buffer[pen] >> 5), pal5bit(paletteram_buffer[pen] >> 0));
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@ -272,7 +272,7 @@ static const dasm_table_entry dasm_table[] =
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{ "ssem", _32le, 0, CPU_DISASSEMBLE_NAME(ssem) },
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{ "ssp1601", _16be, -1, CPU_DISASSEMBLE_NAME(ssp1601) },
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{ "t11", _16le, 0, CPU_DISASSEMBLE_NAME(t11) },
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// { "t90", _8bit, 0, CPU_DISASSEMBLE_NAME(t90) },
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// { "t90", _8bit, 0, CPU_DISASSEMBLE_NAME(t90) },
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{ "tlcs900", _8bit, 0, CPU_DISASSEMBLE_NAME(tlcs900) },
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{ "tms0980", _16be, 0, CPU_DISASSEMBLE_NAME(tms0980) },
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{ "tms1000", _8bit, 0, CPU_DISASSEMBLE_NAME(tms1000) },
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@ -293,7 +293,7 @@ static const dasm_table_entry dasm_table[] =
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{ "v70", _8bit, 0, CPU_DISASSEMBLE_NAME(v70) },
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{ "v810", _16le, 0, CPU_DISASSEMBLE_NAME(v810) },
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{ "z180", _8bit, 0, CPU_DISASSEMBLE_NAME(z180) },
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// { "z8000", _16be, 0, CPU_DISASSEMBLE_NAME(z8000) },
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// { "z8000", _16be, 0, CPU_DISASSEMBLE_NAME(z8000) },
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{ "z80", _8bit, 0, CPU_DISASSEMBLE_NAME(z80) },
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};
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@ -10,4 +10,4 @@
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***************************************************************************/
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extern const char build_version[];
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const char build_version[] = "0.133u3 ("__DATE__")";
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const char build_version[] = "0.133u4 ("__DATE__")";
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