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mcs51: Use callbacks for parallel ports (nw)

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This commit is contained in:
AJR 2018-02-27 22:21:06 -05:00
parent 81fa412066
commit 5e3a7e9bf0
77 changed files with 728 additions and 1034 deletions
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6
src/devices/bus/isa/sb16.cpp
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@ -401,8 +401,6 @@ ADDRESS_MAP_START(sb16_lle_device::sb16_io)
// AM_RANGE(0x0080, 0x0080) // ASP comms
// AM_RANGE(0x0081, 0x0081)
// AM_RANGE(0x0082, 0x0082)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(p2_r, p2_w)
ADDRESS_MAP_END
const tiny_rom_entry *sb16_lle_device::device_rom_region() const
@ -413,6 +411,10 @@ const tiny_rom_entry *sb16_lle_device::device_rom_region() const
MACHINE_CONFIG_START(sb16_lle_device::device_add_mconfig)
MCFG_CPU_ADD("sb16_cpu", I80C52, XTAL(24'000'000))
MCFG_CPU_IO_MAP(sb16_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(sb16_lle_device, p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(sb16_lle_device, p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(sb16_lle_device, p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(sb16_lle_device, p2_w))
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("ymf262", YMF262, XTAL(14'318'181))

6
src/devices/bus/isa/stereo_fx.cpp
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@ -101,8 +101,6 @@ ADDRESS_MAP_START(stereo_fx_device::stereo_fx_io)
AM_RANGE(0xFF40, 0xFF40) AM_READWRITE(dev_dsp_data_r, dev_dsp_data_w)
AM_RANGE(0xFF50, 0xFF50) AM_WRITE(raise_drq_w)
AM_RANGE(0xFF60, 0xFF60) AM_WRITE(dev_host_irq_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ(p1_r) AM_DEVWRITE("ldac", dac_byte_interface, write)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(stereo_fx_device::stereo_fx_rom)
@ -118,6 +116,10 @@ MACHINE_CONFIG_START(stereo_fx_device::device_add_mconfig)
MCFG_CPU_ADD("stereo_fx_cpu", I80C31, XTAL(30'000'000))
MCFG_CPU_IO_MAP(stereo_fx_io)
MCFG_CPU_PROGRAM_MAP(stereo_fx_rom)
MCFG_MCS51_PORT_P1_IN_CB(READ8(stereo_fx_device, p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(DEVWRITE8("ldac", dac_byte_interface, write))
MCFG_MCS51_PORT_P3_IN_CB(READ8(stereo_fx_device, p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(stereo_fx_device, p3_w))
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("ym3812", YM3812, XTAL(3'579'545))

9
src/devices/bus/pc_kbd/keytro.cpp
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@ -350,9 +350,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(pc_kbd_keytronic_pc3270_device::keytronic_pc3270_io)
AM_RANGE(0x0000, 0xffff) AM_READWRITE(internal_data_read, internal_data_write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_read, p1_write)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(p2_read, p2_write)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_read, p3_write)
ADDRESS_MAP_END
@ -426,6 +423,12 @@ MACHINE_CONFIG_START(pc_kbd_keytronic_pc3270_device::device_add_mconfig)
MCFG_CPU_ADD("kb_keytr", I8051, 11060250)
MCFG_CPU_PROGRAM_MAP(keytronic_pc3270_program)
MCFG_CPU_IO_MAP(keytronic_pc3270_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(pc_kbd_keytronic_pc3270_device, p1_read))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(pc_kbd_keytronic_pc3270_device, p1_write))
MCFG_MCS51_PORT_P2_IN_CB(READ8(pc_kbd_keytronic_pc3270_device, p2_read))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(pc_kbd_keytronic_pc3270_device, p2_write))
MCFG_MCS51_PORT_P3_IN_CB(READ8(pc_kbd_keytronic_pc3270_device, p3_read))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(pc_kbd_keytronic_pc3270_device, p3_write))
MACHINE_CONFIG_END

19
src/devices/bus/pc_kbd/msnat.cpp
View File

@ -196,18 +196,6 @@ INPUT_PORTS_END
DEFINE_DEVICE_TYPE(PC_KBD_MICROSOFT_NATURAL, pc_kbd_microsoft_natural_device, "kb_ms_natural", "Microsoft Natural Keyboard")
/*****************************************************************************
ADDRESS MAPS
*****************************************************************************/
ADDRESS_MAP_START(pc_kbd_microsoft_natural_device::microsoft_natural_io)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(p0_read, p0_write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(p1_write)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITE(p2_write)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_read, p3_write)
ADDRESS_MAP_END
/***************************************************************************
ROM DEFINITIONS
***************************************************************************/
@ -259,7 +247,12 @@ void pc_kbd_microsoft_natural_device::device_reset()
MACHINE_CONFIG_START(pc_kbd_microsoft_natural_device::device_add_mconfig)
MCFG_CPU_ADD("ms_natrl_cpu", I8051, XTAL(6'000'000))
MCFG_CPU_IO_MAP(microsoft_natural_io)
MCFG_MCS51_PORT_P0_IN_CB(READ8(pc_kbd_microsoft_natural_device, p0_read))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(pc_kbd_microsoft_natural_device, p0_write))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(pc_kbd_microsoft_natural_device, p1_write))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(pc_kbd_microsoft_natural_device, p2_write))
MCFG_MCS51_PORT_P3_IN_CB(READ8(pc_kbd_microsoft_natural_device, p3_read))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(pc_kbd_microsoft_natural_device, p3_write))
MACHINE_CONFIG_END

2
src/devices/bus/pc_kbd/msnat.h
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@ -54,8 +54,6 @@ private:
DECLARE_WRITE8_MEMBER(p2_write);
DECLARE_READ8_MEMBER(p3_read);
DECLARE_WRITE8_MEMBER(p3_write);
void microsoft_natural_io(address_map &map);
};

96
src/devices/cpu/mcs51/mcs51.cpp
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@ -268,13 +268,15 @@ mcs51_cpu_device::mcs51_cpu_device(const machine_config &mconfig, device_type ty
(program_width == 12) ? address_map_constructor(FUNC(mcs51_cpu_device::program_12bit), this) : (program_width == 13) ? address_map_constructor(FUNC(mcs51_cpu_device::program_13bit), this) : address_map_constructor())
, m_data_config("data", ENDIANNESS_LITTLE, 8, 9, 0,
(data_width == 7) ? address_map_constructor(FUNC(mcs51_cpu_device::data_7bit), this) : (data_width == 8) ? address_map_constructor(FUNC(mcs51_cpu_device::data_8bit), this) : address_map_constructor())
, m_io_config("io", ENDIANNESS_LITTLE, 8, 18, 0)
, m_io_config("io", ENDIANNESS_LITTLE, 8, (features & FEATURE_DS5002FP) ? 17 : 16, 0)
, m_pc(0)
, m_features(features)
, m_ram_mask( (data_width == 8) ? 0xFF : 0x7F )
, m_num_interrupts(5)
, m_sfr_ram(*this, "sfr_ram")
, m_scratchpad(*this, "scratchpad")
, m_port_in_cb{{*this}, {*this}, {*this}, {*this}}
, m_port_out_cb{{*this}, {*this}, {*this}, {*this}}
, m_serial_tx_cb(*this)
, m_serial_rx_cb(*this)
, m_rtemp(0)
@ -427,10 +429,6 @@ void mcs51_cpu_device::iram_iwrite(offs_t a, uint8_t d) { if (a <= m_ram_mask) m
#define BIT_R(a) bit_address_r(a)
#define BIT_W(a,v) bit_address_w(a, v)
/* Input/Output a byte from given I/O port */
#define IN(port) ((uint8_t)m_io->read_byte(port))
#define OUT(port,value) m_io->write_byte(port,value)
/***************************************************************************
SHORTCUTS
@ -2027,10 +2025,10 @@ void mcs51_cpu_device::sfr_write(size_t offset, uint8_t data)
switch (offset)
{
case ADDR_P0: OUT(MCS51_PORT_P0,data); break;
case ADDR_P1: OUT(MCS51_PORT_P1,data); break;
case ADDR_P2: OUT(MCS51_PORT_P2,data); break;
case ADDR_P3: OUT(MCS51_PORT_P3,data); break;
case ADDR_P0: m_port_out_cb[0](data); break;
case ADDR_P1: m_port_out_cb[1](data); break;
case ADDR_P2: m_port_out_cb[2](data); break;
case ADDR_P3: m_port_out_cb[3](data); break;
case ADDR_SBUF: serial_transmit(data); break;
case ADDR_PSW: SET_PARITY(); break;
case ADDR_ACC: SET_PARITY(); break;
@ -2067,10 +2065,10 @@ uint8_t mcs51_cpu_device::sfr_read(size_t offset)
{
/* Read/Write/Modify operations read the port latch ! */
/* Move to memory map */
case ADDR_P0: return RWM ? P0 : (P0 | m_forced_inputs[0]) & IN(MCS51_PORT_P0);
case ADDR_P1: return RWM ? P1 : (P1 | m_forced_inputs[1]) & IN(MCS51_PORT_P1);
case ADDR_P2: return RWM ? P2 : (P2 | m_forced_inputs[2]) & IN(MCS51_PORT_P2);
case ADDR_P3: return RWM ? P3 : (P3 | m_forced_inputs[3]) & IN(MCS51_PORT_P3);
case ADDR_P0: return RWM ? P0 : (P0 | m_forced_inputs[0]) & m_port_in_cb[0]();
case ADDR_P1: return RWM ? P1 : (P1 | m_forced_inputs[1]) & m_port_in_cb[1]();
case ADDR_P2: return RWM ? P2 : (P2 | m_forced_inputs[2]) & m_port_in_cb[2]();
case ADDR_P3: return RWM ? P3 : (P3 | m_forced_inputs[3]) & m_port_in_cb[3]();
case ADDR_PSW:
case ADDR_ACC:
@ -2106,6 +2104,11 @@ void mcs51_cpu_device::device_start()
m_data = &space(AS_DATA);
m_io = &space(AS_IO);
for (auto &cb : m_port_in_cb)
cb.resolve_safe(0xff);
for (auto &cb : m_port_out_cb)
cb.resolve_safe();
m_serial_rx_cb.resolve_safe(0);
m_serial_tx_cb.resolve_safe();
@ -2146,15 +2149,15 @@ void mcs51_cpu_device::device_start()
state_add<uint8_t>( MCS51_P1, "P1", [this](){ return P1; }, [this](uint8_t p){ SET_P1(p); }).formatstr("%02X");
state_add<uint8_t>( MCS51_P2, "P2", [this](){ return P2; }, [this](uint8_t p){ SET_P2(p); }).formatstr("%02X");
state_add<uint8_t>( MCS51_P3, "P3", [this](){ return P3; }, [this](uint8_t p){ SET_P3(p); }).formatstr("%02X");
state_add( MCS51_R0, "R0", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R1, "R1", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R2, "R2", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R3, "R3", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R4, "R4", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R5, "R5", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R6, "R6", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_R7, "R7", m_rtemp).callimport().callexport().formatstr("%02X");
state_add( MCS51_RB, "RB", m_rtemp).mask(0x03).callimport().callexport().formatstr("%02X");
state_add<uint8_t>( MCS51_R0, "R0", [this](){ return R_REG(0); }, [this](uint8_t r){ SET_REG(0, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R1, "R1", [this](){ return R_REG(1); }, [this](uint8_t r){ SET_REG(1, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R2, "R2", [this](){ return R_REG(2); }, [this](uint8_t r){ SET_REG(2, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R3, "R3", [this](){ return R_REG(3); }, [this](uint8_t r){ SET_REG(3, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R4, "R4", [this](){ return R_REG(4); }, [this](uint8_t r){ SET_REG(4, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R5, "R5", [this](){ return R_REG(5); }, [this](uint8_t r){ SET_REG(5, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R6, "R6", [this](){ return R_REG(6); }, [this](uint8_t r){ SET_REG(6, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_R7, "R7", [this](){ return R_REG(7); }, [this](uint8_t r){ SET_REG(7, r); }).formatstr("%02X");
state_add<uint8_t>( MCS51_RB, "RB", [this](){ return (PSW & 0x18)>>3; }, [this](uint8_t rb){ SET_RS(rb); }).mask(0x03).formatstr("%02X");
state_add( STATE_GENPC, "GENPC", m_pc ).noshow();
state_add( STATE_GENPCBASE, "CURPC", m_pc ).noshow();
@ -2163,55 +2166,6 @@ void mcs51_cpu_device::device_start()
m_icountptr = &m_icount;
}
void mcs51_cpu_device::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
case MCS51_R0:
case MCS51_R1:
case MCS51_R2:
case MCS51_R3:
case MCS51_R4:
case MCS51_R5:
case MCS51_R6:
case MCS51_R7:
SET_REG( entry.index() - MCS51_R0, m_rtemp );
break;
case MCS51_RB:
SET_RS( m_rtemp );
break;
default:
fatalerror("CPU_IMPORT_STATE(mcs48) called for unexpected value\n");
}
}
void mcs51_cpu_device::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
case MCS51_R0:
case MCS51_R1:
case MCS51_R2:
case MCS51_R3:
case MCS51_R4:
case MCS51_R5:
case MCS51_R6:
case MCS51_R7:
m_rtemp = R_REG(entry.index() - MCS51_R0);
break;
case MCS51_RB:
m_rtemp = ((PSW & 0x18)>>3);
break;
default:
fatalerror("CPU_EXPORT_STATE(mcs51) called for unexpected value\n");
}
}
void mcs51_cpu_device::state_string_export(const device_state_entry &entry, std::string &str) const
{
switch (entry.index())

42
src/devices/cpu/mcs51/mcs51.h
View File

@ -32,6 +32,26 @@
#pragma once
#define MCFG_MCS51_PORT_P0_IN_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_in_cb(*device, 0, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P0_OUT_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_out_cb(*device, 0, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P1_IN_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_in_cb(*device, 1, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P1_OUT_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_out_cb(*device, 1, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P2_IN_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_in_cb(*device, 2, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P2_OUT_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_out_cb(*device, 2, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P3_IN_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_in_cb(*device, 3, DEVCB_##_devcb);
#define MCFG_MCS51_PORT_P3_OUT_CB(_devcb) \
devcb = &mcs51_cpu_device::set_port_out_cb(*device, 3, DEVCB_##_devcb);
#define MCFG_MCS51_SERIAL_RX_CB(_devcb) \
devcb = &mcs51_cpu_device::set_serial_rx_cb(*device, DEVCB_##_devcb);
@ -59,17 +79,6 @@ enum
DS5002FP_PFI_LINE /* DS5002FP Power fail interrupt */
};
/* special I/O space ports */
enum
{
MCS51_PORT_P0 = 0x20000,
MCS51_PORT_P1 = 0x20001,
MCS51_PORT_P2 = 0x20002,
MCS51_PORT_P3 = 0x20003,
MCS51_PORT_TX = 0x20004 /* P3.1 */
};
/* At least CMOS devices may be forced to read from ports configured as output.
* All you need is a low impedance output connect to the port.
*/
@ -85,9 +94,11 @@ class mcs51_cpu_device : public cpu_device
{
public:
// configuration helpers
template<class Object> static devcb_base &set_port_in_cb(device_t &device, int n, Object &&cb) { return downcast<mcs51_cpu_device &>(device).m_port_in_cb[n].set_callback(std::forward<Object>(cb)); }
template<class Object> static devcb_base &set_port_out_cb(device_t &device, int n, Object &&cb) { return downcast<mcs51_cpu_device &>(device).m_port_out_cb[n].set_callback(std::forward<Object>(cb)); }
static void set_port_forced_input(device_t &device, uint8_t port, uint8_t forced_input) { downcast<mcs51_cpu_device &>(device).m_forced_inputs[port] = forced_input; }
template<class _Object> static devcb_base & set_serial_rx_cb(device_t &device, _Object object) { return downcast<mcs51_cpu_device &>(device).m_serial_rx_cb.set_callback(object); }
template<class _Object> static devcb_base & set_serial_tx_cb(device_t &device, _Object object) { return downcast<mcs51_cpu_device &>(device).m_serial_tx_cb.set_callback(object); }
template<class Object> static devcb_base &set_serial_rx_cb(device_t &device, Object &&cb) { return downcast<mcs51_cpu_device &>(device).m_serial_rx_cb.set_callback(std::forward<Object>(cb)); }
template<class Object> static devcb_base &set_serial_tx_cb(device_t &device, Object &&cb) { return downcast<mcs51_cpu_device &>(device).m_serial_tx_cb.set_callback(std::forward<Object>(cb)); }
void data_7bit(address_map &map);
void data_8bit(address_map &map);
@ -115,8 +126,6 @@ protected:
virtual space_config_vector memory_space_config() const override;
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry) override;
virtual void state_export(const device_state_entry &entry) override;
virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
// device_disasm_interface overrides
@ -175,6 +184,9 @@ protected:
address_space *m_data;
address_space *m_io;
devcb_read8 m_port_in_cb[4];
devcb_write8 m_port_out_cb[4];
/* Serial Port TX/RX Callbacks */
devcb_write8 m_serial_tx_cb; //Call back function when sending data out of serial port
devcb_read8 m_serial_rx_cb; //Call back function to retrieve data when receiving serial port data

9
src/devices/sound/qs1000.cpp
View File

@ -145,9 +145,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(qs1000_device::qs1000_io_map)
AM_RANGE(0x0000, 0x00ff) AM_RAM
AM_RANGE(0x0200, 0x0211) AM_WRITE(wave_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(p2_r, p2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
ADDRESS_MAP_END
@ -200,6 +197,12 @@ MACHINE_CONFIG_START(qs1000_device::device_add_mconfig)
MCFG_CPU_ADD("cpu", I8052, DERIVED_CLOCK(1, 1))
MCFG_CPU_PROGRAM_MAP(qs1000_prg_map)
MCFG_CPU_IO_MAP(qs1000_io_map)
MCFG_MCS51_PORT_P1_IN_CB(READ8(qs1000_device, p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(qs1000_device, p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(qs1000_device, p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(qs1000_device, p2_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(qs1000_device, p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(qs1000_device, p3_w))
MCFG_MCS51_SERIAL_RX_CB(READ8(qs1000_device, data_to_i8052))
MACHINE_CONFIG_END

16
src/mame/drivers/alesis.cpp
View File

@ -130,9 +130,6 @@ ADDRESS_MAP_START(alesis_state::hr16_io)
AM_RANGE(0x0004, 0x0004) AM_WRITE(led_w)
AM_RANGE(0x0006, 0x0007) AM_DEVREADWRITE("hd44780", hd44780_device, read, write)
AM_RANGE(0x0008, 0x0008) AM_WRITE(kb_matrix_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ_PORT("SELECT") AM_WRITENOP
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITENOP
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("nvram") // 32Kx8 SRAM, (battery-backed)
ADDRESS_MAP_END
@ -147,9 +144,6 @@ ADDRESS_MAP_START(alesis_state::sr16_io)
AM_RANGE(0x0200, 0x0200) AM_MIRROR(0xff) AM_WRITE(sr16_lcd_w)
AM_RANGE(0x0300, 0x0300) AM_MIRROR(0xff) AM_WRITE(kb_matrix_w)
AM_RANGE(0x0400, 0x0400) AM_MIRROR(0xff) AM_READ(kb_r)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READNOP
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITENOP
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
AM_RANGE(0x8000, 0xffff) AM_RAM AM_SHARE("nvram") // 32Kx8 SRAM, (battery-backed)
ADDRESS_MAP_END
@ -161,9 +155,6 @@ ADDRESS_MAP_START(alesis_state::mmt8_io)
AM_RANGE(0xff06, 0xff06) AM_WRITE(kb_matrix_w)
AM_RANGE(0xff08, 0xff09) AM_DEVREADWRITE("hd44780", hd44780_device, read, write)
AM_RANGE(0xff0e, 0xff0e) AM_READNOP
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ(kb_r)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITENOP
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(mmt8_p3_r, mmt8_p3_w)
ADDRESS_MAP_END
/* Input ports */
@ -360,6 +351,9 @@ MACHINE_CONFIG_START(alesis_state::hr16)
MCFG_CPU_ADD("maincpu",I8031, XTAL(12'000'000))
MCFG_CPU_PROGRAM_MAP(hr16_mem)
MCFG_CPU_IO_MAP(hr16_io)
MCFG_MCS51_PORT_P1_IN_CB(IOPORT("SELECT"))
MCFG_MCS51_PORT_P3_IN_CB(READ8(alesis_state, p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(alesis_state, p3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)
@ -393,6 +387,7 @@ MACHINE_CONFIG_START(alesis_state::sr16)
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(sr16_mem)
MCFG_CPU_IO_MAP(sr16_io)
MCFG_MCS51_PORT_P1_IN_CB(NOOP)
/* video hardware */
MCFG_SCREEN_MODIFY("screen")
@ -410,6 +405,9 @@ MACHINE_CONFIG_START(alesis_state::mmt8)
/* basic machine hardware */
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_IO_MAP(mmt8_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(alesis_state, kb_r))
MCFG_MCS51_PORT_P3_IN_CB(READ8(alesis_state, mmt8_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(alesis_state, mmt8_p3_w))
MCFG_DEVICE_REMOVE("dm3ag")
MACHINE_CONFIG_END

9
src/mame/drivers/applix.cpp
View File

@ -492,9 +492,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(applix_state::keytronic_pc3270_io)
AM_RANGE(0x0000, 0xffff) AM_READWRITE(internal_data_read, internal_data_write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_read, p1_write)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(p2_read, p2_write)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_read, p3_write)
ADDRESS_MAP_END
// io priorities:
@ -849,6 +846,12 @@ MACHINE_CONFIG_START(applix_state::applix)
MCFG_CPU_ADD("kbdcpu", I8051, 11060250)
MCFG_CPU_PROGRAM_MAP(keytronic_pc3270_program)
MCFG_CPU_IO_MAP(keytronic_pc3270_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(applix_state, p1_read))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(applix_state, p1_write))
MCFG_MCS51_PORT_P2_IN_CB(READ8(applix_state, p2_read))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(applix_state, p2_write))
MCFG_MCS51_PORT_P3_IN_CB(READ8(applix_state, p3_read))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(applix_state, p3_write))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

3
src/mame/drivers/armedf.cpp
View File

@ -750,8 +750,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(bigfghtr_state::bigfghtr_mcu_io_map)
AM_RANGE(0x00000, 0x005ff) AM_WRITE(mcu_spritelist_w) //Sprite RAM, guess shared as well
AM_RANGE(0x00600, 0x03fff) AM_RAM AM_SHARE("sharedram")
AM_RANGE(MCS51_PORT_P1,MCS51_PORT_P1) AM_READNOP // bit 5: bus contention related?
AM_RANGE(MCS51_PORT_P3,MCS51_PORT_P3) AM_WRITENOP
ADDRESS_MAP_END
ADDRESS_MAP_START(armedf_state::sound_map)
@ -1588,6 +1586,7 @@ MACHINE_CONFIG_START(bigfghtr_state::bigfghtr)
MCFG_CPU_ADD("mcu", I8751, XTAL(16'000'000)/2) // verified
MCFG_CPU_PROGRAM_MAP(bigfghtr_mcu_map)
MCFG_CPU_IO_MAP(bigfghtr_mcu_io_map)
MCFG_MCS51_PORT_P1_IN_CB(NOOP) // bit 5: bus contention related?
MCFG_MACHINE_START_OVERRIDE(armedf_state,armedf)
MCFG_MACHINE_RESET_OVERRIDE(armedf_state,armedf)

3
src/mame/drivers/artmagic.cpp
View File

@ -505,7 +505,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(artmagic_state::shtstar_guncpu_io_map)
AM_RANGE(0xc000, 0xcfff) AM_RAM
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READNOP
ADDRESS_MAP_END
@ -878,7 +877,7 @@ MACHINE_CONFIG_START(artmagic_state::shtstar)
MCFG_CPU_ADD("guncpu", I80C31, 6000000)
MCFG_CPU_IO_MAP(shtstar_guncpu_io_map)
MCFG_CPU_PROGRAM_MAP(shtstar_guncpu_map)
MCFG_MCS51_PORT_P1_IN_CB(NOOP) // ?
MACHINE_CONFIG_END

18
src/mame/drivers/barata.cpp
View File

@ -57,7 +57,6 @@ public:
required_device<cpu_device> m_maincpu;
void barata(machine_config &config);
void i8051_io_port(address_map &map);
private:
unsigned char row_selection;
};
@ -291,17 +290,6 @@ READ8_MEMBER(barata_state::port2_r)
return 0;
}
/*************************
* Memory Map Information *
*************************/
ADDRESS_MAP_START(barata_state::i8051_io_port)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0 ) AM_WRITE(port0_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1 ) AM_READ_PORT("PORT1")
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2 ) AM_READWRITE(port2_r, port2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3 ) AM_WRITE(fpga_w)
ADDRESS_MAP_END
/************************
* Machine Drivers *
************************/
@ -309,7 +297,11 @@ ADDRESS_MAP_END
MACHINE_CONFIG_START(barata_state::barata)
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I8051, CPU_CLOCK)
MCFG_CPU_IO_MAP(i8051_io_port)
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(barata_state, port0_w))
MCFG_MCS51_PORT_P1_IN_CB(IOPORT("PORT1"))
MCFG_MCS51_PORT_P2_IN_CB(READ8(barata_state, port2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(barata_state, port2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(barata_state, fpga_w))
MCFG_DEFAULT_LAYOUT( layout_barata )

3
src/mame/drivers/basic52.cpp
View File

@ -76,7 +76,6 @@ ADDRESS_MAP_START(basic52_state::basic52_io)
AM_RANGE(0xa000, 0xa003) AM_DEVREADWRITE("ppi8255", i8255_device, read, write) // PPI-8255
//AM_RANGE(0xc000, 0xdfff) // Expansion block
//AM_RANGE(0xe000, 0xffff) // Expansion block
AM_RANGE(0x20003, 0x20003) AM_READ(unk_r);
ADDRESS_MAP_END
/* Input ports */
@ -107,6 +106,7 @@ MACHINE_CONFIG_START(basic52_state::basic31)
MCFG_CPU_ADD("maincpu", I8031, XTAL(11'059'200))
MCFG_CPU_PROGRAM_MAP(basic52_mem)
MCFG_CPU_IO_MAP(basic52_io)
MCFG_MCS51_PORT_P3_IN_CB(READ8(basic52_state, unk_r))
MCFG_MCS51_SERIAL_TX_CB(DEVWRITE8("terminal", generic_terminal_device, write))
MCFG_MCS51_SERIAL_RX_CB(READ8(basic52_state, from_term))
@ -123,6 +123,7 @@ MACHINE_CONFIG_START(basic52_state::basic52)
MCFG_CPU_REPLACE("maincpu", I8052, XTAL(11'059'200))
MCFG_CPU_PROGRAM_MAP(basic52_mem)
MCFG_CPU_IO_MAP(basic52_io)
MCFG_MCS51_PORT_P3_IN_CB(READ8(basic52_state, unk_r))
MCFG_MCS51_SERIAL_TX_CB(DEVWRITE8("terminal", generic_terminal_device, write))
MCFG_MCS51_SERIAL_RX_CB(READ8(basic52_state, from_term))
MACHINE_CONFIG_END

14
src/mame/drivers/blktiger.cpp
View File

@ -127,15 +127,6 @@ ADDRESS_MAP_START(blktiger_state::blktiger_sound_map)
AM_RANGE(0xe002, 0xe003) AM_DEVREADWRITE("ym2", ym2203_device, read, write)
ADDRESS_MAP_END
ADDRESS_MAP_START(blktiger_state::blktiger_mcu_map)
AM_RANGE(0x0000, 0x0fff) AM_ROM
ADDRESS_MAP_END
ADDRESS_MAP_START(blktiger_state::blktiger_mcu_io_map)
AM_RANGE(MCS51_PORT_P0,MCS51_PORT_P0) AM_READWRITE(blktiger_from_main_r,blktiger_to_main_w)
AM_RANGE(MCS51_PORT_P1,MCS51_PORT_P3) AM_WRITENOP /* other ports unknown */
ADDRESS_MAP_END
static INPUT_PORTS_START( blktiger )
@ -307,8 +298,9 @@ MACHINE_CONFIG_START(blktiger_state::blktiger)
MCFG_CPU_PROGRAM_MAP(blktiger_sound_map)
MCFG_CPU_ADD("mcu", I8751, XTAL(24'000'000)/4) /* ??? */
MCFG_CPU_PROGRAM_MAP(blktiger_mcu_map)
MCFG_CPU_IO_MAP(blktiger_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(blktiger_state, blktiger_from_main_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(blktiger_state, blktiger_to_main_w))
// other ports unknown
//MCFG_CPU_VBLANK_INT_DRIVER("screen", blktiger_state, irq0_line_hold)
MCFG_WATCHDOG_ADD("watchdog")

4
src/mame/drivers/cardline.cpp
View File

@ -233,8 +233,6 @@ ADDRESS_MAP_START(cardline_state::mem_io)
AM_RANGE(0x3003, 0x3003) AM_WRITE(a3003_w)
AM_RANGE(0xc000, 0xdfff) AM_WRITE(vram_w) AM_SHARE("videoram")
AM_RANGE(0xe000, 0xffff) AM_WRITE(attr_w) AM_SHARE("colorram")
/* Ports */
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(hsync_r, video_w)
ADDRESS_MAP_END
@ -323,6 +321,8 @@ MACHINE_CONFIG_START(cardline_state::cardline)
MCFG_MCS51_PORT1_CONFIG(0x10)
MCFG_CPU_PROGRAM_MAP(mem_prg)
MCFG_CPU_IO_MAP(mem_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(cardline_state, hsync_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(cardline_state, video_w))
//MCFG_CPU_VBLANK_INT_DRIVER("screen", cardline_state, irq1_line_hold)
/* video hardware */

9
src/mame/drivers/cdi.cpp
View File

@ -948,17 +948,12 @@ READ8_MEMBER( cdi_state::quizard_mcu_p1_r )
return machine().rand();
}
ADDRESS_MAP_START(cdi_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ(quizard_mcu_p1_r)
ADDRESS_MAP_END
MACHINE_CONFIG_START(cdi_state::quizard1)
quizard(config);
MCFG_MACHINE_RESET_OVERRIDE(cdi_state, quizard1 )
MCFG_CPU_ADD("mcu", I8751, 8000000)
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_IN_CB(READ8(cdi_state, quizard_mcu_p1_r))
// MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cdi_state, irq0_line_pulse)
MACHINE_CONFIG_END
@ -978,7 +973,7 @@ MACHINE_CONFIG_START(cdi_state::quizard4)
MCFG_MACHINE_RESET_OVERRIDE(cdi_state, quizard4 )
MCFG_CPU_ADD("mcu", I8751, 8000000)
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_IN_CB(READ8(cdi_state, quizard_mcu_p1_r))
// MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cdi_state, irq0_line_pulse)
MACHINE_CONFIG_END

29
src/mame/drivers/controlid.cpp
View File

@ -39,17 +39,22 @@ public:
controlidx628_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_lcdc(*this, "nt7534") { }
DECLARE_WRITE8_MEMBER( p0_w );
DECLARE_WRITE8_MEMBER( p1_w );
DECLARE_PALETTE_INIT( controlidx628 );
required_device<nt7534_device> m_lcdc;
void controlidx628(machine_config &config);
private:
DECLARE_WRITE8_MEMBER(p0_w);
DECLARE_WRITE8_MEMBER(p1_w);
DECLARE_WRITE8_MEMBER(p3_w);
DECLARE_PALETTE_INIT(controlidx628);
void io_map(address_map &map);
void prog_map(address_map &map);
private:
required_device<nt7534_device> m_lcdc;
uint8_t p0_data;
uint8_t p1_data;
uint8_t p3_data;
};
@ -63,12 +68,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(controlidx628_state::io_map)
AM_RANGE(0x8000, 0xffff) AM_RAM
// /* Ports start here */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_WRITE(p0_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(p1_w)
// AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_RAM
// AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_RAM
ADDRESS_MAP_END
@ -86,6 +85,11 @@ WRITE8_MEMBER( controlidx628_state::p1_w )
p1_data = data;
}
WRITE8_MEMBER( controlidx628_state::p3_w )
{
p3_data = data;
}
/*************************
* Input ports *
*************************/
@ -110,6 +114,9 @@ MACHINE_CONFIG_START(controlidx628_state::controlidx628)
MCFG_CPU_ADD("maincpu", I80C32, XTAL(11'059'200)) /* Actually the board has an Atmel AT89S52 mcu. */
MCFG_CPU_PROGRAM_MAP(prog_map)
MCFG_CPU_IO_MAP(io_map)
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(controlidx628_state, p0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(controlidx628_state, p1_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(controlidx628_state, p3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

30
src/mame/drivers/daruma.cpp
View File

@ -29,45 +29,17 @@ public:
m_maincpu(*this, "maincpu"),
m_speaker(*this, "speaker") { }
DECLARE_WRITE8_MEMBER(port_w);
DECLARE_READ8_MEMBER(port_r);
DECLARE_READ8_MEMBER(dev0_r);
DECLARE_WRITE8_MEMBER(dev1_w);
DECLARE_WRITE8_MEMBER(dev2_w);
DECLARE_READ8_MEMBER(dev4_r);
required_device<cpu_device> m_maincpu;
required_device<speaker_sound_device> m_speaker;
char port0, port1, port2, port3;
void daruma(machine_config &config);
void mem_io(address_map &map);
void mem_prg(address_map &map);
};
WRITE8_MEMBER(daruma_state::port_w)
{
// printf("port_w: write %02X to PORT (offset=%02X)\n", data, offset);
switch(offset)
{
case MCS51_PORT_P0: port0=data;
case MCS51_PORT_P1: port1=data;
case MCS51_PORT_P2: port2=data;
case MCS51_PORT_P3: port3=data;
}
}
READ8_MEMBER(daruma_state::port_r)
{
switch(offset)
{
case MCS51_PORT_P0: printf("port_r: read %02X from PORT0\n", port0); return port0;
case MCS51_PORT_P1: printf("port_r: read %02X from PORT1\n", port1); return port1;
case MCS51_PORT_P2: printf("port_r: read %02X from PORT2\n", port2); return port2;
case MCS51_PORT_P3: printf("port_r: read %02X from PORT3\n", port3); return port3;
}
return 0;
}
READ8_MEMBER(daruma_state::dev0_r)
{
return 0xFF;
@ -122,7 +94,6 @@ ADDRESS_MAP_START(daruma_state::mem_io)
// AM_RANGE(0x3000, 0x3000) AM_WRITE(dev3_w)
AM_RANGE(0x4000, 0x4000) AM_READ(dev4_r)
AM_RANGE(0x8000, 0xffff) AM_RAM /* 32K CMOS SRAM (HYUNDAY hy62256a) */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(port_r, port_w)
ADDRESS_MAP_END
//TODO: These buttons and switches are all guesses. We'll need to further investigate this.
@ -148,6 +119,7 @@ MACHINE_CONFIG_START(daruma_state::daruma)
MCFG_CPU_ADD("maincpu", I80C32,11059200) //verified on pcb
MCFG_CPU_PROGRAM_MAP(mem_prg)
MCFG_CPU_IO_MAP(mem_io)
// TODO: ports
/* sound hardware */
MCFG_SPEAKER_STANDARD_MONO("mono")

17
src/mame/drivers/dec0.cpp
View File

@ -857,11 +857,6 @@ ADDRESS_MAP_START(dec0_automat_state::secretab_s_map)
AM_RANGE(0xf000, 0xf000) AM_DEVWRITE("adpcm_select1", ls157_device, ba_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(dec0_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(dec0_mcu_port_r, dec0_mcu_port_w)
ADDRESS_MAP_END
/******************************************************************************/
static INPUT_PORTS_START( dec0 )
@ -1873,7 +1868,11 @@ MACHINE_CONFIG_START(dec0_state::hbarrel)
dec0(config);
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000))
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec0_state, dec0_mcu_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec0_state, dec0_mcu_port0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(dec0_state, dec0_mcu_port1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec0_state, dec0_mcu_port2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(dec0_state, dec0_mcu_port3_w))
/* video hardware */
MCFG_SCREEN_MODIFY("screen")
@ -1884,7 +1883,11 @@ MACHINE_CONFIG_START(dec0_state::baddudes)
dec0(config);
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000))
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec0_state, dec0_mcu_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec0_state, dec0_mcu_port0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(dec0_state, dec0_mcu_port1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec0_state, dec0_mcu_port2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(dec0_state, dec0_mcu_port3_w))
/* video hardware */
MCFG_SCREEN_MODIFY("screen")

128
src/mame/drivers/dec8.cpp
View File

@ -804,115 +804,72 @@ ADDRESS_MAP_END
*/
READ8_MEMBER(dec8_state::dec8_mcu_from_main_r)
READ8_MEMBER(dec8_state::i8751_port0_r)
{
switch (offset)
{
case 0:
return m_i8751_port0;
case 1:
return m_i8751_port1;
case 2:
return 0xff;
case 3:
return m_coin_port->read();
}
return 0xff; //compile safe.
return m_i8751_port0;
}
WRITE8_MEMBER(dec8_state::dec8_mcu_to_main_w)
WRITE8_MEMBER(dec8_state::i8751_port0_w)
{
// Outputs P0 and P1 are latched
if (offset==0) m_i8751_port0=data;
else if (offset==1) m_i8751_port1=data;
m_i8751_port0 = data;
}
READ8_MEMBER(dec8_state::i8751_port1_r)
{
return m_i8751_port1;
}
WRITE8_MEMBER(dec8_state::i8751_port1_w)
{
m_i8751_port1 = data;
}
WRITE8_MEMBER(dec8_state::gondo_mcu_to_main_w)
{
// P2 - controls latches for main CPU communication
if (offset==2 && (data&0x10)==0)
if ((data&0x10)==0)
m_i8751_port0 = m_i8751_value>>8;
if (offset==2 && (data&0x20)==0)
if ((data&0x20)==0)
m_i8751_port1 = m_i8751_value&0xff;
if (offset==2 && (data&0x40)==0)
if ((data&0x40)==0)
m_i8751_return = (m_i8751_return & 0xff) | (m_i8751_port0 << 8);
if (offset==2 && (data&0x80)==0)
if ((data&0x80)==0)
m_i8751_return = (m_i8751_return & 0xff00) | m_i8751_port1;
// P2 - IRQ to main CPU
if (offset==2 && (data&4)==0)
if ((data&4)==0)
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
ADDRESS_MAP_START(dec8_state::dec8_mcu_io_map)
AM_RANGE(MCS51_PORT_P0,MCS51_PORT_P3) AM_READWRITE(dec8_mcu_from_main_r, dec8_mcu_to_main_w)
ADDRESS_MAP_END
/*
Super Real Darwin is similar but only appears to have a single port
*/
READ8_MEMBER(dec8_state::srdarwin_mcu_from_main_r)
{
uint8_t ret = 0;
switch (offset)
{
case 0:
ret = m_i8751_port0;
break;
case 1:
ret = 0x00;
logerror("%s: srdarwin_mcu_from_main_r %02x %02x\n", machine().describe_context(), offset, ret);
break;
case 2:
ret = 0xff;
break;
case 3:
ret = m_coin_port->read();
break;
}
return ret;
}
WRITE8_MEMBER(dec8_state::srdarwin_mcu_to_main_w)
{
// Outputs P0 and P1 are latched
if (offset==0) m_i8751_port0=data;
else if (offset == 1)
{
logerror("%s: srdarwin_mcu_to_main_w %02x %02x\n", machine().describe_context(), offset, data);
}
// P2 - controls latches for main CPU communication
if (offset == 2 && (data & 0x10) == 0)
if ((data & 0x10) == 0)
{
m_i8751_port0 = m_i8751_value >> 8;
}
if (offset == 2 && (data & 0x20) == 0)
if ((data & 0x20) == 0)
{
m_i8751_port0 = m_i8751_value & 0xff;
}
if (offset==2 && (data&0x40)==0)
if ((data&0x40)==0)
m_i8751_return = (m_i8751_return & 0xff) | (m_i8751_port0 << 8);
if (offset==2 && (data&0x80)==0)
if ((data&0x80)==0)
m_i8751_return = (m_i8751_return & 0xff00) | m_i8751_port0;
// P2 - IRQ to main CPU
if (offset==2 && (data&0x04)==0)
if ((data&0x04)==0)
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
// guess, toggled after above.
if (offset==2 && (data&0x02)==0)
if ((data&0x02)==0)
m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
}
ADDRESS_MAP_START(dec8_state::srdarwin_mcu_io_map)
AM_RANGE(MCS51_PORT_P0,MCS51_PORT_P3) AM_READWRITE(srdarwin_mcu_from_main_r, srdarwin_mcu_to_main_w)
ADDRESS_MAP_END
/******************************************************************************/
#define PLAYER1_JOYSTICK /* Player 1 controls */ \
@ -2072,8 +2029,12 @@ MACHINE_CONFIG_START(dec8_state::gondo)
/* NMIs are caused by the main CPU */
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000))
MCFG_CPU_IO_MAP(dec8_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec8_state, i8751_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec8_state, i8751_port0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(dec8_state, i8751_port1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(dec8_state, i8751_port1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec8_state, gondo_mcu_to_main_w))
MCFG_MCS51_PORT_P3_IN_CB(IOPORT("I8751"))
/* video hardware */
MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
@ -2126,8 +2087,12 @@ MACHINE_CONFIG_START(dec8_state::garyoret)
/* NMIs are caused by the main CPU */
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000))
MCFG_CPU_IO_MAP(dec8_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec8_state, i8751_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec8_state, i8751_port0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(dec8_state, i8751_port1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(dec8_state, i8751_port1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec8_state, gondo_mcu_to_main_w))
MCFG_MCS51_PORT_P3_IN_CB(IOPORT("I8751"))
/* video hardware */
MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
@ -2180,8 +2145,12 @@ MACHINE_CONFIG_START(dec8_state::ghostb)
/* NMIs are caused by the main CPU */
MCFG_CPU_ADD("mcu", I8751, 3000000*4)
MCFG_CPU_IO_MAP(dec8_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec8_state, i8751_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec8_state, i8751_port0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(dec8_state, i8751_port1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(dec8_state, i8751_port1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec8_state, gondo_mcu_to_main_w))
MCFG_MCS51_PORT_P3_IN_CB(IOPORT("I8751"))
/* video hardware */
MCFG_BUFFERED_SPRITERAM8_ADD("spriteram")
@ -2359,7 +2328,10 @@ MACHINE_CONFIG_START(dec8_state::srdarwin)
/* NMIs are caused by the main CPU */
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000)) /* unknown frequency */
MCFG_CPU_IO_MAP(srdarwin_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(dec8_state, i8751_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(dec8_state, i8751_port0_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(dec8_state, srdarwin_mcu_to_main_w))
MCFG_MCS51_PORT_P3_IN_CB(IOPORT("I8751"))
MCFG_QUANTUM_PERFECT_CPU("maincpu") /* needed for stability with emulated MCU or sometimes commands get missed and game crashes at bosses */

16
src/mame/drivers/djboy.cpp
View File

@ -379,13 +379,6 @@ WRITE8_MEMBER(djboy_state::beast_p3_w)
}
/* Program/data maps are defined in the 8051 core */
ADDRESS_MAP_START(djboy_state::djboy_mcu_io_map)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(beast_p0_r, beast_p0_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(beast_p1_r, beast_p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(beast_p2_r, beast_p2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(beast_p3_r, beast_p3_w)
ADDRESS_MAP_END
/******************************************************************************/
static INPUT_PORTS_START( djboy )
@ -565,7 +558,14 @@ MACHINE_CONFIG_START(djboy_state::djboy)
MCFG_CPU_VBLANK_INT_DRIVER("screen", djboy_state, irq0_line_hold)
MCFG_CPU_ADD("beast", I80C51, 6000000)
MCFG_CPU_IO_MAP(djboy_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(djboy_state, beast_p0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(djboy_state, beast_p0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(djboy_state, beast_p1_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(djboy_state, beast_p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(djboy_state, beast_p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(djboy_state, beast_p2_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(djboy_state, beast_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(djboy_state, beast_p3_w))
MCFG_QUANTUM_TIME(attotime::from_hz(6000))

2
src/mame/drivers/eolith.cpp
View File

@ -266,7 +266,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(eolith_state::sound_io_map)
AM_RANGE(0x0000, 0x7fff) AM_ROMBANK("sound_bank")
AM_RANGE(0x8000, 0x8000) AM_READ(sound_cmd_r)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(sound_p1_w)
ADDRESS_MAP_END
@ -553,6 +552,7 @@ MACHINE_CONFIG_START(eolith_state::eolith45)
MCFG_CPU_ADD("soundcpu", I8032, XTAL(12'000'000))
MCFG_CPU_PROGRAM_MAP(sound_prg_map)
MCFG_CPU_IO_MAP(sound_io_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(eolith_state, sound_p1_w))
MCFG_MCS51_SERIAL_TX_CB(WRITE8(eolith_state, soundcpu_to_qs1000)) // Sound CPU -> QS1000 CPU serial link
MCFG_MACHINE_RESET_OVERRIDE(eolith_state,eolith)

8
src/mame/drivers/fireball.cpp
View File

@ -304,10 +304,6 @@ ADDRESS_MAP_START(fireball_state::fireball_io_map)
AM_RANGE(0x04, 0x05)AM_READWRITE(io_04_r,io_04_w)
AM_RANGE(0x06, 0x07)AM_READWRITE(io_06_r,io_06_w)
//internal port
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
ADDRESS_MAP_END
@ -501,6 +497,10 @@ MACHINE_CONFIG_START(fireball_state::fireball)
MCFG_CPU_ADD("maincpu", I8031, CPU_CLK) //
MCFG_CPU_PROGRAM_MAP(fireball_map)
MCFG_CPU_IO_MAP(fireball_io_map)
MCFG_MCS51_PORT_P1_IN_CB(READ8(fireball_state, p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(fireball_state, p1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(fireball_state, p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(fireball_state, p3_w))
MCFG_TIMER_DRIVER_ADD_PERIODIC("int_0", fireball_state, int_0, attotime::from_hz(555)) //9ms from scope reading 111Hz take care of this in the handler
MCFG_EEPROM_SERIAL_X24C44_ADD("eeprom")

85
src/mame/drivers/hprot1.cpp
View File

@ -72,8 +72,8 @@ public:
, m_lcdc(*this, "hd44780")
{ }
//DECLARE_WRITE8_MEMBER(henry_io_w);
DECLARE_READ8_MEMBER(henry_io_r);
DECLARE_WRITE8_MEMBER(henry_p1_w);
DECLARE_WRITE8_MEMBER(henry_p3_w);
DECLARE_DRIVER_INIT(hprot1);
DECLARE_PALETTE_INIT(hprot1);
HD44780_PIXEL_UPDATE(hprot1_pixel_update);
@ -135,9 +135,6 @@ ADDRESS_MAP_START(hprot1_state::i80c31_io)
AM_RANGE(0xc030,0xc030) AM_MIRROR(0x13cf) AM_DEVREAD("hd44780", hd44780_device, data_read)
/*TODO: attach the watchdog/brownout reset device:
AM_RANGE(0xe000,0xe0??) AM_MIRROR(?) AM_DEVREAD("adm965an", adm965an_device, data_read) */
//AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(henry_io_r, henry_io_w)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(henry_io_r)
ADDRESS_MAP_END
static INPUT_PORTS_START( hprot1 )
@ -196,80 +193,17 @@ void hprot1_state::machine_reset()
{
}
READ8_MEMBER(hprot1_state::henry_io_r)
WRITE8_MEMBER(hprot1_state::henry_p1_w)
{
switch (offset)
{
case 0x01:
{
uint8_t value = ioport("inputs")->read();
#if LOG_IO_PORTS
printf("value:%02X\n", value);
#endif
return value;
}
default:
#if LOG_IO_PORTS
printf("Unhandled I/O Read at offset 0x%02X (return 0)\n", offset);
#endif
return 0;
}
if (LOG_IO_PORTS && data != 0xFF && data != 0xEF)
logerror("Write to P1: %02X\n", data);
}
/*
WRITE8_MEMBER(hprot1_state::henry_io_w)
WRITE8_MEMBER(hprot1_state::henry_p3_w)
{
static uint8_t p0=0, p1=0, p2=0, p3=0;
switch (offset)
{
case 0x00:
{
if (data != p0)
{
p0=data;
#if LOG_IO_PORTS
printf("Write to P0: %02X\n", data);
#endif
}
break;
}
case 0x01:
{
if (data != p1)
{
p1=data;
if (data != 0xFF && data != 0xEF)
#if LOG_IO_PORTS
printf("Write to P1: %02X\n", data);
#endif
}
break;
}
case 0x02:
{
if (data != p2)
{
p2=data;
#if LOG_IO_PORTS
printf("Write to P2: %02X\n", data);
#endif
}
break;
}
case 0x03:
{
if (data != p3)
{
p3=data;
#if LOG_IO_PORTS
printf("Write to P3: %02X\n", data);
#endif
}
break;
}
}
if (LOG_IO_PORTS)
logerror("Write to P3: %02X\n", data);
}
*/
PALETTE_INIT_MEMBER(hprot1_state, hprot1)
{
@ -310,6 +244,9 @@ MACHINE_CONFIG_START(hprot1_state::hprot1)
MCFG_CPU_ADD("maincpu", I80C31, XTAL(10'000'000))
MCFG_CPU_PROGRAM_MAP(i80c31_prg)
MCFG_CPU_IO_MAP(i80c31_io)
MCFG_MCS51_PORT_P1_IN_CB(IOPORT("inputs"))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(hprot1_state, henry_p1_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(hprot1_state, henry_p3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

18
src/mame/drivers/hvyunit.cpp
View File

@ -152,7 +152,6 @@ public:
void hvyunit(machine_config &config);
void master_io(address_map &map);
void master_memory(address_map &map);
void mcu_io(address_map &map);
void slave_io(address_map &map);
void slave_memory(address_map &map);
void sound_io(address_map &map);
@ -445,14 +444,6 @@ ADDRESS_MAP_START(hvyunit_state::sound_io)
ADDRESS_MAP_END
ADDRESS_MAP_START(hvyunit_state::mcu_io)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(mermaid_p0_r, mermaid_p0_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(mermaid_p1_r, mermaid_p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE(mermaid_p2_r, mermaid_p2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(mermaid_p3_r, mermaid_p3_w)
ADDRESS_MAP_END
/*************************************
*
* Port definitions
@ -635,7 +626,14 @@ MACHINE_CONFIG_START(hvyunit_state::hvyunit)
MCFG_CPU_VBLANK_INT_DRIVER("screen", hvyunit_state, irq0_line_hold)
MCFG_CPU_ADD("mermaid", I80C51, 6000000)
MCFG_CPU_IO_MAP(mcu_io)
MCFG_MCS51_PORT_P0_IN_CB(READ8(hvyunit_state, mermaid_p0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(hvyunit_state, mermaid_p0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(hvyunit_state, mermaid_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(hvyunit_state, mermaid_p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(hvyunit_state, mermaid_p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(hvyunit_state, mermaid_p2_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(hvyunit_state, mermaid_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(hvyunit_state, mermaid_p3_w))
MCFG_GENERIC_LATCH_8_ADD("mermaidlatch")
MCFG_GENERIC_LATCH_DATA_PENDING_CB(INPUTLINE("mermaid", INPUT_LINE_IRQ0))

33
src/mame/drivers/icatel.cpp
View File

@ -39,8 +39,10 @@ public:
DECLARE_READ8_MEMBER(magic_string);
DECLARE_READ8_MEMBER(ioport_r);
DECLARE_WRITE8_MEMBER(ioport_w);
DECLARE_READ8_MEMBER(i80c31_p1_r);
DECLARE_READ8_MEMBER(i80c31_p3_r);
DECLARE_WRITE8_MEMBER(i80c31_p1_w);
DECLARE_WRITE8_MEMBER(i80c31_p3_w);
DECLARE_READ8_MEMBER(cn8_extension_r);
DECLARE_WRITE8_MEMBER(cn8_extension_w);
@ -87,7 +89,6 @@ ADDRESS_MAP_START(icatel_state::i80c31_io)
AM_RANGE(0x80C0,0x80C0) AM_MIRROR(0x3F1F) AM_READWRITE(ci15_r, ci15_w) // 74LS244 (tristate buffer)
AM_RANGE(0xC000,0xCFFF) AM_READWRITE(cn8_extension_r, cn8_extension_w)
AM_RANGE(0xE000,0xEFFF) AM_READWRITE(modem_r, modem_w)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(ioport_r, ioport_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(icatel_state::i80c31_data)
@ -113,19 +114,21 @@ READ8_MEMBER(icatel_state::magic_string)
return mstr[offset%5];
}
READ8_MEMBER(icatel_state::ioport_r)
READ8_MEMBER(icatel_state::i80c31_p1_r)
{
switch (offset%4)
{
case 0: return 0xff;
case 1: return 0x7f;
case 2: return 0xff;
case 3: return 0xff;
}
return 0;
return 0x7f;
}
WRITE8_MEMBER(icatel_state::ioport_w)
READ8_MEMBER(icatel_state::i80c31_p3_r)
{
return 0xff;
}
WRITE8_MEMBER(icatel_state::i80c31_p1_w)
{
}
WRITE8_MEMBER(icatel_state::i80c31_p3_w)
{
}
@ -249,6 +252,10 @@ MACHINE_CONFIG_START(icatel_state::icatel)
MCFG_CPU_PROGRAM_MAP(i80c31_prg)
MCFG_CPU_DATA_MAP(i80c31_data)
MCFG_CPU_IO_MAP(i80c31_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(icatel_state, i80c31_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(icatel_state, i80c31_p1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(icatel_state, i80c31_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(icatel_state, i80c31_p3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

12
src/mame/drivers/karnov.cpp
View File

@ -866,19 +866,15 @@ ADDRESS_MAP_START(karnov_state::chelnovjbl_mcu_map)
AM_RANGE(0x0000, 0x1fff) AM_ROM
ADDRESS_MAP_END
ADDRESS_MAP_START(karnov_state::chelnovjbl_mcu_io_map)
//internal port
// AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(p1_r, p1_w)
// AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
ADDRESS_MAP_END
MACHINE_CONFIG_START(karnov_state::chelnovjbl)
karnov(config);
MCFG_CPU_ADD("mcu", I8031, 2000000) // ??mhz
MCFG_CPU_PROGRAM_MAP(chelnovjbl_mcu_map)
MCFG_CPU_IO_MAP(chelnovjbl_mcu_io_map)
// MCFG_MCS51_PORT_P1_IN_CB(READ8(karnov_state, p1_r))
// MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(karnov_state, p1_w))
// MCFG_MCS51_PORT_P3_IN_CB(READ8(karnov_state, p3_r))
// MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(karnov_state, p3_w))
MACHINE_CONFIG_END

11
src/mame/drivers/limenko.cpp
View File

@ -120,7 +120,6 @@ public:
void limenko_map(address_map &map);
void spotty_io_map(address_map &map);
void spotty_map(address_map &map);
void spotty_sound_io_map(address_map &map);
};
/*****************************************************************************************************
@ -300,11 +299,6 @@ READ8_MEMBER(limenko_state::spotty_sound_r)
return m_oki->read(space,0);
}
ADDRESS_MAP_START(limenko_state::spotty_sound_io_map)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ(spotty_sound_r) AM_DEVWRITE("oki", okim6295_device, write) //? sound latch and ?
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(spotty_sound_cmd_r, spotty_sound_cmd_w) //not sure about anything...
ADDRESS_MAP_END
/*****************************************************************************************************
VIDEO HARDWARE EMULATION
*****************************************************************************************************/
@ -780,7 +774,10 @@ MACHINE_CONFIG_START(limenko_state::spotty)
MCFG_CPU_VBLANK_INT_DRIVER("screen", limenko_state, irq0_line_hold)
MCFG_CPU_ADD("audiocpu", AT89C4051, 4000000) /* 4 MHz */
MCFG_CPU_IO_MAP(spotty_sound_io_map)
MCFG_MCS51_PORT_P1_IN_CB(READ8(limenko_state, spotty_sound_r))
MCFG_MCS51_PORT_P1_OUT_CB(DEVWRITE8("oki", okim6295_device, write)) //? sound latch and ?
MCFG_MCS51_PORT_P3_IN_CB(READ8(limenko_state, spotty_sound_cmd_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(limenko_state, spotty_sound_cmd_w)) //not sure about anything...
MCFG_EEPROM_SERIAL_93C46_ADD("eeprom")

22
src/mame/drivers/m72.cpp
View File

@ -397,22 +397,15 @@ READ8_MEMBER(m72_state::mcu_snd_r)
return m_mcu_snd_cmd_latch;
}
READ8_MEMBER(m72_state::mcu_port_r)
WRITE8_MEMBER(m72_state::mcu_port1_w)
{
logerror("port read: %02x\n", offset);
return 0;
m_mcu_sample_latch = data;
m_soundcpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
}
WRITE8_MEMBER(m72_state::mcu_port_w)
WRITE8_MEMBER(m72_state::mcu_port3_w)
{
if (offset == 1)
{
m_mcu_sample_latch = data;
m_soundcpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
}
else
logerror("port: %02x %02x\n", offset, data);
logerror("port3: %02x\n", data);
}
WRITE8_MEMBER(m72_state::mcu_low_w)
@ -1121,9 +1114,6 @@ ADDRESS_MAP_START(m72_state::mcu_io_map)
AM_RANGE(0x0002, 0x0002) AM_READWRITE(mcu_snd_r, mcu_ack_w)
/* shared at b0000 - b0fff on the main cpu */
AM_RANGE(0xc000, 0xcfff) AM_READWRITE(mcu_data_r,mcu_data_w )
/* Ports */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(mcu_port_r, mcu_port_w)
ADDRESS_MAP_END
#define COIN_MODE_1 \
@ -1904,6 +1894,8 @@ MACHINE_CONFIG_START(m72_state::m72_8751)
MCFG_CPU_ADD("mcu",I8751, XTAL(8'000'000)) /* Uses its own XTAL */
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(m72_state, mcu_port1_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(m72_state, mcu_port3_w))
MCFG_CPU_VBLANK_INT_DRIVER("screen", m72_state, mcu_int)
MACHINE_CONFIG_END

14
src/mame/drivers/marywu.cpp
View File

@ -38,7 +38,6 @@ public:
DECLARE_WRITE8_MEMBER(ay2_port_a_w);
DECLARE_WRITE8_MEMBER(ay2_port_b_w);
DECLARE_READ8_MEMBER(keyboard_r);
DECLARE_READ8_MEMBER(port_r);
void marywu(machine_config &config);
void io_map(address_map &map);
void program_map(address_map &map);
@ -138,17 +137,6 @@ WRITE8_MEMBER( marywu_state::multiplex_7seg_w )
m_selected_7seg_module = data;
}
READ8_MEMBER( marywu_state::port_r )
{
//TODO: figure out what each bit is mapped to in the 80c31 ports P1 and P3
switch(offset){
//case 1:
// return (1 << 6);
default:
return 0x00;
}
}
READ8_MEMBER( marywu_state::keyboard_r )
{
switch(m_selected_7seg_module % 8){
@ -181,7 +169,6 @@ ADDRESS_MAP_START(marywu_state::io_map)
AM_RANGE(0x9003, 0x9003) AM_MIRROR(0x0ffc) AM_DEVREADWRITE("ay2", ay8910_device, data_r, data_w)
AM_RANGE(0xb000, 0xb001) AM_MIRROR(0x0ffe) AM_DEVREADWRITE("i8279", i8279_device, read, write)
AM_RANGE(0xf000, 0xf000) AM_NOP /* TODO: Investigate this. There's something going on at this address range. */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(port_r)
ADDRESS_MAP_END
MACHINE_CONFIG_START(marywu_state::marywu)
@ -189,6 +176,7 @@ MACHINE_CONFIG_START(marywu_state::marywu)
MCFG_CPU_ADD("maincpu", I80C31, XTAL(10'738'635)) //actual CPU is a Winbond w78c31b-24
MCFG_CPU_PROGRAM_MAP(program_map)
MCFG_CPU_IO_MAP(io_map)
//TODO: figure out what each bit is mapped to in the 80c31 ports P1 and P3
/* Keyboard & display interface */
MCFG_DEVICE_ADD("i8279", I8279, XTAL(10'738'635)) /* should it be perhaps a fraction of the XTAL clock ? */

15
src/mame/drivers/maygay1b.cpp
View File

@ -761,13 +761,6 @@ READ8_MEMBER(maygay1b_state::mcu_port2_r)
return ret;
}
ADDRESS_MAP_START(maygay1b_state::maygay_mcu_io)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE( mcu_port0_r, mcu_port0_w )
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE( mcu_port1_w )
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READWRITE( mcu_port2_r, mcu_port2_w )
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE( mcu_port3_w )
ADDRESS_MAP_END
// machine driver for maygay m1 board /////////////////////////////////
@ -777,8 +770,12 @@ MACHINE_CONFIG_START(maygay1b_state::maygay_m1)
MCFG_CPU_PROGRAM_MAP(m1_memmap)
MCFG_CPU_ADD("mcu", I80C51, 2000000) // EP840034.A-P-80C51AVW
MCFG_CPU_IO_MAP(maygay_mcu_io)
MCFG_MCS51_PORT_P0_IN_CB(READ8(maygay1b_state, mcu_port0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(maygay1b_state, mcu_port0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(maygay1b_state, mcu_port1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(maygay1b_state, mcu_port2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(maygay1b_state, mcu_port2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(maygay1b_state, mcu_port3_w))
MCFG_DEVICE_ADD("duart68681", MC68681, M1_DUART_CLOCK)
MCFG_MC68681_IRQ_CALLBACK(WRITELINE(maygay1b_state, duart_irq_handler))

12
src/mame/drivers/mephistp.cpp
View File

@ -125,11 +125,6 @@ ADDRESS_MAP_START(mephisto_pinball_state::mephisto_8051_io)
AM_RANGE(0x0000, 0x07ff) AM_RAM
AM_RANGE(0x0800, 0x0800) AM_WRITE(sound_rombank_w)
AM_RANGE(0x1000, 0x1000) AM_DEVWRITE("dac", dac08_device, write)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_NOP // AD0-AD7
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(ay8910_read, ay8910_write)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITENOP // A8-A15
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE(t0_t1_w)
AM_RANGE(MCS51_PORT_TX, MCS51_PORT_TX) AM_READNOP // from MUART
ADDRESS_MAP_END
#ifdef UNUSED_DEFINITION
@ -178,8 +173,11 @@ MACHINE_CONFIG_START(mephisto_pinball_state::mephisto)
//MCFG_I8155_OUT_TIMEROUT_CB(WRITELINE(mephisto_pinball_state, clk_shift_w))
MCFG_CPU_ADD("soundcpu", I8051, XTAL(12'000'000))
MCFG_CPU_PROGRAM_MAP(mephisto_8051_map)
MCFG_CPU_IO_MAP(mephisto_8051_io)
MCFG_CPU_PROGRAM_MAP(mephisto_8051_map) // EA tied high for external program ROM
MCFG_MCS51_PORT_P1_IN_CB(READ8(mephisto_pinball_state, ay8910_read))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(mephisto_pinball_state, ay8910_write))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(mephisto_pinball_state, t0_t1_w))
MCFG_MCS51_SERIAL_RX_CB(NOOP) // from MUART
MCFG_SPEAKER_STANDARD_MONO("mono")

5
src/mame/drivers/micro3d.cpp
View File

@ -285,7 +285,6 @@ ADDRESS_MAP_START(micro3d_state::soundmem_io)
AM_RANGE(0xfe00, 0xfe00) AM_WRITE(micro3d_upd7759_w)
AM_RANGE(0xff00, 0xff00) AM_WRITE(micro3d_snd_dac_a)
AM_RANGE(0xff01, 0xff01) AM_WRITE(micro3d_snd_dac_b)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(micro3d_sound_io_r, micro3d_sound_io_w)
ADDRESS_MAP_END
@ -324,6 +323,10 @@ MACHINE_CONFIG_START(micro3d_state::micro3d)
MCFG_CPU_ADD("audiocpu", I8051, XTAL(11'059'200))
MCFG_CPU_PROGRAM_MAP(soundmem_prg)
MCFG_CPU_IO_MAP(soundmem_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(micro3d_state, micro3d_sound_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(micro3d_state, micro3d_sound_p1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(micro3d_state, micro3d_sound_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(micro3d_state, micro3d_sound_p3_w))
MCFG_MCS51_SERIAL_TX_CB(WRITE8(micro3d_state, data_from_i8031))
MCFG_MCS51_SERIAL_RX_CB(READ8(micro3d_state, data_to_i8031))

201
src/mame/drivers/minicom.cpp
View File

@ -52,11 +52,14 @@ public:
, m_maincpu(*this, "maincpu")
{ }
DECLARE_WRITE8_MEMBER(minicom_io_w);
DECLARE_READ8_MEMBER(minicom_io_r);
DECLARE_WRITE8_MEMBER(i87c52_p0_w);
DECLARE_WRITE8_MEMBER(i87c52_p1_w);
DECLARE_WRITE8_MEMBER(i87c52_p2_w);
DECLARE_WRITE8_MEMBER(i87c52_p3_w);
DECLARE_READ8_MEMBER(i87c52_p1_r);
DECLARE_READ8_MEMBER(i87c52_p2_r);
DECLARE_DRIVER_INIT(minicom);
void minicom(machine_config &config);
void i87c52_io(address_map &map);
private:
uint8_t m_p[4];
uint16_t m_display_data;
@ -66,10 +69,6 @@ private:
required_device<cpu_device> m_maincpu;
};
ADDRESS_MAP_START(minicom_state::i87c52_io)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(minicom_io_r, minicom_io_w)
ADDRESS_MAP_END
void minicom_state::machine_start()
{
// zerofill
@ -92,24 +91,18 @@ void minicom_state::machine_reset()
output().set_digit_value(i, 0);
}
READ8_MEMBER(minicom_state::minicom_io_r)
READ8_MEMBER(minicom_state::i87c52_p1_r)
{
//P1.3 seems to be an indicator of whether or not we have a printer device attached.
// at address 0xABF the code checks this flag in order to decide which string to display:
// "MINIPRINT IS RESET" or "MINICOM IS RESET"
return PRINTER_ATTACHED << 3;
}
READ8_MEMBER(minicom_state::i87c52_p2_r)
{
switch (offset)
{
case 1:
//P1.3 seems to be an indicator of whether or not we have a printer device attached.
// at address 0xABF the code checks this flag in order to decide which string to display:
// "MINIPRINT IS RESET" or "MINICOM IS RESET"
return PRINTER_ATTACHED << 3;
case 2:
// return 0; //para a palestra no Garoa... :-)
return 1; //to skip the "NO POWER" warning. I'm not sure why.
default:
#if LOG_IO_PORTS
printf("Unhandled I/O Read at offset 0x%02X (return 0)\n", offset);
#endif
return 0;
}
return 1; //to skip the "NO POWER" warning. I'm not sure why.
}
#if LOG_IO_PORTS
@ -125,101 +118,94 @@ static void printbits(uint8_t v) {
#define P1_UNKNOWN_BITS (0xFF & ~(1 << 2))
#define P2_UNKNOWN_BITS 0xFF
#define P3_UNKNOWN_BITS (0xFF & ~((1 << 4)|(1 << 5)))
WRITE8_MEMBER(minicom_state::minicom_io_w)
WRITE8_MEMBER(minicom_state::i87c52_p0_w)
{
switch (offset)
if (data != m_p[0])
{
case 0x00:
{
if (data != m_p[offset])
{
m_p[offset]=data;
m_p[0]=data;
//Bit P0.1 is the serial-input of a 20-bit shift register (made of a couple of chained UCN5810AF chips)
//We are emulating the display based on the assumption that the firmware will multiplex it by defining one digit at a given time
//It would be better (in terms of being closer to the actual hardware) to emulate the 20 bit shift register and update all digits
//for which a bit is TTL high. It seems to me that in the real hardware that would result in dimmer brightness in the display and it
//does not seem trivial to me to implement this using our current layout system. I'm leaving this note to whoever finds it exciting
//Bit P0.1 is the serial-input of a 20-bit shift register (made of a couple of chained UCN5810AF chips)
//We are emulating the display based on the assumption that the firmware will multiplex it by defining one digit at a given time
//It would be better (in terms of being closer to the actual hardware) to emulate the 20 bit shift register and update all digits
//for which a bit is TTL high. It seems to me that in the real hardware that would result in dimmer brightness in the display and it
//does not seem trivial to me to implement this using our current layout system. I'm leaving this note to whoever finds it exciting
//to explore these possibilities (perhaps myself in the future?).
if (BIT(data,1)){
m_digit_index = 0;
}
}
break;
if (BIT(data,1)){
m_digit_index = 0;
}
case 0x01:
{
if (data != m_p[offset])
{
}
}
WRITE8_MEMBER(minicom_state::i87c52_p1_w)
{
if (data != m_p[1])
{
#if LOG_IO_PORTS
uint8_t changed = m_p[offset] ^ data;
if (changed ^ P1_UNKNOWN_BITS)
{
printf("Write to P1: %02X changed: ( ) (", data);
printbits(changed);
printf(") ( ) ( )\n");
}
uint8_t changed = m_p[1] ^ data;
if (changed ^ P1_UNKNOWN_BITS)
{
printf("Write to P1: %02X changed: ( ) (", data);
printbits(changed);
printf(") ( ) ( )\n");
}
#endif
if (FALLING_EDGE(m_p[offset], data, 2))
{
m_digit_index--;
if (m_digit_index<0) m_digit_index = 19;
}
m_p[offset]=data;
}
break;
}
case 0x02:
if (FALLING_EDGE(m_p[offset], data, 2))
{
if (data != m_p[offset])
{
m_digit_index--;
if (m_digit_index<0) m_digit_index = 19;
}
m_p[1] = data;
}
}
WRITE8_MEMBER(minicom_state::i87c52_p2_w)
{
if (data != m_p[2])
{
#if LOG_IO_PORTS
uint8_t changed = m_p[offset] ^ data;
if (changed ^ P2_UNKNOWN_BITS)
{
printf("Write to P2: %02X changed: ( ) ( ) (", data);
printbits(changed);
printf(") ( )\n");
}
uint8_t changed = m_p[2] ^ data;
if (changed ^ P2_UNKNOWN_BITS)
{
printf("Write to P2: %02X changed: ( ) ( ) (", data);
printbits(changed);
printf(") ( )\n");
}
#endif
m_p[offset]=data;
}
break;
}
case 0x03:
{
if (data != m_p[offset])
{
uint8_t changed = m_p[offset] ^ data;
m_p[2] = data;
}
}
WRITE8_MEMBER(minicom_state::i87c52_p3_w)
{
if (data != m_p[3])
{
uint8_t changed = m_p[3] ^ data;
#if LOG_IO_PORTS
if (changed ^ P3_UNKNOWN_BITS)
{
printf("Write to P3: %02X changed: ( ) ( ) ( ) (", data);
printbits(changed);
printf(")\n");
}
if (changed ^ P3_UNKNOWN_BITS)
{
printf("Write to P3: %02X changed: ( ) ( ) ( ) (", data);
printbits(changed);
printf(")\n");
}
#endif
if (FALLING_EDGE(m_p[offset], data, 4)) //P3.4 = T0
{
m_display_data &= 0xFF00;
m_display_data |= m_p[0];
}
if (FALLING_EDGE(m_p[offset], data, 5)) //P3.5 = T1
{
m_display_data &= 0xFF;
m_display_data |= (m_p[0] << 8);
}
if (BIT(changed,4) || BIT(changed,5))
{
output().set_digit_value(m_digit_index, bitswap<16>(m_display_data, 9, 1, 3, 11, 12, 4, 2, 10, 14, 6, 7, 5, 0, 15, 13, 8) & 0x3FFF);
}
m_p[offset]=data;
}
break;
if (FALLING_EDGE(m_p[3], data, 4)) //P3.4 = T0
{
m_display_data &= 0xFF00;
m_display_data |= m_p[0];
}
if (FALLING_EDGE(m_p[3], data, 5)) //P3.5 = T1
{
m_display_data &= 0xFF;
m_display_data |= (m_p[0] << 8);
}
if (BIT(changed,4) || BIT(changed,5))
{
output().set_digit_value(m_digit_index, bitswap<16>(m_display_data, 9, 1, 3, 11, 12, 4, 2, 10, 14, 6, 7, 5, 0, 15, 13, 8) & 0x3FFF);
}
m_p[3] = data;
}
}
@ -230,7 +216,12 @@ DRIVER_INIT_MEMBER( minicom_state, minicom )
MACHINE_CONFIG_START(minicom_state::minicom)
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I87C52, XTAL(10'000'000)) /*FIX-ME: verify the correct clock frequency */
MCFG_CPU_IO_MAP(i87c52_io)
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(minicom_state, i87c52_p0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(minicom_state, i87c52_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(minicom_state, i87c52_p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(minicom_state, i87c52_p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(minicom_state, i87c52_p2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(minicom_state, i87c52_p3_w))
/* video hardware */
/* fluorescent 14-segment display forming a row of 20 characters */

159
src/mame/drivers/minitel_2_rpic.cpp
View File

@ -98,8 +98,10 @@ public:
TIMER_DEVICE_CALLBACK_MEMBER(minitel_scanline);
DECLARE_WRITE8_MEMBER ( port_w );
DECLARE_READ8_MEMBER ( port_r );
DECLARE_WRITE8_MEMBER(port1_w);
DECLARE_WRITE8_MEMBER(port3_w);
DECLARE_READ8_MEMBER(port1_r);
DECLARE_READ8_MEMBER(port3_r);
DECLARE_WRITE8_MEMBER ( dev_crtl_reg_w );
DECLARE_READ8_MEMBER ( dev_keyb_ser_r );
@ -114,12 +116,12 @@ protected:
required_ioport_array<16> m_io_kbd;
virtual void machine_start() override;
char port0, port1, port2, port3;
uint8_t port1, port3;
int keyboard_para_ser;
unsigned char keyboard_x_row_reg;
uint8_t keyboard_x_row_reg;
unsigned char last_ctrl_reg;
uint8_t last_ctrl_reg;
};
void minitel_state::machine_start()
@ -134,95 +136,74 @@ void minitel_state::machine_start()
m_palette->set_pen_color( 7, 255, 255, 255);
}
WRITE8_MEMBER(minitel_state::port_w)
WRITE8_MEMBER(minitel_state::port1_w)
{
LOG("port_w: write %02X to PORT (offset=%02X)\n", data, offset);
LOG("port_w: write %02X to PORT1\n", data);
switch(offset| 0x20000)
if( (port1 ^ data) & PORT_1_KBSERIN )
{
case MCS51_PORT_P0:
port0 = data;
break;
case MCS51_PORT_P1:
if( (port1 ^ data) & PORT_1_KBSERIN )
{
LOG("PORT_1_KBSERIN : %d \n", data & PORT_1_KBSERIN );
}
if( (port1 ^ data) & PORT_1_MDM_DCD )
{
LOG("PORT_1_MDM_DCD : %d \n", data & PORT_1_MDM_DCD );
}
if( (port1 ^ data) & PORT_1_MDM_PRD )
{
LOG("PORT_1_MDM_PRD : %d \n", data & PORT_1_MDM_PRD );
}
if( (port1 ^ data) & PORT_1_MDM_TXD )
{
LOG("PORT_1_MDM_TXD : %d \n", data & PORT_1_MDM_TXD );
}
if( (port1 ^ data) & PORT_1_MDM_RTS )
{
LOG("PORT_1_MDM_RTS : %d \n", data & PORT_1_MDM_RTS );
}
if( (port1 ^ data) & PORT_1_KBLOAD )
{
LOG("PORT_1_KBLOAD : %d PC:0x%x\n", data & PORT_1_KBLOAD,m_maincpu->pc() );
if(data & PORT_1_KBLOAD)
keyboard_para_ser = 1;
else
keyboard_para_ser = 0;
}
if( (port1 ^ data) & PORT_1_SCL )
{
LOG("PORT_1_SCL : %d \n", data & PORT_1_SCL );
}
if( (port1 ^ data) & PORT_1_SDA )
{
LOG("PORT_1_SDA : %d \n", data & PORT_1_SDA );
}
port1=data;
break;
case MCS51_PORT_P2:
port2=data;
break;
case MCS51_PORT_P3:
port3=data;
break;
LOG("PORT_1_KBSERIN : %d \n", data & PORT_1_KBSERIN );
}
if( (port1 ^ data) & PORT_1_MDM_DCD )
{
LOG("PORT_1_MDM_DCD : %d \n", data & PORT_1_MDM_DCD );
}
if( (port1 ^ data) & PORT_1_MDM_PRD )
{
LOG("PORT_1_MDM_PRD : %d \n", data & PORT_1_MDM_PRD );
}
if( (port1 ^ data) & PORT_1_MDM_TXD )
{
LOG("PORT_1_MDM_TXD : %d \n", data & PORT_1_MDM_TXD );
}
if( (port1 ^ data) & PORT_1_MDM_RTS )
{
LOG("PORT_1_MDM_RTS : %d \n", data & PORT_1_MDM_RTS );
}
if( (port1 ^ data) & PORT_1_KBLOAD )
{
LOG("PORT_1_KBLOAD : %d PC:0x%x\n", data & PORT_1_KBLOAD,m_maincpu->pc() );
if(data & PORT_1_KBLOAD)
keyboard_para_ser = 1;
else
keyboard_para_ser = 0;
}
if( (port1 ^ data) & PORT_1_SCL )
{
LOG("PORT_1_SCL : %d \n", data & PORT_1_SCL );
}
if( (port1 ^ data) & PORT_1_SDA )
{
LOG("PORT_1_SDA : %d \n", data & PORT_1_SDA );
}
port1 = data;
}
READ8_MEMBER(minitel_state::port_r)
WRITE8_MEMBER(minitel_state::port3_w)
{
LOG("port_r: read PORT (offset=%02X) %x\n", offset,m_maincpu->pc());
LOG("port_w: write %02X to PORT3\n", data);
port3 = data;
}
switch(offset | 0x20000)
{
case MCS51_PORT_P0:
LOG("port_r: read %02X from PORT0\n", port0);
return port0;
case MCS51_PORT_P1:
LOG("port_r: read %02X from PORT1 - Keyboard -> %x\n", port1,((keyboard_x_row_reg>>7)&1));
return ( (port1&0xFE) | ((keyboard_x_row_reg>>7)&1) ) ;
case MCS51_PORT_P2:
LOG("port_r: read %02X from PORT2\n", port2);
return port2;
case MCS51_PORT_P3:
LOG("port_r: read %02X from PORT3\n", port3);
return port3;
}
return 0;
READ8_MEMBER(minitel_state::port1_r)
{
LOG("port_r: read %02X from PORT1 - Keyboard -> %x\n", port1,((keyboard_x_row_reg>>7)&1));
return ( (port1&0xFE) | ((keyboard_x_row_reg>>7)&1) ) ;
}
READ8_MEMBER(minitel_state::port3_r)
{
LOG("port_r: read %02X from PORT3\n", port3);
return port3;
}
WRITE8_MEMBER(minitel_state::dev_crtl_reg_w)
@ -304,7 +285,6 @@ ADDRESS_MAP_START(minitel_state::mem_io)
AM_RANGE(0x2000, 0x3fff) AM_READWRITE(dev_keyb_ser_r, dev_crtl_reg_w)
/* ts9347 */
AM_RANGE(0x4000, 0x5ffF) AM_READWRITE(ts9347_io_r, ts9347_io_w)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(port_r, port_w)
ADDRESS_MAP_END
/* Input ports */
@ -419,7 +399,10 @@ MACHINE_CONFIG_START(minitel_state::minitel2)
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", I80C32, XTAL(14'318'181)) //verified on pcb
MCFG_CPU_PROGRAM_MAP(mem_prg)
MCFG_CPU_IO_MAP(mem_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(minitel_state, port1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(minitel_state, port1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(minitel_state, port3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(minitel_state, port3_w))
MCFG_DEVICE_ADD("ts9347", TS9347, 0)
MCFG_EF9345_PALETTE("palette")

27
src/mame/drivers/peplus.cpp
View File

@ -246,8 +246,7 @@ public:
m_s7000_ram(*this, "s7000_ram"),
m_sb000_ram(*this, "sb000_ram"),
m_sd000_ram(*this, "sd000_ram"),
m_sf000_ram(*this, "sf000_ram"),
m_io_port(*this, "io_port")
m_sf000_ram(*this, "sf000_ram")
{
}
@ -276,7 +275,6 @@ public:
required_shared_ptr<uint8_t> m_sb000_ram;
required_shared_ptr<uint8_t> m_sd000_ram;
required_shared_ptr<uint8_t> m_sf000_ram;
required_shared_ptr<uint8_t> m_io_port;
tilemap_t *m_bg_tilemap;
uint8_t m_wingboard;
@ -305,8 +303,12 @@ public:
uint8_t m_bv_data_bit;
uint8_t m_bv_loop_count;
uint16_t id023_data;
uint8_t m_paldata;
uint8_t m_paldata2;
DECLARE_WRITE8_MEMBER(peplus_bgcolor_w);
DECLARE_WRITE8_MEMBER(paldata_w);
DECLARE_WRITE8_MEMBER(paldata2_w);
DECLARE_WRITE8_MEMBER(peplus_crtc_display_w);
DECLARE_WRITE8_MEMBER(peplus_duart_w);
DECLARE_WRITE8_MEMBER(peplus_cmos_w);
@ -446,11 +448,21 @@ WRITE_LINE_MEMBER(peplus_state::crtc_vsync)
handle_lightpen();
}
WRITE8_MEMBER(peplus_state::paldata_w)
{
m_paldata = data;
}
WRITE8_MEMBER(peplus_state::paldata2_w)
{
m_paldata2 = data;
}
WRITE8_MEMBER(peplus_state::peplus_crtc_display_w)
{
m_videoram[m_vid_address] = data;
m_palette_ram[m_vid_address] = m_io_port[1];
m_palette_ram2[m_vid_address] = m_io_port[3];
m_palette_ram[m_vid_address] = m_paldata;
m_palette_ram2[m_vid_address] = m_paldata2;
m_bg_tilemap->mark_tile_dirty(m_vid_address);
@ -1055,9 +1067,6 @@ ADDRESS_MAP_START(peplus_state::peplus_iomap)
// Superboard Data
AM_RANGE(0xf000, 0xffff) AM_RAM AM_SHARE("sf000_ram")
/* Ports start here */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_RAM AM_SHARE("io_port")
ADDRESS_MAP_END
@ -1333,6 +1342,8 @@ MACHINE_CONFIG_START(peplus_state::peplus)
MCFG_CPU_ADD("maincpu", I80C32, XTAL(20'000'000)/2) /* 10MHz */
MCFG_CPU_PROGRAM_MAP(peplus_map)
MCFG_CPU_IO_MAP(peplus_iomap)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(peplus_state, paldata_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(peplus_state, paldata2_w))
MCFG_NVRAM_ADD_0FILL("cmos")

3
src/mame/drivers/piggypas.cpp
View File

@ -75,8 +75,6 @@ ADDRESS_MAP_START(piggypas_state::piggypas_io)
AM_RANGE(0x1000, 0x1000) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE(0x1800, 0x1801) AM_DEVWRITE("hd44780", hd44780_device, write)
AM_RANGE(0x1802, 0x1803) AM_DEVREAD("hd44780", hd44780_device, read)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READ_PORT("IN2")
ADDRESS_MAP_END
@ -133,6 +131,7 @@ MACHINE_CONFIG_START(piggypas_state::piggypas)
MCFG_CPU_ADD("maincpu", I80C31, XTAL(8'448'000)) // OKI M80C31F or M80C154S
MCFG_CPU_PROGRAM_MAP(piggypas_map)
MCFG_CPU_IO_MAP(piggypas_io)
MCFG_MCS51_PORT_P3_IN_CB(IOPORT("IN2"))
MCFG_MCS51_SERIAL_TX_CB(WRITE8(piggypas_state, mcs51_tx_callback))
// MCFG_CPU_VBLANK_INT_DRIVER("screen", piggypas_state, irq0_line_hold)

3
src/mame/drivers/rbmk.cpp
View File

@ -240,8 +240,6 @@ WRITE8_MEMBER(rbmk_state::mcu_io_mux_w)
ADDRESS_MAP_START(rbmk_state::mcu_io)
AM_RANGE(0x0ff00, 0x0ffff) AM_READWRITE(mcu_io_r, mcu_io_w )
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE(mcu_io_mux_w )
ADDRESS_MAP_END
static INPUT_PORTS_START( rbmk )
@ -572,6 +570,7 @@ MACHINE_CONFIG_START(rbmk_state::rbmk)
MCFG_CPU_ADD("mcu", AT89C4051, 22000000 / 4) // frequency isn't right
MCFG_CPU_PROGRAM_MAP(mcu_mem)
MCFG_CPU_IO_MAP(mcu_io)
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(rbmk_state, mcu_io_mux_w))
MCFG_CPU_VBLANK_INT_DRIVER("screen", rbmk_state, mcu_irq)
MCFG_GFXDECODE_ADD("gfxdecode", "palette", rbmk)

4
src/mame/drivers/re900.cpp
View File

@ -258,9 +258,6 @@ ADDRESS_MAP_START(re900_state::mem_io)
AM_RANGE(0xe001, 0xe001) AM_DEVWRITE("tms9128", tms9928a_device, register_write)
AM_RANGE(0xe800, 0xe801) AM_DEVWRITE("ay_re900", ay8910_device, address_data_w)
AM_RANGE(0xe802, 0xe802) AM_DEVREAD("ay_re900", ay8910_device, data_r)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_WRITE(cpu_port_0_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_NOP
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_NOP
ADDRESS_MAP_END
@ -387,6 +384,7 @@ MACHINE_CONFIG_START(re900_state::re900)
MCFG_CPU_ADD("maincpu", I8051, MAIN_CLOCK)
MCFG_CPU_PROGRAM_MAP(mem_prg)
MCFG_CPU_IO_MAP(mem_io)
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(re900_state, cpu_port_0_w))
/* video hardware */
MCFG_DEVICE_ADD( "tms9128", TMS9128, XTAL(10'738'635) / 2 ) /* TMS9128NL on the board */

5
src/mame/drivers/rmnimbus.cpp
View File

@ -97,7 +97,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(rmnimbus_state::nimbus_iocpu_io)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000, 0x000FF) AM_READWRITE(nimbus_pc8031_iou_r, nimbus_pc8031_iou_w)
AM_RANGE(0x20000, 0x20004) AM_READWRITE(nimbus_pc8031_port_r, nimbus_pc8031_port_w)
ADDRESS_MAP_END
MACHINE_CONFIG_START(rmnimbus_state::nimbus)
@ -112,6 +111,10 @@ MACHINE_CONFIG_START(rmnimbus_state::nimbus)
MCFG_CPU_ADD(IOCPU_TAG, I8031, 11059200)
MCFG_CPU_PROGRAM_MAP(nimbus_iocpu_mem)
MCFG_CPU_IO_MAP(nimbus_iocpu_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(rmnimbus_state, nimbus_pc8031_port1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(rmnimbus_state, nimbus_pc8031_port1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(rmnimbus_state, nimbus_pc8031_port3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(rmnimbus_state, nimbus_pc8031_port3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

4
src/mame/drivers/segas16a.cpp
View File

@ -1014,10 +1014,7 @@ ADDRESS_MAP_END
//**************************************************************************
ADDRESS_MAP_START(segas16a_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0xffff) AM_READWRITE(mcu_io_r, mcu_io_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READNOP AM_WRITE(mcu_control_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READNOP // read during jb int0
ADDRESS_MAP_END
@ -2060,6 +2057,7 @@ MACHINE_CONFIG_START(segas16a_state::system16a_i8751)
MCFG_CPU_ADD("mcu", I8751, 8000000)
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(segas16a_state, mcu_control_w))
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", segas16a_state, mcu_irq_assert)
MACHINE_CONFIG_END

3
src/mame/drivers/segas16b.cpp
View File

@ -1902,7 +1902,6 @@ WRITE8_MEMBER(segas16b_state::spin_68k_w)
ADDRESS_MAP_START(segas16b_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x001f) AM_MIRROR(0xff00) AM_DEVREADWRITE("mapper", sega_315_5195_mapper_device, read, write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ_PORT("SERVICE") AM_WRITE(spin_68k_w)
ADDRESS_MAP_END
@ -3791,6 +3790,8 @@ MACHINE_CONFIG_START(segas16b_state::system16b_i8751)
MCFG_CPU_ADD("mcu", I8751, MASTER_CLOCK_8MHz)
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_IN_CB(IOPORT("SERVICE"))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(segas16b_state, spin_68k_w))
MCFG_SCREEN_MODIFY("screen")
MCFG_SCREEN_VBLANK_CALLBACK(INPUTLINE("mcu", INPUT_LINE_IRQ0))

3
src/mame/drivers/sliver.cpp
View File

@ -395,8 +395,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(sliver_state::soundmem_io)
AM_RANGE(0x0100, 0x0100) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE(0x0101, 0x0101) AM_DEVREAD("soundlatch", generic_latch_8_device, read)
/* ports */
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(oki_setbank )
ADDRESS_MAP_END
ADDRESS_MAP_START(sliver_state::oki_map)
@ -520,6 +518,7 @@ MACHINE_CONFIG_START(sliver_state::sliver)
MCFG_CPU_ADD("audiocpu", I8051, 8000000)
MCFG_CPU_PROGRAM_MAP(soundmem_prg)
MCFG_CPU_IO_MAP(soundmem_io)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(sliver_state, oki_setbank))
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)

69
src/mame/drivers/snowbros.cpp
View File

@ -221,57 +221,29 @@ ADDRESS_MAP_START(snowbros_state::sound_io_map)
ADDRESS_MAP_END
READ8_MEMBER(snowbros_state::prot_io_r)
{
// never read?
return 0x00;
}
/* Semicom AT89C52 MCU */
// probably not endian safe
WRITE8_MEMBER(snowbros_state::prot_io_w)
WRITE8_MEMBER(snowbros_state::prot_p0_w)
{
switch (offset)
{
case 0x00:
{
uint16_t word = m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset];
word = (word & 0xff00) | (data << 0);
m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset] = word;
break;
}
case 0x01:
{
uint16_t word = m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset];
word = (word & 0x00ff) | (data << 8);
m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset] = word;
break;
}
case 0x02: // offset
{
m_semicom_prot_offset = data;
break;
}
case 0x03: // ??
{
//logerror("offset %02x data %02x\n",offset,data);
break;
}
}
uint16_t word = m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset];
word = (word & 0xff00) | (data << 0);
m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset] = word;
}
/* Semicom AT89C52 MCU */
ADDRESS_MAP_START(snowbros_state::protection_map)
AM_RANGE(0x0000, 0x1fff) AM_ROM
ADDRESS_MAP_END
// probably not endian safe
WRITE8_MEMBER(snowbros_state::prot_p1_w)
{
uint16_t word = m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset];
word = (word & 0x00ff) | (data << 8);
m_hyperpac_ram[(0xe000/2)+m_semicom_prot_offset] = word;
}
ADDRESS_MAP_START(snowbros_state::protection_iomap)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(prot_io_r,prot_io_w)
ADDRESS_MAP_END
WRITE8_MEMBER(snowbros_state::prot_p2_w)
{
// offset
m_semicom_prot_offset = data;
}
/* Winter Bobble - bootleg GFX chip */
@ -1835,9 +1807,10 @@ MACHINE_CONFIG_START(snowbros_state::semicom_mcu)
/* basic machine hardware */
MCFG_CPU_ADD("protection", I8052, XTAL(16'000'000)) // AT89C52
MCFG_CPU_PROGRAM_MAP(protection_map)
MCFG_CPU_IO_MAP(protection_iomap)
MCFG_CPU_ADD("protection", I80C52, XTAL(16'000'000)) // AT89C52
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(snowbros_state, prot_p0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(snowbros_state, prot_p1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(snowbros_state, prot_p2_w))
MACHINE_CONFIG_END

5
src/mame/drivers/spinb.cpp
View File

@ -191,8 +191,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(spinb_state::dmd_io)
AM_RANGE(0x0000, 0x1fff) AM_WRITE(dmdram_w)
AM_RANGE(0x0000, 0xffff) AM_READ(dmdram_r)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(p1_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(p3_r, p3_w)
ADDRESS_MAP_END
static INPUT_PORTS_START( spinb )
@ -642,6 +640,9 @@ MACHINE_CONFIG_START(spinb_state::spinb)
MCFG_CPU_ADD("dmdcpu",I8031, XTAL(16'000'000))
MCFG_CPU_PROGRAM_MAP(dmd_mem)
MCFG_CPU_IO_MAP(dmd_io)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(spinb_state, p1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(spinb_state, p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(spinb_state, p3_w))
MCFG_NVRAM_ADD_1FILL("nvram")

41
src/mame/drivers/splus.cpp
View File

@ -43,7 +43,6 @@ public:
m_cmosh_ram(*this, "cmosh"),
m_program_ram(*this, "program_ram"),
m_reel_ram(*this, "reel_ram"),
m_io_port(*this, "io_port"),
m_i10(*this, "I10"),
m_i20(*this, "I20"),
m_i30(*this, "I30"),
@ -60,6 +59,7 @@ public:
m_bank30 = 0x00;
m_bank40 = 0x00;
m_io_port1 = 0x00;
m_p1_reels = 0x00;
m_p1_unknown = 0x00;
}
@ -78,7 +78,6 @@ public:
required_shared_ptr<uint8_t> m_reel_ram;
// IO Ports
required_shared_ptr<uint8_t> m_io_port;
required_ioport m_i10;
required_ioport m_i20;
required_ioport m_i30;
@ -98,20 +97,21 @@ public:
uint8_t m_bank30;
uint8_t m_bank40;
uint8_t m_io_port1;
uint8_t m_p1_reels;
uint8_t m_p1_unknown;
int16_t m_stepper_pos[5];
uint8_t m_stop_pos[5];
DECLARE_WRITE8_MEMBER(splus_io_w);
DECLARE_WRITE8_MEMBER(splus_p1_w);
DECLARE_WRITE8_MEMBER(splus_load_pulse_w);
DECLARE_WRITE8_MEMBER(splus_serial_w);
DECLARE_WRITE8_MEMBER(splus_7seg_w);
DECLARE_WRITE8_MEMBER(splus_duart_w);
DECLARE_READ8_MEMBER(splus_serial_r);
DECLARE_READ8_MEMBER(splus_m_reel_ram_r);
DECLARE_READ8_MEMBER(splus_io_r);
DECLARE_READ8_MEMBER(splus_p3_r);
DECLARE_READ8_MEMBER(splus_duart_r);
DECLARE_READ8_MEMBER(splus_watchdog_r);
DECLARE_READ8_MEMBER(splus_registers_r);
@ -151,7 +151,7 @@ static const uint8_t optics[200] = {
* Write Handlers *
******************/
WRITE8_MEMBER(splus_state::splus_io_w)
WRITE8_MEMBER(splus_state::splus_p1_w)
{
// P1.0 = Reel 1 Controller
// P1.1 = Reel 2 Controller
@ -161,10 +161,11 @@ WRITE8_MEMBER(splus_state::splus_io_w)
// P1.5 = 7-seg display, door
// P1.6 = 7-seg display, prog
// P1.7 = Unknown
int x = 0;
m_io_port1 = data;
// Process Port 1
if (offset == 1 && ((data & 0x1f) != 0x00)) {
if ((data & 0x1f) != 0x00) {
// Unknown Bit 7
m_p1_unknown = (~data & 0x80);
@ -174,7 +175,7 @@ WRITE8_MEMBER(splus_state::splus_io_w)
m_p1_reels = (data & 0x1f);
// Loop through Reel Controllers
for (x = 0; x < 5; x++) {
for (int x = 0; x < 5; x++) {
// Test Reel Controller
if (((m_p1_reels >> x) & 1) == 0x01) {
// Forward Direction
@ -196,20 +197,18 @@ WRITE8_MEMBER(splus_state::splus_io_w)
osd_printf_info("Steppers %02X-%02X-%02X-%02X-%02X Motor=%02X Dir=%02X reels=%02X unk=%02X\n", m_stop_pos[0],m_stop_pos[1],m_stop_pos[2],m_stop_pos[3],m_stop_pos[4],((m_bank40 >> 0) & 1),((m_bank10 >> 5) & 1),(data & 0x1f), m_p1_unknown);
#endif
}
m_io_port[offset] = data;
}
WRITE8_MEMBER(splus_state::splus_load_pulse_w)
{
// uint8_t out = 0;
// out = ((~m_io_port[1] & 0xf0)>>4); // Output Bank
// out = ((~m_io_port1 & 0xf0)>>4); // Output Bank
}
WRITE8_MEMBER(splus_state::splus_serial_w)
{
uint8_t out = 0;
out = ((~m_io_port[1] & 0xe0)>>5); // Output Bank
out = ((~m_io_port1 & 0xe0)>>5); // Output Bank
switch (out)
{
@ -357,8 +356,8 @@ WRITE8_MEMBER(splus_state::splus_7seg_w)
seg = ((~data & 0xf0)>>4); // Segment Number
val = (~data & 0x0f); // Digit Value
// Need to add ~m_io_port[1]-1 to seg value
if (seg < 0x0a && (m_io_port[1] & 0xe0) == 0xe0)
// Need to add ~m_io_port1-1 to seg value
if (seg < 0x0a && (m_io_port1 & 0xe0) == 0xe0)
output().set_digit_value(seg, ls48_map[val]);
}
@ -387,7 +386,7 @@ READ8_MEMBER(splus_state::splus_serial_r)
uint8_t in = 0x00;
uint8_t val = 0x00;
in = ((~m_io_port[1] & 0xe0)>>5); // Input Bank
in = ((~m_io_port1 & 0xe0)>>5); // Input Bank
switch (in)
{
@ -524,12 +523,9 @@ READ8_MEMBER(splus_state::splus_m_reel_ram_r)
return m_reel_ram[offset];
}
READ8_MEMBER(splus_state::splus_io_r)
READ8_MEMBER(splus_state::splus_p3_r)
{
if (offset == 3)
return m_io_port[offset] & 0xf3; // Ignore Int0 and Int1, or machine will loop forever waiting
else
return m_io_port[offset];
return 0xf3; // Ignore Int0 and Int1, or machine will loop forever waiting
}
READ8_MEMBER(splus_state::splus_duart_r)
@ -625,9 +621,6 @@ ADDRESS_MAP_START(splus_state::splus_iomap)
// SSxxxx Reel Chip
AM_RANGE(0x8000, 0x9fff) AM_READ(splus_m_reel_ram_r) AM_SHARE("reel_ram")
// Ports start here
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READ(splus_io_r) AM_WRITE(splus_io_w) AM_SHARE("io_port")
ADDRESS_MAP_END
/*************************
@ -689,6 +682,8 @@ MACHINE_CONFIG_START(splus_state::splus) // basic machine hardware
MCFG_CPU_ADD("maincpu", I80C32, CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(splus_map)
MCFG_CPU_IO_MAP(splus_iomap)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(splus_state, splus_p1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(splus_state, splus_p3_r))
// Fill NVRAM
MCFG_NVRAM_ADD_0FILL("cmosl")

9
src/mame/drivers/sslam.cpp
View File

@ -462,11 +462,6 @@ WRITE8_MEMBER(sslam_state::playmark_snd_control_w)
// (data & 0x40) -> always set
}
ADDRESS_MAP_START(sslam_state::sound_io_map)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(playmark_snd_control_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(playmark_snd_command_r, playmark_oki_w)
ADDRESS_MAP_END
/* Input Ports */
static INPUT_PORTS_START( sslam )
@ -734,7 +729,9 @@ MACHINE_CONFIG_START(sslam_state::powerbls)
MCFG_CPU_VBLANK_INT_DRIVER("screen", sslam_state, irq2_line_hold)
MCFG_CPU_ADD("audiocpu", I80C51, 12000000) /* 83C751 */
MCFG_CPU_IO_MAP(sound_io_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(sslam_state, playmark_snd_control_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(sslam_state, playmark_snd_command_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(sslam_state, playmark_oki_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

30
src/mame/drivers/superqix.cpp
View File

@ -1018,19 +1018,8 @@ ADDRESS_MAP_START(superqix_state::sqix_port_map)
//AM_RANGE(0xf970, 0xfa6f) AM_RAM // this is probably a portion of the remainder of the chips at 9L and 9M which isn't used or tested for graphics ram
ADDRESS_MAP_END
/* I8751 memory handlers */
ADDRESS_MAP_START(superqix_state::sqix_8031_mcu_io_map)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(bootleg_mcu_port1_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(bootleg_mcu_port3_r, bootleg_mcu_port3_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(superqix_state::sqix_mcu_io_map)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READ_PORT("SYSTEM")
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READ_PORT("DSW1")
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITE(mcu_port2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(mcu_port3_r, mcu_port3_w)
ADDRESS_MAP_START(superqix_state::sqix_8031_map)
AM_RANGE(0x0000, 0x0fff) AM_ROM AM_REGION("mcu", 0) // external program ROM
ADDRESS_MAP_END
@ -1409,7 +1398,11 @@ MACHINE_CONFIG_START(superqix_state::sqix)
MCFG_CPU_PERIODIC_INT_DRIVER(superqix_state, sqix_timer_irq, 4*60) /* ??? */
MCFG_CPU_ADD("mcu", I8751, XTAL(12'000'000)/2) /* i8751-88, 12 MHz / 2 (6 MHz), verified from pcb tracing */
MCFG_CPU_IO_MAP(sqix_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(IOPORT("SYSTEM"))
MCFG_MCS51_PORT_P1_IN_CB(IOPORT("DSW1"))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(superqix_state, mcu_port2_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(superqix_state, mcu_port3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(superqix_state, mcu_port3_w))
MCFG_MACHINE_START_OVERRIDE(superqix_state,superqix)
@ -1448,8 +1441,11 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(superqix_state::sqix_8031)
sqix(config);
MCFG_CPU_MODIFY("mcu") /* p8031ah, clock not verified */
MCFG_CPU_IO_MAP(sqix_8031_mcu_io_map)
MCFG_CPU_REPLACE("mcu", I8031, XTAL(12'000'000)/2) /* p8031ah, clock not verified */
MCFG_CPU_PROGRAM_MAP(sqix_8031_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(superqix_state, bootleg_mcu_port1_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(superqix_state, bootleg_mcu_port3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(superqix_state, bootleg_mcu_port3_w))
MACHINE_CONFIG_END
@ -1623,7 +1619,7 @@ ROM_START( sqixb1 ) // formerly 'sqixa'
ROM_LOAD( "sq01.97", 0x00000, 0x08000, CRC(0888b7de) SHA1(de3e4637436de185f43d2ad4186d4cfdcd4d33d9) ) // == b03__01.ef3
ROM_LOAD( "b03__02.h3", 0x10000, 0x10000, CRC(9c23cb64) SHA1(7e04cb18cabdc0031621162cbc228cd95875a022) ) // actual label is something different on the bootleg
ROM_REGION( 0x10000, "mcu", 0 ) /* I8031 code */
ROM_REGION( 0x01000, "mcu", 0 ) /* I8031 code */
ROM_LOAD( "sq07.ic108", 0x00000, 0x1000, CRC(d11411fb) SHA1(31183f433596c4d2503c01f6dc8d91024f2cf5de) ) // actual label is something different on the bootleg
ROM_REGION( 0x08000, "gfx1", 0 )

39
src/mame/drivers/system1.cpp
View File

@ -393,6 +393,8 @@ void system1_state::machine_start()
save_item(NAME(m_videomode_prev));
save_item(NAME(m_mcu_control));
save_item(NAME(m_nob_maincpu_latch));
save_item(NAME(m_nob_mcu_latch));
save_item(NAME(m_nob_mcu_status));
}
@ -657,15 +659,30 @@ TIMER_DEVICE_CALLBACK_MEMBER(system1_state::mcu_t0_callback)
*
*************************************/
READ8_MEMBER(system1_state::nob_mcu_latch_r)
{
return m_nob_mcu_latch;
}
WRITE8_MEMBER(system1_state::nob_mcu_latch_w)
{
m_nob_mcu_latch = data;
}
WRITE8_MEMBER(system1_state::nob_mcu_status_w)
{
m_nob_mcu_status = data;
}
WRITE8_MEMBER(system1_state::nob_mcu_control_p2_w)
{
/* bit 0 triggers a read from MCU port 0 */
if (((m_mcu_control ^ data) & 0x01) && !(data & 0x01))
*m_nob_mcu_latch = m_nob_maincpu_latch;
m_nob_mcu_latch = m_nob_maincpu_latch;
/* bit 1 triggers a write from MCU port 0 */
if (((m_mcu_control ^ data) & 0x02) && !(data & 0x02))
m_nob_maincpu_latch = *m_nob_mcu_latch;
m_nob_maincpu_latch = m_nob_mcu_latch;
/* bit 2 is toggled once near the end of an IRQ */
if (((m_mcu_control ^ data) & 0x04) && !(data & 0x04))
@ -697,7 +714,7 @@ WRITE8_MEMBER(system1_state::nob_maincpu_latch_w)
READ8_MEMBER(system1_state::nob_mcu_status_r)
{
return *m_nob_mcu_status;
return m_nob_mcu_status;
}
@ -833,17 +850,7 @@ ADDRESS_MAP_END
*************************************/
ADDRESS_MAP_START(system1_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0xffff) AM_READWRITE(mcu_io_r, mcu_io_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(mcu_control_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(system1_state::nob_mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_RAM AM_SHARE("nob_mcu_latch")
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITEONLY AM_SHARE("nob_mcu_status")
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITE(nob_mcu_control_p2_w)
ADDRESS_MAP_END
@ -2437,6 +2444,7 @@ MACHINE_CONFIG_START(system1_state::mcu)
MCFG_CPU_ADD("mcu", I8751, SOUND_CLOCK)
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(system1_state, mcu_control_w))
MCFG_CPU_VBLANK_INT_DRIVER("screen", system1_state, mcu_irq_assert)
MCFG_TIMER_DRIVER_ADD_PERIODIC("mcu_t0", system1_state, mcu_t0_callback, attotime::from_usec(2500))
@ -2458,7 +2466,10 @@ MACHINE_CONFIG_START(system1_state::nobm)
/* basic machine hardware */
MCFG_CPU_ADD("mcu", I8751, SOUND_CLOCK)
MCFG_CPU_IO_MAP(nob_mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(system1_state, nob_mcu_latch_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(system1_state, nob_mcu_latch_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(system1_state, nob_mcu_status_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(system1_state, nob_mcu_control_p2_w))
MACHINE_CONFIG_END

2
src/mame/drivers/tecnbras.cpp
View File

@ -57,7 +57,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(tecnbras_state::i80c31_io)
AM_RANGE(0x0100+DMD_OFFSET, 0x0145+DMD_OFFSET) AM_WRITE(set_x_position_w)
AM_RANGE(0x06B8, 0x06BC) AM_WRITE(print_column_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_NOP /*buzzer ?*/
ADDRESS_MAP_END
DRIVER_INIT_MEMBER( tecnbras_state, tecnbras )
@ -107,6 +106,7 @@ MACHINE_CONFIG_START(tecnbras_state::tecnbras)
MCFG_CPU_ADD("maincpu", I80C31, XTAL(12'000'000)) /* verified on pcb */
MCFG_CPU_PROGRAM_MAP(i80c31_prg)
MCFG_CPU_IO_MAP(i80c31_io)
MCFG_MCS51_PORT_P1_OUT_CB(NOOP) // buzzer ?
/* TODO: Add an I2C RTC (Phillips PCF8583P)
pin 6 (SCL): cpu T0/P3.4 (pin 14)

14
src/mame/drivers/thedeep.cpp
View File

@ -240,14 +240,6 @@ READ8_MEMBER(thedeep_state::p0_r)
return (ioport("COINS")->read() & 0xfe) | (coin_mux & 1);
}
ADDRESS_MAP_START(thedeep_state::mcu_io_map)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(MCS51_PORT_P0,MCS51_PORT_P0) AM_READ(p0_r)
AM_RANGE(MCS51_PORT_P1,MCS51_PORT_P1) AM_WRITE(p1_w)
AM_RANGE(MCS51_PORT_P2,MCS51_PORT_P2) AM_READWRITE(from_main_r,to_main_w)
AM_RANGE(MCS51_PORT_P3,MCS51_PORT_P3) AM_WRITE(p3_w)
ADDRESS_MAP_END
/***************************************************************************
@ -420,7 +412,11 @@ MACHINE_CONFIG_START(thedeep_state::thedeep)
/* MCU is a i8751 running at 8Mhz (8mhz xtal)*/
MCFG_CPU_ADD("mcu", I8751, XTAL(8'000'000))
MCFG_CPU_IO_MAP(mcu_io_map)
MCFG_MCS51_PORT_P0_IN_CB(READ8(thedeep_state, p0_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(thedeep_state, p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(thedeep_state, from_main_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(thedeep_state, to_main_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(thedeep_state, p3_w))
MCFG_CPU_VBLANK_INT_DRIVER("screen", thedeep_state, mcu_irq) // unknown source, but presumably vblank
MCFG_DEVICE_DISABLE()

91
src/mame/drivers/ti630.cpp
View File

@ -50,8 +50,9 @@ public:
, m_lcdc(*this, "hd44780")
{ }
DECLARE_WRITE8_MEMBER(ti630_io_w);
DECLARE_READ8_MEMBER(ti630_io_r);
DECLARE_WRITE8_MEMBER(i80c31_p1_w);
DECLARE_WRITE8_MEMBER(i80c31_p3_w);
DECLARE_READ8_MEMBER(i80c31_p1_r);
DECLARE_DRIVER_INIT(ti630);
DECLARE_PALETTE_INIT(ti630);
void ti630(machine_config &config);
@ -79,8 +80,6 @@ ADDRESS_MAP_START(ti630_state::i80c31_io)
AM_RANGE(0x1000,0x1000) /*AM_MIRROR(?)*/ AM_DEVWRITE("hd44780", hd44780_device, data_write)
AM_RANGE(0x2000,0x2000) /*AM_MIRROR(?)*/ AM_DEVREAD("hd44780", hd44780_device, control_read)
AM_RANGE(0x8000,0xffff) AM_RAM /*TODO: verify the ammont of RAM and the correct address range to which it is mapped. This is just a first reasonable guess that apparently yields good results in the emulation */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(ti630_io_r, ti630_io_w)
ADDRESS_MAP_END
void ti630_state::machine_start()
@ -91,76 +90,25 @@ void ti630_state::machine_reset()
{
}
READ8_MEMBER(ti630_state::ti630_io_r)
READ8_MEMBER(ti630_state::i80c31_p1_r)
{
switch (offset)
{
case 0x01:
{
uint8_t value = 0;
#if LOG_IO_PORTS
printf("P1 read value:%02X\n", value);
#endif
return value;
}
default:
#if LOG_IO_PORTS
printf("Unhandled I/O Read at offset 0x%02X (return 0)\n", offset);
#endif
return 0;
}
uint8_t value = 0;
if (LOG_IO_PORTS)
logerror("P1 read value:%02X\n", value);
return value;
}
WRITE8_MEMBER(ti630_state::ti630_io_w)
WRITE8_MEMBER(ti630_state::i80c31_p1_w)
{
static uint8_t p0=0, p1=0, p2=0, p3=0;
switch (offset)
{
case 0x00:
{
if (data != p0)
{
p0=data;
#if LOG_IO_PORTS
printf("Write to P0: %02X\n", data);
#endif
}
break;
}
case 0x01:
{
if (data != p1)
{
p1=data;
#if LOG_IO_PORTS
printf("Write to P1: %02X\n", data);
#endif
}
break;
}
case 0x02:
{
if (data != p2)
{
p2=data;
#if LOG_IO_PORTS
printf("Write to P2: %02X\n", data);
#endif
}
break;
}
case 0x03:
{
if (data != p3)
{
p3=data;
#if LOG_IO_PORTS
printf("Write to P3: %02X\n", data);
#endif
}
break;
}
}
if (LOG_IO_PORTS)
logerror("Write to P1: %02X\n", data);
}
WRITE8_MEMBER(ti630_state::i80c31_p3_w)
{
if (LOG_IO_PORTS)
logerror("Write to P3: %02X\n", data);
}
PALETTE_INIT_MEMBER(ti630_state, ti630)
@ -189,6 +137,9 @@ MACHINE_CONFIG_START(ti630_state::ti630)
MCFG_CPU_ADD("maincpu", I80C31, XTAL(10'000'000))
MCFG_CPU_PROGRAM_MAP(i80c31_prg)
MCFG_CPU_IO_MAP(i80c31_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(ti630_state, i80c31_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(ti630_state, i80c31_p1_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(ti630_state, i80c31_p3_w))
/* video hardware */
MCFG_SCREEN_ADD("screen", LCD)

68
src/mame/drivers/tumbleb.cpp
View File

@ -811,59 +811,28 @@ ADDRESS_MAP_START(tumbleb_state::jumpkids_sound_map)
ADDRESS_MAP_END
READ8_MEMBER(tumbleb_state::prot_io_r)
{
// never read?
return 0x00;
}
/* Semicom AT89C52 MCU */
// probably not endian safe
WRITE8_MEMBER(tumbleb_state::prot_io_w)
WRITE8_MEMBER(tumbleb_state::prot_p0_w)
{
switch (offset)
{
case 0x00:
{
uint16_t word = m_mainram[(m_protbase/2) + m_semicom_prot_offset];
word = (word & 0xff00) | (data << 0);
m_mainram[(m_protbase/2) + m_semicom_prot_offset] = word;
break;
}
case 0x01:
{
uint16_t word = m_mainram[(m_protbase/2) + m_semicom_prot_offset];
word = (word & 0x00ff) | (data << 8);
m_mainram[(m_protbase/2) + m_semicom_prot_offset] = word;
break;
}
case 0x02: // offset
{
m_semicom_prot_offset = data;
break;
}
case 0x03: // ??
{
//logerror("offset %02x data %02x\n",offset,data);
break;
}
}
uint16_t word = m_mainram[(m_protbase/2) + m_semicom_prot_offset];
word = (word & 0xff00) | (data << 0);
m_mainram[(m_protbase/2) + m_semicom_prot_offset] = word;
}
// probably not endian safe
WRITE8_MEMBER(tumbleb_state::prot_p1_w)
{
uint16_t word = m_mainram[(m_protbase/2) + m_semicom_prot_offset];
word = (word & 0x00ff) | (data << 8);
m_mainram[(m_protbase/2) + m_semicom_prot_offset] = word;
}
/* Semicom AT89C52 MCU */
ADDRESS_MAP_START(tumbleb_state::protection_map)
AM_RANGE(0x0000, 0x1fff) AM_ROM
ADDRESS_MAP_END
ADDRESS_MAP_START(tumbleb_state::protection_iomap)
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P3) AM_READWRITE(prot_io_r,prot_io_w)
ADDRESS_MAP_END
WRITE8_MEMBER(tumbleb_state::prot_p2_w)
{
m_semicom_prot_offset = data;
}
/******************************************************************************/
@ -2287,8 +2256,9 @@ MACHINE_CONFIG_START(tumbleb_state::cookbib_mcu)
/* basic machine hardware */
MCFG_CPU_ADD("protection", I8052, 16000000) // AT89C52
MCFG_CPU_PROGRAM_MAP(protection_map)
MCFG_CPU_IO_MAP(protection_iomap)
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(tumbleb_state, prot_p0_w))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(tumbleb_state, prot_p1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(tumbleb_state, prot_p2_w))
/* video hardware */
MCFG_SCREEN_MODIFY("screen")

18
src/mame/drivers/videopkr.cpp
View File

@ -993,8 +993,6 @@ ADDRESS_MAP_START(videopkr_state::i8751_io_port)
AM_RANGE(0xa000, 0xbfff) AM_RAM // video RAM?
AM_RANGE(0xc000, 0xc003) AM_DEVREADWRITE("ppi", i8255_device, read, write)
AM_RANGE(0xf000, 0xf000) AM_WRITEONLY // ???
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READONLY // ???
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_NOP // ???
ADDRESS_MAP_END
ADDRESS_MAP_START(videopkr_state::i8039_sound_mem)
@ -1012,11 +1010,6 @@ ADDRESS_MAP_END
ADDRESS_MAP_START(videopkr_state::i8051_sound_port)
AM_RANGE(0x0000, 0x1ff) AM_RAM
/* ports */
AM_RANGE(MCS51_PORT_P0, MCS51_PORT_P0) AM_READWRITE(baby_sound_p0_r, baby_sound_p0_w)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(baby_sound_p1_r, baby_sound_p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_READ(baby_sound_p2_r) AM_WRITE(baby_sound_p2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_READWRITE(baby_sound_p3_r, baby_sound_p3_w)
ADDRESS_MAP_END
@ -1342,6 +1335,14 @@ MACHINE_CONFIG_START(videopkr_state::babypkr)
MCFG_CPU_REPLACE("soundcpu", I8031, CPU_CLOCK )
MCFG_CPU_PROGRAM_MAP(i8051_sound_mem)
MCFG_CPU_IO_MAP(i8051_sound_port)
MCFG_MCS51_PORT_P0_IN_CB(READ8(videopkr_state, baby_sound_p0_r))
MCFG_MCS51_PORT_P0_OUT_CB(WRITE8(videopkr_state, baby_sound_p0_w))
MCFG_MCS51_PORT_P1_IN_CB(READ8(videopkr_state, baby_sound_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(videopkr_state, baby_sound_p1_w))
MCFG_MCS51_PORT_P2_IN_CB(READ8(videopkr_state, baby_sound_p2_r))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(videopkr_state, baby_sound_p2_w))
MCFG_MCS51_PORT_P3_IN_CB(READ8(videopkr_state, baby_sound_p3_r))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(videopkr_state, baby_sound_p3_w))
/* video hardware */
MCFG_SCREEN_MODIFY("screen")
@ -1373,6 +1374,9 @@ MACHINE_CONFIG_START(videopkr_state::bpoker)
MCFG_CPU_REPLACE("maincpu", I8751, XTAL(6'000'000))
MCFG_CPU_PROGRAM_MAP(i8751_map)
MCFG_CPU_IO_MAP(i8751_io_port)
MCFG_MCS51_PORT_P0_IN_CB(NOOP) // ???
MCFG_MCS51_PORT_P1_IN_CB(NOOP) // ???
MCFG_MCS51_PORT_P1_OUT_CB(NOOP) // ???
MCFG_DEVICE_ADD("ppi", I8255A, 0)
//MCFG_I8255_OUT_PORTA_CB()

2
src/mame/drivers/vt220.cpp
View File

@ -74,7 +74,6 @@ ADDRESS_MAP_START(vt220_state::vt220_io)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x2000, 0x2fff) AM_MIRROR(0xc000) AM_RAM
AM_RANGE(0x3800, 0x380f) AM_MIRROR(0xc7f0) AM_DEVREADWRITE("duart", scn2681_device, read, write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READNOP
ADDRESS_MAP_END
ADDRESS_MAP_START(vt220_state::vt220a_io)
@ -105,6 +104,7 @@ MACHINE_CONFIG_START(vt220_state::vt220)
MCFG_CPU_ADD("maincpu", I8051, XTAL(11'059'200)) // from schematic for earlier version
MCFG_CPU_PROGRAM_MAP(vt220_mem)
MCFG_CPU_IO_MAP(vt220_io)
MCFG_MCS51_PORT_P1_IN_CB(NOOP) // ???
MCFG_DEVICE_ADD("duart", SCN2681, XTAL(3'686'400))
MCFG_MC68681_IRQ_CALLBACK(INPUTLINE("maincpu", MCS51_INT1_LINE))

2
src/mame/includes/blktiger.h
View File

@ -78,8 +78,6 @@ public:
void blktigerbl(machine_config &config);
void blktiger_io_map(address_map &map);
void blktiger_map(address_map &map);
void blktiger_mcu_io_map(address_map &map);
void blktiger_mcu_map(address_map &map);
void blktiger_sound_map(address_map &map);
void blktigerbl_io_map(address_map &map);
};

1
src/mame/includes/cdi.h
View File

@ -135,7 +135,6 @@ public:
void cdimono2_mem(address_map &map);
void cdimono2_servo_mem(address_map &map);
void cdimono2_slave_mem(address_map &map);
void mcu_io_map(address_map &map);
};
/*----------- debug defines -----------*/

8
src/mame/includes/dec0.h
View File

@ -76,8 +76,11 @@ public:
DECLARE_READ16_MEMBER(midres_controls_r);
DECLARE_READ8_MEMBER(hippodrm_prot_r);
DECLARE_WRITE8_MEMBER(hippodrm_prot_w);
DECLARE_READ8_MEMBER(dec0_mcu_port_r);
DECLARE_WRITE8_MEMBER(dec0_mcu_port_w);
DECLARE_READ8_MEMBER(dec0_mcu_port0_r);
DECLARE_WRITE8_MEMBER(dec0_mcu_port0_w);
DECLARE_WRITE8_MEMBER(dec0_mcu_port1_w);
DECLARE_WRITE8_MEMBER(dec0_mcu_port2_w);
DECLARE_WRITE8_MEMBER(dec0_mcu_port3_w);
DECLARE_READ16_MEMBER(hippodrm_68000_share_r);
DECLARE_WRITE16_MEMBER(hippodrm_68000_share_w);
DECLARE_WRITE16_MEMBER(sprite_mirror_w);
@ -135,7 +138,6 @@ public:
void dec0_map(address_map &map);
void dec0_s_map(address_map &map);
void hippodrm_sub_map(address_map &map);
void mcu_io_map(address_map &map);
void midres_map(address_map &map);
void midres_s_map(address_map &map);
void midresb_map(address_map &map);

10
src/mame/includes/dec8.h
View File

@ -114,9 +114,11 @@ public:
DECLARE_WRITE8_MEMBER(oscar_int_w);
DECLARE_WRITE8_MEMBER(shackled_int_w);
DECLARE_WRITE8_MEMBER(flip_screen_w);
DECLARE_READ8_MEMBER(dec8_mcu_from_main_r);
DECLARE_WRITE8_MEMBER(dec8_mcu_to_main_w);
DECLARE_READ8_MEMBER(srdarwin_mcu_from_main_r);
DECLARE_READ8_MEMBER(i8751_port0_r);
DECLARE_WRITE8_MEMBER(i8751_port0_w);
DECLARE_READ8_MEMBER(i8751_port1_r);
DECLARE_WRITE8_MEMBER(i8751_port1_w);
DECLARE_WRITE8_MEMBER(gondo_mcu_to_main_w);
DECLARE_WRITE8_MEMBER(srdarwin_mcu_to_main_w);
DECLARE_WRITE8_MEMBER(dec8_bg_data_w);
DECLARE_READ8_MEMBER(dec8_bg_data_r);
@ -181,7 +183,6 @@ public:
void csilver_map(address_map &map);
void csilver_s_map(address_map &map);
void csilver_sub_map(address_map &map);
void dec8_mcu_io_map(address_map &map);
void dec8_s_map(address_map &map);
void garyoret_map(address_map &map);
void gondo_map(address_map &map);
@ -194,7 +195,6 @@ public:
void shackled_map(address_map &map);
void shackled_sub_map(address_map &map);
void srdarwin_map(address_map &map);
void srdarwin_mcu_io_map(address_map &map);
void ym3526_s_map(address_map &map);
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;

1
src/mame/includes/djboy.h
View File

@ -100,5 +100,4 @@ public:
void cpu1_port_am(address_map &map);
void cpu2_am(address_map &map);
void cpu2_port_am(address_map &map);
void djboy_mcu_io_map(address_map &map);
};

1
src/mame/includes/karnov.h
View File

@ -84,7 +84,6 @@ public:
void wndrplnt(machine_config &config);
void karnovjbl(machine_config &config);
void base_sound_map(address_map &map);
void chelnovjbl_mcu_io_map(address_map &map);
void chelnovjbl_mcu_map(address_map &map);
void karnov_map(address_map &map);
void karnov_sound_map(address_map &map);

4
src/mame/includes/m72.h
View File

@ -119,8 +119,8 @@ public:
DECLARE_READ8_MEMBER(mcu_sample_r);
DECLARE_WRITE8_MEMBER(mcu_ack_w);
DECLARE_READ8_MEMBER(mcu_snd_r);
DECLARE_READ8_MEMBER(mcu_port_r);
DECLARE_WRITE8_MEMBER(mcu_port_w);
DECLARE_WRITE8_MEMBER(mcu_port1_w);
DECLARE_WRITE8_MEMBER(mcu_port3_w);
DECLARE_WRITE8_MEMBER(mcu_low_w);
DECLARE_WRITE8_MEMBER(mcu_high_w);
DECLARE_READ8_MEMBER(snd_cpu_sample_r);

1
src/mame/includes/maygay1b.h
View File

@ -153,5 +153,4 @@ public:
void maygay_m1_empire(machine_config &config);
void m1_memmap(address_map &map);
void m1_nec_memmap(address_map &map);
void maygay_mcu_io(address_map &map);
};

6
src/mame/includes/micro3d.h
View File

@ -154,8 +154,10 @@ public:
DECLARE_CUSTOM_INPUT_MEMBER(botss_hwchk_r);
DECLARE_WRITE8_MEMBER(micro3d_snd_dac_a);
DECLARE_WRITE8_MEMBER(micro3d_snd_dac_b);
DECLARE_WRITE8_MEMBER(micro3d_sound_io_w);
DECLARE_READ8_MEMBER(micro3d_sound_io_r);
DECLARE_WRITE8_MEMBER(micro3d_sound_p1_w);
DECLARE_WRITE8_MEMBER(micro3d_sound_p3_w);
DECLARE_READ8_MEMBER(micro3d_sound_p1_r);
DECLARE_READ8_MEMBER(micro3d_sound_p3_r);
DECLARE_DRIVER_INIT(micro3d);
DECLARE_DRIVER_INIT(botss);
virtual void machine_reset() override;

6
src/mame/includes/rmnimbus.h
View File

@ -128,8 +128,10 @@ public:
DECLARE_WRITE8_MEMBER(nimbus_pc8031_w);
DECLARE_READ8_MEMBER(nimbus_pc8031_iou_r);
DECLARE_WRITE8_MEMBER(nimbus_pc8031_iou_w);
DECLARE_READ8_MEMBER(nimbus_pc8031_port_r);
DECLARE_WRITE8_MEMBER(nimbus_pc8031_port_w);
DECLARE_READ8_MEMBER(nimbus_pc8031_port1_r);
DECLARE_WRITE8_MEMBER(nimbus_pc8031_port1_w);
DECLARE_READ8_MEMBER(nimbus_pc8031_port3_r);
DECLARE_WRITE8_MEMBER(nimbus_pc8031_port3_w);
DECLARE_READ8_MEMBER(nimbus_iou_r);
DECLARE_WRITE8_MEMBER(nimbus_iou_w);
DECLARE_WRITE8_MEMBER(nimbus_sound_ay8910_porta_w);

7
src/mame/includes/snowbros.h
View File

@ -42,8 +42,9 @@ public:
DECLARE_WRITE16_MEMBER(snowbros_irq4_ack_w);
DECLARE_WRITE16_MEMBER(snowbros_irq3_ack_w);
DECLARE_WRITE16_MEMBER(snowbros_irq2_ack_w);
DECLARE_READ8_MEMBER(prot_io_r);
DECLARE_WRITE8_MEMBER(prot_io_w);
DECLARE_WRITE8_MEMBER(prot_p0_w);
DECLARE_WRITE8_MEMBER(prot_p1_w);
DECLARE_WRITE8_MEMBER(prot_p2_w);
DECLARE_READ16_MEMBER(sb3_sound_r);
DECLARE_READ16_MEMBER(_4in1_02_read);
DECLARE_READ16_MEMBER(_3in1_read);
@ -93,8 +94,6 @@ public:
void honeydol_sound_map(address_map &map);
void hyperpac_map(address_map &map);
void hyperpac_sound_map(address_map &map);
void protection_iomap(address_map &map);
void protection_map(address_map &map);
void snowbros3_map(address_map &map);
void snowbros_map(address_map &map);
void sound_io_map(address_map &map);

1
src/mame/includes/sslam.h
View File

@ -77,6 +77,5 @@ public:
void sslam(machine_config &config);
void powerbls(machine_config &config);
void powerbls_map(address_map &map);
void sound_io_map(address_map &map);
void sslam_program_map(address_map &map);
};

3
src/mame/includes/superqix.h
View File

@ -105,9 +105,8 @@ public:
void sqix(machine_config &config);
void sqix_8031(machine_config &config);
void sqix_nomcu(machine_config &config);
void sqix_8031_mcu_io_map(address_map &map);
void sqix_mcu_io_map(address_map &map);
void sqix_port_map(address_map &map);
void sqix_8031_map(address_map &map);
protected:
virtual void machine_init_common() override;

12
src/mame/includes/system1.h
View File

@ -16,8 +16,6 @@ public:
m_ppi8255(*this, "ppi8255"),
m_ram(*this, "ram"),
m_spriteram(*this, "spriteram"),
m_nob_mcu_latch(*this, "nob_mcu_latch"),
m_nob_mcu_status(*this, "nob_mcu_status"),
m_paletteram(*this, "palette"),
m_videomode_custom(nullptr),
m_maincpu(*this, "maincpu"),
@ -39,8 +37,6 @@ public:
optional_device<i8255_device> m_ppi8255;
required_shared_ptr<uint8_t> m_ram;
required_shared_ptr<uint8_t> m_spriteram;
optional_shared_ptr<uint8_t> m_nob_mcu_latch;
optional_shared_ptr<uint8_t> m_nob_mcu_status;
required_shared_ptr<uint8_t> m_paletteram;
std::unique_ptr<uint8_t[]> m_videoram;
@ -50,6 +46,8 @@ public:
uint8_t m_videomode_prev;
uint8_t m_mcu_control;
uint8_t m_nob_maincpu_latch;
uint8_t m_nob_mcu_latch;
uint8_t m_nob_mcu_status;
int m_nobb_inport23_step;
std::unique_ptr<uint8_t[]> m_mix_collide;
uint8_t m_mix_collide_summary;
@ -65,8 +63,11 @@ public:
DECLARE_READ8_MEMBER(sound_data_r);
DECLARE_WRITE8_MEMBER(soundport_w);
DECLARE_WRITE8_MEMBER(mcu_control_w);
DECLARE_WRITE8_MEMBER(mcu_io_w);
DECLARE_READ8_MEMBER(mcu_io_r);
DECLARE_WRITE8_MEMBER(mcu_io_w);
DECLARE_READ8_MEMBER(nob_mcu_latch_r);
DECLARE_WRITE8_MEMBER(nob_mcu_latch_w);
DECLARE_WRITE8_MEMBER(nob_mcu_status_w);
DECLARE_WRITE8_MEMBER(nob_mcu_control_p2_w);
DECLARE_READ8_MEMBER(nob_maincpu_latch_r);
DECLARE_WRITE8_MEMBER(nob_maincpu_latch_w);
@ -192,7 +193,6 @@ public:
void banked_decrypted_opcodes_map(address_map &map);
void decrypted_opcodes_map(address_map &map);
void mcu_io_map(address_map &map);
void nob_mcu_io_map(address_map &map);
void nobo_map(address_map &map);
void sound_map(address_map &map);
void system1_map(address_map &map);

1
src/mame/includes/thedeep.h
View File

@ -77,5 +77,4 @@ public:
void thedeep(machine_config &config);
void audio_map(address_map &map);
void main_map(address_map &map);
void mcu_io_map(address_map &map);
};

7
src/mame/includes/tumbleb.h
View File

@ -63,8 +63,9 @@ public:
DECLARE_WRITE16_MEMBER(semicom_soundcmd_w);
DECLARE_WRITE8_MEMBER(oki_sound_bank_w);
DECLARE_WRITE8_MEMBER(jumpkids_oki_bank_w);
DECLARE_READ8_MEMBER(prot_io_r);
DECLARE_WRITE8_MEMBER(prot_io_w);
DECLARE_WRITE8_MEMBER(prot_p0_w);
DECLARE_WRITE8_MEMBER(prot_p1_w);
DECLARE_WRITE8_MEMBER(prot_p2_w);
DECLARE_READ16_MEMBER(bcstory_1a0_read);
DECLARE_WRITE16_MEMBER(bcstory_tilebank_w);
DECLARE_WRITE16_MEMBER(chokchok_tilebank_w);
@ -152,8 +153,6 @@ public:
void jumpkids_main_map(address_map &map);
void jumpkids_sound_map(address_map &map);
void pangpang_main_map(address_map &map);
void protection_iomap(address_map &map);
void protection_map(address_map &map);
void semicom_sound_map(address_map &map);
void suprtrio_main_map(address_map &map);
void suprtrio_sound_map(address_map &map);

51
src/mame/machine/dec0.cpp
View File

@ -150,37 +150,46 @@ WRITE16_MEMBER(dec0_state::hippodrm_68000_share_w)
*/
READ8_MEMBER(dec0_state::dec0_mcu_port_r)
READ8_MEMBER(dec0_state::dec0_mcu_port0_r)
{
uint8_t result = 0xff;
// P0 connected to latches
if (offset == 0)
{
if (!BIT(m_i8751_ports[2], 4))
result &= m_i8751_command >> 8;
if (!BIT(m_i8751_ports[2], 5))
result &= m_i8751_command & 0x00ff;
}
if (!BIT(m_i8751_ports[2], 4))
result &= m_i8751_command >> 8;
if (!BIT(m_i8751_ports[2], 5))
result &= m_i8751_command & 0x00ff;
return result;
}
WRITE8_MEMBER(dec0_state::dec0_mcu_port_w)
WRITE8_MEMBER(dec0_state::dec0_mcu_port0_w)
{
if (offset == 2)
{
if (!BIT(data, 2) && BIT(m_i8751_ports[2], 2))
m_maincpu->set_input_line(M68K_IRQ_5, HOLD_LINE);
if (!BIT(data, 3))
m_mcu->set_input_line(MCS51_INT1_LINE, CLEAR_LINE);
if (BIT(data, 6) && !BIT(m_i8751_ports[2], 6))
m_i8751_return = (m_i8751_return & 0xff00) | m_i8751_ports[0];
if (BIT(data, 7) && !BIT(m_i8751_ports[2], 7))
m_i8751_return = (m_i8751_return & 0x00ff) | (m_i8751_ports[0] << 8);
}
m_i8751_ports[0] = data;
}
m_i8751_ports[offset] = data;
WRITE8_MEMBER(dec0_state::dec0_mcu_port1_w)
{
m_i8751_ports[1] = data;
}
WRITE8_MEMBER(dec0_state::dec0_mcu_port2_w)
{
if (!BIT(data, 2) && BIT(m_i8751_ports[2], 2))
m_maincpu->set_input_line(M68K_IRQ_5, HOLD_LINE);
if (!BIT(data, 3))
m_mcu->set_input_line(MCS51_INT1_LINE, CLEAR_LINE);
if (BIT(data, 6) && !BIT(m_i8751_ports[2], 6))
m_i8751_return = (m_i8751_return & 0xff00) | m_i8751_ports[0];
if (BIT(data, 7) && !BIT(m_i8751_ports[2], 7))
m_i8751_return = (m_i8751_return & 0x00ff) | (m_i8751_ports[0] << 8);
m_i8751_ports[2] = data;
}
WRITE8_MEMBER(dec0_state::dec0_mcu_port3_w)
{
m_i8751_ports[3] = data;
}
void dec0_state::baddudes_i8751_write(int data)

43
src/mame/machine/micro3d.cpp
View File

@ -473,35 +473,30 @@ WRITE8_MEMBER(micro3d_state::micro3d_snd_dac_b)
/* TODO: This controls upd7759 volume */
}
WRITE8_MEMBER(micro3d_state::micro3d_sound_io_w)
WRITE8_MEMBER(micro3d_state::micro3d_sound_p1_w)
{
m_sound_port_latch[offset] = data;
m_sound_port_latch[1] = data;
switch (offset)
{
case 0x01:
{
micro3d_sound_device *noise = (data & 4) ? m_noise_2 : m_noise_1;
noise->noise_sh_w(data);
break;
}
case 0x03:
{
m_upd7759->set_bank_base((data & 0x4) ? 0x20000 : 0);
m_upd7759->reset_w((data & 0x10) ? 0 : 1);
break;
}
}
micro3d_sound_device *noise = (data & 4) ? m_noise_2 : m_noise_1;
noise->noise_sh_w(data);
}
READ8_MEMBER(micro3d_state::micro3d_sound_io_r)
WRITE8_MEMBER(micro3d_state::micro3d_sound_p3_w)
{
switch (offset)
{
case 0x01: return (m_sound_port_latch[offset] & 0x7f) | m_sound_sw->read();
case 0x03: return (m_sound_port_latch[offset] & 0xf7) | (m_upd7759->busy_r() ? 0x08 : 0);
default: return 0;
}
m_sound_port_latch[3] = data;
m_upd7759->set_bank_base((data & 0x4) ? 0x20000 : 0);
m_upd7759->reset_w((data & 0x10) ? 0 : 1);
}
READ8_MEMBER(micro3d_state::micro3d_sound_p1_r)
{
return (m_sound_port_latch[1] & 0x7f) | m_sound_sw->read();
}
READ8_MEMBER(micro3d_state::micro3d_sound_p3_r)
{
return (m_sound_port_latch[3] & 0xf7) | (m_upd7759->busy_r() ? 0x08 : 0);
}
WRITE8_MEMBER(micro3d_state::micro3d_upd7759_w)

62
src/mame/machine/rmnimbus.cpp
View File

@ -1384,52 +1384,58 @@ WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_iou_w)
}
}
READ8_MEMBER(rmnimbus_state::nimbus_pc8031_port_r)
READ8_MEMBER(rmnimbus_state::nimbus_pc8031_port1_r)
{
int pc=m_iocpu->pc();
uint8_t result = (m_eeprom_bits & ~4) | (m_eeprom->do_read() << 2);
if(LOG_PC8031_PORT)
logerror("8031: PCPORTR %04X read of P1 returns %02X\n",pc,result);
return result;
}
READ8_MEMBER(rmnimbus_state::nimbus_pc8031_port3_r)
{
int pc=m_iocpu->pc();
uint8_t result = 0;
if(LOG_PC8031_PORT)
logerror("8031: PCPORTR %04X read of %04X returns %02X\n",pc,offset,result);
switch(offset)
{
case 0x01:
result = (m_eeprom_bits & ~4) | (m_eeprom->do_read() << 2);
break;
}
logerror("8031: PCPORTR %04X read of P3 returns %02X\n",pc,result);
return result;
}
WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_port_w)
WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_port1_w)
{
int pc=m_iocpu->pc();
switch (offset)
{
case 0x01:
m_eeprom->cs_write((data & 8) ? 1 : 0);
m_eeprom->cs_write((data & 8) ? 1 : 0);
if(!(data & 8))
m_eeprom_state = 0;
else if(!(data & 2) || (m_eeprom_state == 2))
m_eeprom_state = 2;
else if((data & 8) && (!(m_eeprom_bits & 8)))
m_eeprom_state = 1;
else if((!(data & 1)) && (m_eeprom_bits & 1) && (m_eeprom_state == 1))
m_eeprom_state = 2; //wait until 1 clk after cs rises to set di else it's seen as a start bit
if(!(data & 8))
m_eeprom_state = 0;
else if(!(data & 2) || (m_eeprom_state == 2))
m_eeprom_state = 2;
else if((data & 8) && (!(m_eeprom_bits & 8)))
m_eeprom_state = 1;
else if((!(data & 1)) && (m_eeprom_bits & 1) && (m_eeprom_state == 1))
m_eeprom_state = 2; //wait until 1 clk after cs rises to set di else it's seen as a start bit
m_eeprom->di_write(((data & 2) && (m_eeprom_state == 2)) ? 1 : 0);
m_eeprom->clk_write((data & 1) ? 1 : 0);
m_eeprom_bits = data;
break;
}
m_eeprom->di_write(((data & 2) && (m_eeprom_state == 2)) ? 1 : 0);
m_eeprom->clk_write((data & 1) ? 1 : 0);
m_eeprom_bits = data;
if(LOG_PC8031_PORT)
logerror("8031 PCPORTW %04X write of %02X to %04X\n",pc,data,offset);
logerror("8031 PCPORTW %04X write of %02X to P1\n",pc,data);
}
WRITE8_MEMBER(rmnimbus_state::nimbus_pc8031_port3_w)
{
int pc=m_iocpu->pc();
if(LOG_PC8031_PORT)
logerror("8031 PCPORTW %04X write of %02X to P3\n",pc,data);
}
/* IO Unit */

7
src/mame/machine/wangpckb.cpp
View File

@ -102,9 +102,6 @@ ADDRESS_MAP_START(wangpc_keyboard_device::wangpc_keyboard_io)
//AM_RANGE(0x0000, 0xfeff) AM_READNOP
AM_RANGE(0x47, 0x58) AM_MIRROR(0xff00) AM_READNOP
AM_RANGE(0x00, 0x00) AM_MIRROR(0xff00) AM_DEVWRITE(SN76496_TAG, sn76496_device, write)
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_READWRITE(kb_p1_r, kb_p1_w)
AM_RANGE(MCS51_PORT_P2, MCS51_PORT_P2) AM_WRITE(kb_p2_w)
AM_RANGE(MCS51_PORT_P3, MCS51_PORT_P3) AM_WRITE(kb_p3_w)
ADDRESS_MAP_END
@ -115,6 +112,10 @@ ADDRESS_MAP_END
MACHINE_CONFIG_START(wangpc_keyboard_device::device_add_mconfig)
MCFG_CPU_ADD(I8051_TAG, I8051, XTAL(4'000'000))
MCFG_CPU_IO_MAP(wangpc_keyboard_io)
MCFG_MCS51_PORT_P1_IN_CB(READ8(wangpc_keyboard_device, kb_p1_r))
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(wangpc_keyboard_device, kb_p1_w))
MCFG_MCS51_PORT_P2_OUT_CB(WRITE8(wangpc_keyboard_device, kb_p2_w))
MCFG_MCS51_PORT_P3_OUT_CB(WRITE8(wangpc_keyboard_device, kb_p3_w))
MCFG_MCS51_SERIAL_TX_CB(WRITE8(wangpc_keyboard_device, mcs51_tx_callback))
MCFG_MCS51_SERIAL_RX_CB(READ8(wangpc_keyboard_device, mcs51_rx_callback))

3
src/mame/video/pcd.cpp
View File

@ -133,7 +133,6 @@ ADDRESS_MAP_START(pcx_video_device::pcx_vid_io)
AM_RANGE(0xa000, 0xa001) AM_READWRITE(vram_latch_r, vram_latch_w)
AM_RANGE(0xa002, 0xa003) AM_READWRITE(term_mcu_r, term_mcu_w)
AM_RANGE(0xc000, 0xc7ff) AM_RAM
AM_RANGE(MCS51_PORT_P1, MCS51_PORT_P1) AM_WRITE(p1_w)
ADDRESS_MAP_END
ADDRESS_MAP_START(pcx_video_device::pcx_vram)
@ -144,7 +143,7 @@ MACHINE_CONFIG_START(pcx_video_device::device_add_mconfig)
MCFG_CPU_ADD("graphics", I8031, XTAL(24'000'000)/2)
MCFG_CPU_PROGRAM_MAP(pcx_vid_map)
MCFG_CPU_IO_MAP(pcx_vid_io)
MCFG_MCS51_PORT_P1_OUT_CB(WRITE8(pcx_video_device, p1_w))
MCFG_MCS51_SERIAL_TX_CB(WRITE8(pcx_video_device, tx_callback))
MCFG_MCS51_SERIAL_RX_CB(READ8(pcx_video_device, rx_callback))