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https://github.com/holub/mame
synced 2025-06-03 19:36:26 +03:00
sharcdrc: more fixes, more ops (nw)
This commit is contained in:
Ville Linde
parent
9f9afbe9db
commit
5e64d45ecb
@ -616,7 +616,7 @@ private:
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void static_generate_mode1_ops();
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void load_fast_iregs(drcuml_block *block);
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void save_fast_iregs(drcuml_block *block);
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void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot);
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void generate_update_cycles(drcuml_block *block, compiler_state *compiler, uml::parameter param, int allow_exception);
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int generate_opcode(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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void generate_unimplemented_compute(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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@ -1183,7 +1183,7 @@ void adsp21062_device::compile_block(offs_t pc)
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/* iterate over instructions in the sequence and compile them */
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for (curdesc = seqhead; curdesc != seqlast->next(); curdesc = curdesc->next())
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generate_sequence_instruction(block, &compiler, curdesc);
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generate_sequence_instruction(block, &compiler, curdesc, false);
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/* if we need to return to the start, do it */
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if (seqlast->flags & OPFLAG_RETURN_TO_START)
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@ -1335,7 +1335,7 @@ void adsp21062_device::static_generate_out_of_cycles()
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}
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void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, bool last_delayslot)
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{
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/* add an entry for the log */
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// if (m_drcuml->logging() && !(desc->flags & OPFLAG_VIRTUAL_NOOP))
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@ -1387,6 +1387,11 @@ void adsp21062_device::generate_sequence_instruction(drcuml_block *block, compil
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if (compiler->mode1_delay.counter > 0)
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{
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compiler->mode1_delay.counter--;
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// delayed operation in the last delay slot needs to be done before the branch is taken
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if (last_delayslot)
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compiler->mode1_delay.counter = 0;
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if (compiler->mode1_delay.counter <= 0)
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{
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switch (compiler->mode1_delay.mode)
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@ -1696,7 +1701,48 @@ void adsp21062_device::generate_clear_mode1_imm(drcuml_block *block, compiler_st
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void adsp21062_device::generate_update_circular_buffer(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, int g, int i)
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{
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// TODO
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if (g)
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{
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// PM
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code_label end = compiler->labelnum++;
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code_label label2 = compiler->labelnum++;
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UML_CMP(block, PM_L(i), 0);
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UML_JMPc(block, COND_E, end);
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UML_ADD(block, I0, PM_B(i), PM_L(i));
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UML_CMP(block, PM_I(i), I0);
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UML_JMPc(block, COND_LE, label2);
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UML_SUB(block, PM_I(i), PM_I(i), PM_L(i));
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UML_JMP(block, end);
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UML_LABEL(block, label2);
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UML_CMP(block, PM_I(i), PM_B(i));
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UML_JMPc(block, COND_G, end);
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UML_ADD(block, PM_I(i), PM_I(i), PM_L(i));
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UML_LABEL(block, end);
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}
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else
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{
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// DM
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code_label end = compiler->labelnum++;
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code_label label2 = compiler->labelnum++;
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UML_CMP(block, DM_L(i), 0);
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UML_JMPc(block, COND_E, end);
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UML_ADD(block, I0, DM_B(i), DM_L(i));
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UML_CMP(block, DM_I(i), I0);
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UML_JMPc(block, COND_LE, label2);
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UML_SUB(block, DM_I(i), DM_I(i), DM_L(i));
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UML_JMP(block, end);
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UML_LABEL(block, label2);
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UML_CMP(block, DM_I(i), DM_B(i));
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UML_JMPc(block, COND_G, end);
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UML_ADD(block, DM_I(i), DM_I(i), DM_L(i));
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UML_LABEL(block, end);
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}
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}
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void adsp21062_device::generate_astat_copy(drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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@ -1736,8 +1782,8 @@ void adsp21062_device::generate_call(drcuml_block *block, compiler_state *compil
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// compile delay slots if needed
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if (delayslot)
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{
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generate_sequence_instruction(block, &compiler_temp, desc->delay.first());
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generate_sequence_instruction(block, &compiler_temp, desc->delay.last());
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generate_sequence_instruction(block, &compiler_temp, desc->delay.first(), false);
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generate_sequence_instruction(block, &compiler_temp, desc->delay.last(), true);
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}
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if (delayslot)
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@ -1784,8 +1830,8 @@ void adsp21062_device::generate_jump(drcuml_block *block, compiler_state *compil
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// compile delay slots if needed
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if (delayslot)
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{
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generate_sequence_instruction(block, &compiler_temp, desc->delay.first());
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generate_sequence_instruction(block, &compiler_temp, desc->delay.last());
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generate_sequence_instruction(block, &compiler_temp, desc->delay.first(), false);
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generate_sequence_instruction(block, &compiler_temp, desc->delay.last(), true);
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}
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// clear interrupt
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@ -3444,8 +3490,6 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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case 0x07: // Ra = Rx + Ry, Rs = Rx - Ry
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case 0x0f: // Fa = Fx + Fy, Fs = Fx - Fy
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case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
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case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
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case 0x06: // Rm = R3-0 * R7-4 (SSFR), Ra = (R11-8 + R15-12) / 2
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case 0x08: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 + R15-12
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case 0x09: // MRF = MRF + R3-0 * R7-4 (SSF), Ra = R11-8 - R15-12
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@ -3511,6 +3555,46 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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UML_ICOPYFS(block, REG(ps), F5);
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return;
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case 0x04: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 + R15-12
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UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
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UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
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UML_DMULS(block, I0, I0, I0, I1);
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UML_DSHR(block, I0, I0, 31);
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UML_ADD(block, I2, REG(fxa), REG(fya));
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if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
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if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
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if (AV_CALC_REQUIRED) UML_SETc(block, COND_V, ASTAT_AV);
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if (AC_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AC);
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if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
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if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
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// TODO: multiplier flags
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UML_MOV(block, REG(fm), I0);
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UML_MOV(block, REG(fa), I2);
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return;
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case 0x05: // Rm = R3-0 * R7-4 (SSFR), Ra = R11-8 - R15-12
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UML_DSEXT(block, I0, REG(fxm), SIZE_DWORD);
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UML_DSEXT(block, I1, REG(fym), SIZE_DWORD);
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UML_DMULS(block, I0, I0, I0, I1);
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UML_DSHR(block, I0, I0, 31);
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UML_SUB(block, I2, REG(fxa), REG(fya));
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if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
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if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
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if (AV_CALC_REQUIRED) UML_SETc(block, COND_V, ASTAT_AV);
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if (AC_CALC_REQUIRED) UML_SETc(block, COND_C, ASTAT_AC);
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if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
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if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
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// TODO: multiplier flags
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UML_MOV(block, REG(fm), I0);
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UML_MOV(block, REG(fa), I2);
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return;
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case 0x18: // Fm = F3-0 * F7-4, Fa = F11-8 + F15-12
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// TODO: denormals
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UML_FSCOPYI(block, F0, REG(fxm));
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@ -3777,7 +3861,6 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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switch (operation)
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{
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case 0x09: // Rn = (Rx + Ry) / 2
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case 0x61: // Rn = MIN(Rx, Ry)
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case 0x63: // Rn = CLIP Rx BY Ry
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case 0x92: // Fn = ABS(Fx - Fy)
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case 0x89: // Fn = (Fx + Fy) / 2
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@ -3911,6 +3994,20 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
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return;
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case 0x61: // Rn = MIN(Rx, Ry)
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UML_MOV(block, REG(rn), REG(rx));
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UML_CMP(block, REG(rx), REG(ry));
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UML_MOVc(block, COND_G, REG(rn), REG(ry));
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if (AZ_CALC_REQUIRED || AN_CALC_REQUIRED)
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UML_CMP(block, REG(rn), 0);
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if (AZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_AZ);
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if (AN_CALC_REQUIRED) UML_SETc(block, COND_S, ASTAT_AN);
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if (AV_CALC_REQUIRED) UML_MOV(block, ASTAT_AV, 0);
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if (AC_CALC_REQUIRED) UML_MOV(block, ASTAT_AC, 0);
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if (AS_CALC_REQUIRED) UML_MOV(block, ASTAT_AS, 0);
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if (AI_CALC_REQUIRED) UML_MOV(block, ASTAT_AI, 0);
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return;
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case 0x62: // Rn = MAX(Rx, Ry)
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UML_MOV(block, REG(rn), REG(rx));
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UML_CMP(block, REG(rx), REG(ry));
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@ -4542,7 +4639,6 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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switch (operation)
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{
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case 0x04: // Rn = ASHIFT Rx BY Ry | <data8>
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case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
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case 0x44: // Rn = FDEP Rx BY Ry | <bit6>:<len6>
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case 0x4c: // Rn = FDEP Rx BY Ry | <bit6>:<len6> (SE)
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case 0x24: // Rn = Rn OR ASHIFT Rx BY Ry | <data8>
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@ -4706,8 +4802,7 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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case 0xc0: // Rn = BSET Rx BY Ry | <data8>
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{
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UML_MOV(block, I0, REG(ry));
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UML_MOV(block, I1, 1);
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UML_SHL(block, I1, I1, I0);
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UML_SHL(block, I1, 1, I0);
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UML_OR(block, REG(rn), REG(rn), I1);
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if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
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if (SV_CALC_REQUIRED)
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@ -4719,11 +4814,26 @@ void adsp21062_device::generate_compute(drcuml_block *block, compiler_state *com
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return;
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}
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case 0xc4: // Rn = BCLR Rx BY Ry | <data8>
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{
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UML_MOV(block, I0, REG(ry));
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UML_SHL(block, I1, 1, I0);
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UML_XOR(block, I1, I1, 0xffffffff);
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UML_AND(block, REG(rn), REG(rn), I1);
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if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
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if (SV_CALC_REQUIRED)
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{
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UML_CMP(block, I0, 31);
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UML_SETc(block, COND_G, ASTAT_SV);
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}
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if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
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return;
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}
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case 0xcc: // BTST Rx BY Ry | <data8>
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{
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UML_MOV(block, I0, REG(ry));
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UML_MOV(block, I1, 1);
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UML_SHL(block, I1, I1, I0);
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UML_SHL(block, I1, 1, I0);
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UML_TEST(block, REG(rx), I1);
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if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
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if (SV_CALC_REQUIRED)
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@ -4816,8 +4926,10 @@ void adsp21062_device::generate_if_condition(drcuml_block *block, compiler_state
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case 0x0d: /* TF */
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UML_TEST(block, ASTAT_BTF, 1);
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UML_JMPc(block, COND_E, skip_label);
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break;
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case 0x0e: /* BM */
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UML_JMP(block, skip_label);
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break;
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case 0x0f: /* NOT LCE */
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UML_CMP(block, CURLCNTR, 1);
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UML_JMPc(block, COND_E, skip_label);
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@ -5083,9 +5195,9 @@ void adsp21062_device::generate_shift_imm(drcuml_block *block, compiler_state *c
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case 0x02: // ROT Rx BY <data8>
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if (shift < 0)
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UML_ROL(block, REG(rn), REG(rx), shift & 0x1f);
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else
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UML_ROR(block, REG(rn), REG(rx), (-shift) & 0x1f);
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else
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UML_ROL(block, REG(rn), REG(rx), shift & 0x1f);
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if (SZ_CALC_REQUIRED) UML_SETc(block, COND_Z, ASTAT_SZ);
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if (SV_CALC_REQUIRED) UML_MOV(block, ASTAT_SV, 0);
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if (SS_CALC_REQUIRED) UML_MOV(block, ASTAT_SS, 0);
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