From 5ea843e4d012612a43373ae4b15ffea065074184 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 6 Nov 2018 06:03:20 +0100 Subject: [PATCH] m68000: show PMMU registers for 68020/030/040 in debugger --- src/devices/cpu/m68000/m68000.h | 4 +++- src/devices/cpu/m68000/m68kcpu.cpp | 34 ++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h index fcceb9b5ac7..64656832919 100644 --- a/src/devices/cpu/m68000/m68000.h +++ b/src/devices/cpu/m68000/m68000.h @@ -98,7 +98,9 @@ enum M68K_D0, M68K_D1, M68K_D2, M68K_D3, M68K_D4, M68K_D5, M68K_D6, M68K_D7, M68K_A0, M68K_A1, M68K_A2, M68K_A3, M68K_A4, M68K_A5, M68K_A6, M68K_A7, M68K_FP0, M68K_FP1, M68K_FP2, M68K_FP3, M68K_FP4, M68K_FP5, M68K_FP6, M68K_FP7, - M68K_FPSR, M68K_FPCR + M68K_FPSR, M68K_FPCR, M68K_CRP_LIMIT, M68K_CRP_APTR, M68K_SRP_LIMIT, M68K_SRP_APTR, + M68K_MMU_TC, M68K_TT0, M68K_TT1, M68K_MMU_SR, M68K_ITT0, M68K_ITT1, + M68K_DTT0, M68K_DTT1, M68K_URP_APTR }; class m68000_base_device : public cpu_device diff --git a/src/devices/cpu/m68000/m68kcpu.cpp b/src/devices/cpu/m68000/m68kcpu.cpp index 352a204b9e7..e875b377af3 100644 --- a/src/devices/cpu/m68000/m68kcpu.cpp +++ b/src/devices/cpu/m68000/m68kcpu.cpp @@ -1600,6 +1600,40 @@ void m68000_base_device::define_state(void) state_add(M68K_FPSR, "FPSR", m_fpsr); state_add(M68K_FPCR, "FPCR", m_fpcr); } + + if (m_has_pmmu) + { + state_add(M68K_MMU_TC, "TC", m_mmu_tc); + state_add(M68K_MMU_SR, "PSR", m_mmu_sr); + + if (m_cpu_type & (CPU_TYPE_010|CPU_TYPE_020)) // 68010/68020 + 68851 PMMU + { + state_add(M68K_CRP_LIMIT, "CRP_LIMIT", m_mmu_crp_limit); + state_add(M68K_CRP_APTR, "CRP_APTR", m_mmu_crp_aptr); + state_add(M68K_SRP_LIMIT, "SRP_LIMIT", m_mmu_srp_limit); + state_add(M68K_SRP_APTR, "SRP_APTR", m_mmu_srp_aptr); + } + + if (m_cpu_type & CPU_TYPE_030) + { + state_add(M68K_TT0, "TT0", m_mmu_tt0); + state_add(M68K_TT1, "TT1", m_mmu_tt1); + state_add(M68K_CRP_LIMIT, "CRP_LIMIT", m_mmu_crp_limit); + state_add(M68K_CRP_APTR, "CRP_APTR", m_mmu_crp_aptr); + state_add(M68K_SRP_LIMIT, "SRP_LIMIT", m_mmu_srp_limit); + state_add(M68K_SRP_APTR, "SRP_APTR", m_mmu_srp_aptr); + } + + if (m_cpu_type & CPU_TYPE_040) + { + state_add(M68K_ITT0, "ITT0", m_mmu_itt0); + state_add(M68K_ITT1, "ITT1", m_mmu_itt1); + state_add(M68K_DTT0, "DTT0", m_mmu_dtt0); + state_add(M68K_DTT1, "DTT1", m_mmu_dtt1); + state_add(M68K_URP_APTR, "URP", m_mmu_urp_aptr); + state_add(M68K_SRP_APTR, "SRP", m_mmu_srp_aptr); + } + } }