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https://github.com/holub/mame
synced 2025-04-23 17:00:53 +03:00
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This commit is contained in:
Angelo Salese
parent
a91bedf120
commit
5ef0be7c9d
@ -487,25 +487,28 @@ WRITE32_MEMBER(hng64_state::hng64_com_w)
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COMBINE_DATA(&m_com_ram[offset]);
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}
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WRITE32_MEMBER(hng64_state::hng64_com_share_w)
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/* TODO: fully understand this */
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WRITE8_MEMBER(hng64_state::hng64_com_share_mips_w)
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{
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logerror("commw (PC=%08x): %08x %08x %08x\n", space.device().safe_pc(), data, (offset*4)+0xc0001000, mem_mask);
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if (offset == 0x0) COMBINE_DATA(&m_com_shared_a);
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if (offset == 0x1) COMBINE_DATA(&m_com_shared_b);
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m_com_shared[offset ^ 3] = data;
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}
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READ32_MEMBER(hng64_state::hng64_com_share_r)
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READ8_MEMBER(hng64_state::hng64_com_share_mips_r)
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{
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logerror("commr (PC=%08x): %08x %08x\n", space.device().safe_pc(), (offset*4)+0xc0001000, mem_mask);
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return m_com_shared[offset];
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}
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//if(offset == 0x0) return m_com_shared_a;
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//if(offset == 0x1) return m_com_shared_b;
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WRITE8_MEMBER(hng64_state::hng64_com_share_w)
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{
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m_com_shared[offset] = data;
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}
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if(offset==0x0) return 0x0000aaaa;
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if(offset==0x1) return 0x00030000; // fatfurwa : at bfc06624 it wants a 01 : at bfc06650 it wants a 02
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READ8_MEMBER(hng64_state::hng64_com_share_r)
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{
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if(offset == 4)
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return m_com_shared[offset] | 1; // some busy flag?
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return 0x00;
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return m_com_shared[offset];
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}
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WRITE32_MEMBER(hng64_state::hng64_pal_w)
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@ -859,21 +862,38 @@ READ32_MEMBER(hng64_state::dl_r)
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}
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#endif
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// Some kind of buffering of the display lists, or 'render current buffer' write?
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WRITE32_MEMBER(hng64_state::dl_control_w)
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WRITE32_MEMBER(hng64_state::dl_upload_w)
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{
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// printf("\n"); // Debug - ajg
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// TODO: put this back in.
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/*
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if (activeBuffer==0 || activeBuffer==1)
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memcpy(&hng64_dls[activeBuffer][0],&hng64_dl[0],0x200);
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// this handles 3d to fb upload
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#if 0
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UINT16 packet3d[16];
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// Only if it's VALID (hack)
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if (data & 1)
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activeBuffer = 0;
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if (data & 2)
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activeBuffer = 1;
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*/
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for(int packetStart=0;packetStart<0x200/4;packetStart+=8)
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{
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// Create a 3d packet
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//UINT16 packetStart = offset - 0x08;
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//if (offset == 0x7f) packetStart += 1;
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for (int i = 0; i < 0x08; i++)
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{
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packet3d[i*2+0] = (m_dl[packetStart+i] & 0xffff0000) >> 16;
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packet3d[i*2+1] = (m_dl[packetStart+i] & 0x0000ffff);
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}
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// Send it off to the 3d subsystem.
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hng64_command3d(machine(), packet3d);
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}
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#endif
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}
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WRITE32_MEMBER(hng64_state::dl_control_w) // This handles framebuffers
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{
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if(data & 2) // clear current buffer
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clear3d();
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// if(data & 1) // swap buffers
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// if(data & 4) // reset buffer count
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}
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#ifdef UNUSED_FUNCTION
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@ -1141,7 +1161,7 @@ static ADDRESS_MAP_START( hng_map, AS_PROGRAM, 32, hng64_state )
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AM_RANGE(0x20200000, 0x20203fff) AM_RAM_WRITE(hng64_pal_w) AM_SHARE("paletteram")
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AM_RANGE(0x20208000, 0x2020805f) AM_READWRITE(tcram_r, tcram_w) AM_SHARE("tcram") // Transition Control
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AM_RANGE(0x20300000, 0x203001ff) AM_RAM_WRITE(dl_w) AM_SHARE("dl") // 3d Display List
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// AM_RANGE(0x20300200, 0x20300213) AM_RAM_WRITE(xxxx) AM_SHARE("xxxxxxxx") // 3d Display List Upload?
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AM_RANGE(0x20300200, 0x20300213) AM_WRITE(dl_upload_w) // 3d Display List Upload
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AM_RANGE(0x20300214, 0x20300217) AM_WRITE(dl_control_w)
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AM_RANGE(0x20300218, 0x2030021b) AM_READ(unk_vreg_r)
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@ -1162,7 +1182,7 @@ static ADDRESS_MAP_START( hng_map, AS_PROGRAM, 32, hng64_state )
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// Communications
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AM_RANGE(0xc0000000, 0xc0000fff) AM_READWRITE(hng64_com_r, hng64_com_w) AM_SHARE("com_ram")
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AM_RANGE(0xc0001000, 0xc0001007) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
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AM_RANGE(0xc0001000, 0xc0001007) AM_READWRITE8(hng64_com_share_mips_r, hng64_com_share_mips_w,0xffffffff)
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/* 6e000000-6fffffff */
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/* 80000000-81ffffff */
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@ -1172,165 +1192,109 @@ static ADDRESS_MAP_START( hng_map, AS_PROGRAM, 32, hng64_state )
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/* a0000000-a3ffffff */
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ADDRESS_MAP_END
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/**************/
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/** COMM CPU **/
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/**************/
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#define KL5C_MMU_A(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[((xxx-1)*2)+1] << 2) | ((state->m_com_mmu_mem[(xxx-1)*2] & 0xc0) >> 6) )
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#define KL5C_MMU_B(xxx) ( (xxx == 0) ? 0x0000 : (state->m_com_mmu_mem[(xxx-1)*2] & 0x3f) )
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/*
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0x6010: tests RAM at [3]8000
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DIRECT_UPDATE_MEMBER(hng64_state::KL5C80_direct_handler)
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*/
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UINT8 hng64_state::read_comm_data(UINT32 offset)
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{
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direct.explicit_configure(0x0000, 0xffff, 0xffff, m_com_op_base);
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return ~0;
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if((offset & 0x10000) == 0)
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return m_comm_rom[offset & 0xffff];
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if(offset & 0x10000)
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return m_comm_ram[(offset & 0xffff)];
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printf("%08x\n",offset);
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return 0xff;
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}
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static UINT32 KL5C80_translate_address(hng64_state *state, UINT16 vAddr)
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void hng64_state::write_comm_data(UINT32 offset,UINT8 data)
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{
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int i;
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UINT8 bNum = 4;
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/* Determine what B the vAddr is in */
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for (i = 1; i < 5; i++)
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if((offset & 0x10000) == 0)
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{
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if ( ((KL5C_MMU_B(i)+1)*0x400) > vAddr)
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{
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bNum = i-1;
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break;
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}
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//m_comm_rom[offset];
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return;
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}
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if(offset & 0x10000)
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{
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m_comm_ram[offset & 0xffff] = data;
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return;
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}
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/* Calculate the full address and return */
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if (bNum == 0)
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{
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return vAddr;
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}
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else
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{ /* the offset to the base physical address plus the vAddr's offset from the virtual base */
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return ((KL5C_MMU_A(bNum) + (KL5C_MMU_B(bNum)+1)) * 0x400) + (vAddr - ((KL5C_MMU_B(bNum)+1) * 0x400));
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}
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printf("%08x %02x\n",offset,data);
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}
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static void KL5C80_virtual_mem_sync(hng64_state *state)
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READ8_MEMBER(hng64_state::hng64_comm_space_r)
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{
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/* The KL5C80 maps each progressive chunk from the beginning of the
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virtual region until the beginning of the next virtual region.
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This is implemented here in a lame way to simplify the code. */
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if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
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return m_comm_rom[offset];
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int i,region;
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for (region = 0; region < 5; region++)
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for(int i=0;i<5;i++)
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{
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int logical_offset = (KL5C_MMU_B(region)+1) * 0x400;
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int physical_offset = (KL5C_MMU_A(region) + (KL5C_MMU_B(region)+1)) * 0x400;
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if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
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return read_comm_data(m_mmua[i]|offset);
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}
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/* The first MMU region is a special case */
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if (region == 0)
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{
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logical_offset = 0x0000;
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physical_offset = 0x00000;
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}
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return 0xff;
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}
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logerror("Now copying 0x%x to 0x%x\n", physical_offset, logical_offset);
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for (i = logical_offset; i <= 0xffff; i++)
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WRITE8_MEMBER(hng64_state::hng64_comm_space_w)
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{
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if((offset & 0xfc00) == 0) // B0 is fixed at 0-0x3ff
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return;// m_comm_rom[offset];
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for(int i=0;i<5;i++)
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{
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if(offset >= m_mmub[i] && offset <= m_mmub[i+1]-1)
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{
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if (physical_offset+i <= 0xfffff)
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state->m_com_op_base[i] = state->m_com_virtual_mem[physical_offset+i];
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write_comm_data(m_mmua[i]|offset,data);
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return;
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}
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}
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}
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static void KL5C80_init(hng64_state *state)
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READ8_MEMBER(hng64_state::hng64_comm_mmu_r)
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{
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UINT8 *hng64_com_mmu_mem = state->m_com_mmu_mem;
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/* init the MMU */
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hng64_com_mmu_mem[0] =
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hng64_com_mmu_mem[2] =
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hng64_com_mmu_mem[4] =
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hng64_com_mmu_mem[6] = 0x3f;
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hng64_com_mmu_mem[1] =
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hng64_com_mmu_mem[3] =
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hng64_com_mmu_mem[5] = 0x00;
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hng64_com_mmu_mem[7] = 0xf0;
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return m_mmu_regs[offset];
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}
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READ8_MEMBER(hng64_state::hng64_comm_memory_r)
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{
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hng64_state *state = machine().driver_data<hng64_state>();
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UINT32 physical_address = KL5C80_translate_address(state, offset);
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logerror("READING 0x%02x from 0x%04x (0x%05x)\n", m_com_virtual_mem[physical_address], offset, physical_address);
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#define MMUA (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2)
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#define MMUB (m_mmu_regs[(offset&~1)+0]&0x3f)
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/* Custom "virtual" memory map */
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if (physical_address >= 0x26000 && physical_address <= 0x28000)
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WRITE8_MEMBER(hng64_state::hng64_comm_mmu_w)
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{
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m_mmu_regs[offset] = data;
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/* cheap: avoid to overwrite read only params*/
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if((offset & 6) == 6)
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{
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/* May very well be shared memory - it reads 16 bits from it at 0x309 */
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m_mmu_regs[6] = m_mmu_regs[6] & 0x3f;
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m_mmu_regs[7] = 0xf0;
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}
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return m_com_virtual_mem[physical_address];
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{
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m_mmua[offset/2+1] = (m_mmu_regs[(offset&~1)+0]>>6)|(m_mmu_regs[(offset&~1)+1]<<2);
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m_mmua[offset/2+1]*= 0x400;
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m_mmub[offset/2+1] = (m_mmu_regs[(offset&~1)+0]&0x3f);
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m_mmub[offset/2+1]++;
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m_mmub[offset/2+1]*= 0x400;
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//printf("%d A %08x B %04x\n",offset/2,m_mmua[offset/2],m_mmub[offset/2]);
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//printf("A %04x B %02x\n",MMUA,MMUB);
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}
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}
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WRITE8_MEMBER(hng64_state::hng64_comm_memory_w)
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{
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// Write to both virtual and physical memory
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// UINT32 physical_address = KL5C80_translate_address(offset);
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// logerror("WRITING 0x%02x to 0x%04x (0x%05x)\n", hng64_com_virtual_mem[physical_address], offset, physical_address);
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}
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/* KL5C80 I/O handlers */
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WRITE8_MEMBER(hng64_state::hng64_comm_io_mmu)
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{
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m_com_mmu_mem[offset] = data;
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/* Debugging - you can't change A4 - the hardware doesn't let you */
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if (m_com_mmu_mem[7] != 0xf0 || ((m_com_mmu_mem[6] & 0xc0) != 0x00))
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logerror("KL5C MMU error !!! Code is trying to change A4!\n");
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hng64_state *state = machine().driver_data<hng64_state>();
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logerror("COMM CPU MMU WRITE : ");
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logerror("B : %02x %02x %02x %02x A : %03x %03x %03x %03x\n", KL5C_MMU_B(1), KL5C_MMU_B(2), KL5C_MMU_B(3), KL5C_MMU_B(4),
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KL5C_MMU_A(1), KL5C_MMU_A(2), KL5C_MMU_A(3), KL5C_MMU_A(4));
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KL5C80_virtual_mem_sync(state);
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}
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#ifdef UNUSED_FUNCTION
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READ8_MEMBER(hng64_state::hng64_comm_shared_r)
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{
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// I'm thinking 0x54 comes from an interrupt on the MIPS CPU? Or maybe the Toshiba one?
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// Nothing from CPU0 seems to ping the COM CPU as often as it reads 0x54.
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// Sometimes it wants 0x54 to be a 0x01 and sometimes it wants a 0x02.
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// It's not an interrupt on the KL5C80 because they aren't enabled before 0x54 is ping'ed
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// There is a special onboard interrupt handler for the KL5C80 though...
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if (offset==0x00) logerror("COM CPU reading from 0x50.\n");
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if (offset==0x01) logerror("COM CPU reading from 0x51.\n");
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if (offset==0x02) logerror("COM CPU reading from 0x52.\n");
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if (offset==0x03) logerror("COM CPU reading from 0x53.\n");
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if (offset==0x04) (hng64_com_shared_b & 0x000000ff) ? return 0xff : return 0x00;
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}
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WRITE8_MEMBER(hng64_state::hng64_comm_shared_w)
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{
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if (offset==0x00) hng64_com_shared_a = (hng64_com_shared_a & 0x00ffffff) | (data << 24);
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if (offset==0x01) hng64_com_shared_a = (hng64_com_shared_a & 0xff00ffff) | (data << 16);
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if (offset==0x02) hng64_com_shared_a = (hng64_com_shared_a & 0xffff00ff) | (data << 8);
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if (offset==0x03) hng64_com_shared_a = (hng64_com_shared_a & 0xffffff00) | (data << 0);
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if (offset==0x04) logerror("COM CPU writing to 0x54.\n");
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logerror("COM CPU wrote to com_shared_a : %08x\n", hng64_com_shared_a);
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}
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#endif
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static ADDRESS_MAP_START( hng_comm_map, AS_PROGRAM, 8, hng64_state )
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AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_memory_r, hng64_comm_memory_w )
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AM_RANGE(0x0000,0xffff) AM_READWRITE(hng64_comm_space_r, hng64_comm_space_w )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( hng_comm_io_map, AS_IO, 8, hng64_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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/* Reserved for the KL5C80 internal hardware */
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AM_RANGE(0x00, 0x07) AM_WRITE(hng64_comm_io_mmu ) AM_SHARE("com_mmu_mem")
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AM_RANGE(0x00, 0x07) AM_READWRITE(hng64_comm_mmu_r,hng64_comm_mmu_w )
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// AM_RANGE(0x08,0x1f) AM_NOP /* Reserved */
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// AM_RANGE(0x20,0x25) AM_READWRITE /* Timer/Counter B */ /* hng64 writes here */
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// AM_RANGE(0x27,0x27) AM_NOP /* Reserved */
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@ -1343,7 +1307,7 @@ static ADDRESS_MAP_START( hng_comm_io_map, AS_IO, 8, hng64_state )
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// AM_RANGE(0x3c,0x3f) AM_NOP /* Reserved */
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/* General IO */
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AM_RANGE(0x50,0x54) AM_NOP // AM_WRITE(hng64_comm_shared_r, hng64_comm_shared_w)
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AM_RANGE(0x50,0x57) AM_READWRITE(hng64_com_share_r, hng64_com_share_w)
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// AM_RANGE(0x72,0x72) AM_WRITE /* dunno yet */
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ADDRESS_MAP_END
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@ -1748,7 +1712,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(hng64_state::hng64_irq)
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case 224*2: m_set_irq(0x0001); break; // lv 0 vblank irq
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//case 0*2: m_set_irq(0x0002); break; // lv 1
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//case 64*2: m_set_irq(0x0004); break; // lv 2
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case 128*2: m_set_irq(0x0800); break; // lv 11 network irq?
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case 128*2: m_set_irq(0x0800); break; // lv 11 network irq?
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}
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}
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@ -1762,14 +1726,14 @@ void hng64_state::machine_start()
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mips3drc_add_fastram(m_maincpu, 0x00000000, 0x00ffffff, FALSE, m_mainram);
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mips3drc_add_fastram(m_maincpu, 0x04000000, 0x05ffffff, TRUE, m_cart);
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mips3drc_add_fastram(m_maincpu, 0x1fc00000, 0x1fc7ffff, TRUE, m_rombase);
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|
||||
m_comm_rom = memregion("user2")->base();
|
||||
m_comm_ram = auto_alloc_array(machine(),UINT8,0x10000);
|
||||
}
|
||||
|
||||
|
||||
void hng64_state::machine_reset()
|
||||
{
|
||||
int i;
|
||||
const UINT8 *rom = memregion("user2")->base();
|
||||
|
||||
/* Sound CPU */
|
||||
UINT8 *RAM = (UINT8*)m_soundram;
|
||||
membank("bank1")->set_base(&RAM[0x1f0000]); // allows us to boot
|
||||
@ -1777,27 +1741,18 @@ void hng64_state::machine_reset()
|
||||
m_audiocpu->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
|
||||
m_audiocpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
|
||||
|
||||
/* Comm CPU */
|
||||
KL5C80_init(this);
|
||||
|
||||
/* Fill up virtual memory with ROM */
|
||||
for (i = 0x0; i < 0x100000; i++)
|
||||
m_com_virtual_mem[i] = rom[i];
|
||||
|
||||
KL5C80_virtual_mem_sync(this);
|
||||
|
||||
address_space &space = m_comm->space(AS_PROGRAM);
|
||||
space.set_direct_update_handler(direct_update_delegate(FUNC(hng64_state::KL5C80_direct_handler), this));
|
||||
|
||||
m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE); // reset the CPU and let 'er rip
|
||||
// m_comm->set_input_line(INPUT_LINE_RESET, PULSE_LINE); // reset the CPU and let 'er rip
|
||||
// m_comm->set_input_line(INPUT_LINE_HALT, ASSERT_LINE); // hold on there pardner...
|
||||
|
||||
// "Display List" init - ugly
|
||||
m_activeBuffer = 0;
|
||||
// m_activeBuffer = 0;
|
||||
|
||||
/* For simulate MCU stepping */
|
||||
m_mcu_fake_time = 0;
|
||||
m_mcu_en = 0;
|
||||
|
||||
m_mmub[0] = 0;
|
||||
m_mmub[5] = 0; // rolls back to 0xffff
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -28,8 +28,8 @@ public:
|
||||
m_3dregs(*this, "3dregs"),
|
||||
m_3d_1(*this, "3d_1"),
|
||||
m_3d_2(*this, "3d_2"),
|
||||
m_com_ram(*this, "com_ram"),
|
||||
m_com_mmu_mem(*this, "com_mmu_mem"){ }
|
||||
m_com_ram(*this, "com_ram")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<cpu_device> m_audiocpu;
|
||||
@ -52,7 +52,7 @@ public:
|
||||
required_shared_ptr<UINT32> m_3d_2;
|
||||
|
||||
required_shared_ptr<UINT32> m_com_ram;
|
||||
required_shared_ptr<UINT8> m_com_mmu_mem;
|
||||
//required_shared_ptr<UINT8> m_com_mmu_mem;
|
||||
|
||||
|
||||
int m_mcu_type;
|
||||
@ -63,8 +63,7 @@ public:
|
||||
/* Communications stuff */
|
||||
UINT8 *m_com_op_base;
|
||||
UINT8 *m_com_virtual_mem;
|
||||
UINT32 m_com_shared_a;
|
||||
UINT32 m_com_shared_b;
|
||||
UINT8 m_com_shared[8];
|
||||
|
||||
INT32 m_dma_start;
|
||||
INT32 m_dma_dst;
|
||||
@ -126,8 +125,10 @@ public:
|
||||
DECLARE_READ32_MEMBER(hng64_random_read);
|
||||
DECLARE_READ32_MEMBER(hng64_com_r);
|
||||
DECLARE_WRITE32_MEMBER(hng64_com_w);
|
||||
DECLARE_WRITE32_MEMBER(hng64_com_share_w);
|
||||
DECLARE_READ32_MEMBER(hng64_com_share_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_com_share_w);
|
||||
DECLARE_READ8_MEMBER(hng64_com_share_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_com_share_mips_w);
|
||||
DECLARE_READ8_MEMBER(hng64_com_share_mips_r);
|
||||
DECLARE_WRITE32_MEMBER(hng64_pal_w);
|
||||
DECLARE_READ32_MEMBER(hng64_sysregs_r);
|
||||
DECLARE_WRITE32_MEMBER(hng64_sysregs_w);
|
||||
@ -143,11 +144,11 @@ public:
|
||||
DECLARE_WRITE32_MEMBER(dl_w);
|
||||
DECLARE_READ32_MEMBER(dl_r);
|
||||
DECLARE_WRITE32_MEMBER(dl_control_w);
|
||||
DECLARE_WRITE32_MEMBER(dl_upload_w);
|
||||
DECLARE_WRITE32_MEMBER(tcram_w);
|
||||
DECLARE_READ32_MEMBER(tcram_r);
|
||||
DECLARE_READ32_MEMBER(unk_vreg_r);
|
||||
DECLARE_WRITE32_MEMBER(hng64_soundram_w);
|
||||
|
||||
DECLARE_READ32_MEMBER(hng64_soundram_r);
|
||||
|
||||
// not actually used, but left in code so you can turn it and see the (possibly undesired?) behavior, see notes in memory map
|
||||
@ -158,16 +159,16 @@ public:
|
||||
|
||||
DECLARE_WRITE32_MEMBER(hng64_sprite_clear_even_w);
|
||||
DECLARE_WRITE32_MEMBER(hng64_sprite_clear_odd_w);
|
||||
DECLARE_READ8_MEMBER(hng64_comm_memory_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_memory_w);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_io_mmu);
|
||||
DECLARE_WRITE32_MEMBER(trap_write);
|
||||
DECLARE_WRITE32_MEMBER(hng64_3d_1_w);
|
||||
DECLARE_WRITE32_MEMBER(activate_3d_buffer);
|
||||
DECLARE_READ8_MEMBER(hng64_comm_shared_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_shared_w);
|
||||
DECLARE_WRITE32_MEMBER(hng64_videoram_w);
|
||||
DECLARE_DIRECT_UPDATE_MEMBER(KL5C80_direct_handler);
|
||||
DECLARE_READ8_MEMBER(hng64_comm_space_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_space_w);
|
||||
DECLARE_READ8_MEMBER(hng64_comm_mmu_r);
|
||||
DECLARE_WRITE8_MEMBER(hng64_comm_mmu_w);
|
||||
DECLARE_DRIVER_INIT(hng64_race);
|
||||
DECLARE_DRIVER_INIT(fatfurwa);
|
||||
DECLARE_DRIVER_INIT(hng64);
|
||||
@ -178,6 +179,13 @@ public:
|
||||
|
||||
void m_set_irq(UINT32 irq_vector);
|
||||
UINT32 m_irq_pending;
|
||||
UINT8 *m_comm_rom;
|
||||
UINT8 *m_comm_ram;
|
||||
UINT8 m_mmu_regs[8];
|
||||
UINT32 m_mmua[6];
|
||||
UINT16 m_mmub[6];
|
||||
UINT8 read_comm_data(UINT32 offset);
|
||||
void write_comm_data(UINT32 offset,UINT8 data);
|
||||
int m_irq_level;
|
||||
TILE_GET_INFO_MEMBER(get_hng64_tile0_8x8_info);
|
||||
TILE_GET_INFO_MEMBER(get_hng64_tile0_16x16_info);
|
||||
@ -193,6 +201,9 @@ public:
|
||||
UINT32 screen_update_hng64(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
void screen_eof_hng64(screen_device &screen, bool state);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(hng64_irq);
|
||||
|
||||
void clear3d();
|
||||
|
||||
};
|
||||
|
||||
/*----------- defined in video/hng64.c -----------*/
|
||||
|
||||
@ -5,7 +5,6 @@
|
||||
#define MAKE_MAME_REEEEAAALLLL_SLOW 0
|
||||
|
||||
|
||||
static void clear3d(running_machine &machine); // TODO: Inline
|
||||
|
||||
|
||||
static void hng64_mark_all_tiles_dirty( hng64_state *state, int tilemap )
|
||||
@ -1633,8 +1632,8 @@ UINT32 hng64_state::screen_update_hng64(screen_device &screen, bitmap_rgb32 &bit
|
||||
void hng64_state::screen_eof_hng64(screen_device &screen, bool state)
|
||||
{
|
||||
// rising edge
|
||||
if (state)
|
||||
clear3d(machine());
|
||||
//if (state)
|
||||
// clear3d();
|
||||
}
|
||||
|
||||
void hng64_state::video_start()
|
||||
@ -2514,7 +2513,7 @@ void hng64_command3d(running_machine& machine, const UINT16* packet)
|
||||
int numPolys = 0;
|
||||
struct polygon* polys = auto_alloc_array(machine, struct polygon, 1024*5);
|
||||
|
||||
//printf("packet type : %04x\n", packet[0]);
|
||||
//printf("packet type : %04x %04x|%04x %04x|%04x %04x|%04x %04x\n", packet[0],packet[1],packet[2],packet[3],packet[4],packet[5],packet[6],packet[7]);
|
||||
switch (packet[0])
|
||||
{
|
||||
case 0x0000: // Appears to be a NOP.
|
||||
@ -2601,31 +2600,30 @@ void hng64_command3d(running_machine& machine, const UINT16* packet)
|
||||
auto_free(machine, polys);
|
||||
}
|
||||
|
||||
static void clear3d(running_machine &machine)
|
||||
void hng64_state::clear3d()
|
||||
{
|
||||
hng64_state *state = machine.driver_data<hng64_state>();
|
||||
int i;
|
||||
|
||||
const rectangle &visarea = machine.primary_screen->visible_area();
|
||||
const rectangle &visarea = machine().primary_screen->visible_area();
|
||||
|
||||
// Clear each of the display list buffers after drawing - todo: kill!
|
||||
for (i = 0; i < 0x81; i++)
|
||||
{
|
||||
state->m_dls[0][i] = 0;
|
||||
state->m_dls[1][i] = 0;
|
||||
m_dls[0][i] = 0;
|
||||
m_dls[1][i] = 0;
|
||||
}
|
||||
|
||||
// Reset the buffers...
|
||||
for (i = 0; i < (visarea.max_x)*(visarea.max_y); i++)
|
||||
{
|
||||
state->m_depthBuffer3d[i] = 100.0f;
|
||||
state->m_colorBuffer3d[i] = MAKE_ARGB(0, 0, 0, 0);
|
||||
m_depthBuffer3d[i] = 100.0f;
|
||||
m_colorBuffer3d[i] = MAKE_ARGB(0, 0, 0, 0);
|
||||
}
|
||||
|
||||
// Set some matrices to the identity...
|
||||
setIdentity(state->m_projectionMatrix);
|
||||
setIdentity(state->m_modelViewMatrix);
|
||||
setIdentity(state->m_cameraMatrix);
|
||||
setIdentity(m_projectionMatrix);
|
||||
setIdentity(m_modelViewMatrix);
|
||||
setIdentity(m_cameraMatrix);
|
||||
}
|
||||
|
||||
/* 3D/framebuffer video registers
|
||||
@ -2634,6 +2632,8 @@ static void clear3d(running_machine &machine)
|
||||
* UINT32 | Bits | Use
|
||||
* | 3322 2222 2222 1111 1111 11 |
|
||||
* -------+-1098-7654-3210-9876-5432-1098-7654-3210-+----------------
|
||||
* 0 | ---- --x- ---- ---- ---- ---- ---- ---- | Reads in Fatal Fury WA, if on then there isn't a 3d refresh (busy flag?).
|
||||
* 0 | ---- ---x ---- ---- ---- ---- ---- ---- | set at POST, probably 3d disable
|
||||
* 0 | ???? ???? ???? ???? ccc? ???? ???? ???? | framebuffer color base, 0x311800 in Fatal Fury WA, 0x313800 in Buriki One
|
||||
* 1 | |
|
||||
* 2 | ???? ???? ???? ???? ???? ???? ???? ???? | camera / framebuffer global x/y? Actively used by Samurai Shodown 64 2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user